High-Gain Class-AB OTA with Low Quiescent Current

High-performance operational transconductance amplifier (OTA) is designed for switched-capacitor applications. Without using a cascoded output stage, which limits the voltage swing, the output resistance is significantly increased for high DC gain by accurately controlling the output current. Also, the output stage has class-AB operation, so the overall power efficiency is improved. With significantly low quiescent current, the presented new OTA achieves higher DC gain than conventional OTAs. Theoretical analysis and HSPICE simulations prove the performance of the new OTA.     

一种低电压的全差分OTA

文章介绍了一种低电压的全差分OTA的实现，通过电流驱动体效应（CDB）使低电源电压OTA设计成为可能。提出了一种新的共模反馈结构（CMFB）实现了全差分输出，提高了OTA的输出范围。文章采用0．18um CMOS工艺库。SPICE仿真结果表明：在电源电压为800mV时，OTA的增益为59．2DB，单位增益带宽为14．3MHz．输出范围为674mV．     

Ultra Low Power Improved Differential Amplifier

In this paper, a low voltage and ultra low power operational transconductance amplifier (OTA) is presented. As will be shown, the transient response and open loop gain of the proposed OTA are improved using adaptive biasing and DC gain enhancement techniques. The contributions of the proposed OTA are ultra low power consumption (only 3.977 μw), low supply voltages (±0.6 V), high swing, high speed, and high gain. It can clearly be seen that for the proposed OTA, the gain of the differential half-circuit in the input stage (A _d ), DC gain (A ₀), gain bandwidth (GBW), and slew rate (SR) are increased, whereas the settling time (T _S ) is decreased. The results of simulations done using 0.18 μm Silterra CMOS process technology and the measurement results are presented to validate and compare the advantages of this work and other related works.     

Ultra low voltage, high performance operational transconductance amplifier and its application in a tunable Gm-C filter

This paper presents an ultra low voltage, high performance Operational Transconductance Amplifier (OTA) and its application to implement a tunable Gm-C filter. The proposed OTA uses a 0.5 V single supply and consumes 60 μw. Employing special CMFF and CMFB circuits has improved CMRR to 138 dB in DC. Using bulk driven input stage results in higher linearity such that by applying a 500 mv_p-p sine wave input signal at 2 MHz frequency in unity gain closed loop configuration, third harmonic distortion for output voltage is −46 dB and becomes −42.4 dB in open loop state for 820 mv_p-p output voltage at 2 MHz. DC gain of the OTA is 47 dB and its unity gain bandwidth is 17.8 MHz with 20 pF capacitance load due to both deliberately optimized design and special frequency compensation technique. The OTA has been used to realize a wide tunable Gm-C low-pass filter whose cutoff frequency is tunable from 1.4 to 6 MHz. Proposed OTA and filter have been simulated in 0.18 μm TSMC CMOS technology with Hspice. Monte Carlo and temperature dependent simulation results are included to forecast the mismatch and temperature effects after fabrication process.     

A power efficient gain enhancing technique for current mirror operational transconductance amplifiers

In this paper, a power efficient voltage gain enhancing technique is described. This technique is suitable for the amplifiers which use current starving method for gain enhancement (explained in the text). The proposed technique makes use of the current which conventionally goes to ground, through a parallel path. In this paper, the new technique is demonstrated for current mirror type of operational transconductance amplifier (OTA). Simulation results show that gain improves by a factor ~2, while consuming the same power as conventional OTA. The added advantage of this technique is that it does not affect the voltage swing while increasing the gain. Compared to the conventional current starving technique, the proposed technique also improves the noise performance and settling speed of the amplifier. The results are compared with the conventional technique, in terms of gain, settling and noise performance. A comparison of FoM (MHz.pF/mA), with other amplifiers, is given at the end as well.     

A 1.1 mW 87 dB dynamic range ΔΣ modulator for audio applications

This paper presents a 1.1 mW 87 dB dynamic range third order AS modulator implemented in 0.18 μm CMOS technology for audio applications.By adopting a feed-forward multi-bit topology,the signal swing at the output of the first integrator can be suppressed.A simple current mirror single stage OTA with 34 dB DC gain working under 1 V power supply is used in the first integrator.The prototype modulator achieves 87 dB DR and 83.8 dB peak SNDR across the bandwidth from 100 Hz to 24 kHz with 3 kHz input signal.     

A fully-differential OTA based on CMOS cascode inverters operating from 1-V power supply

A low voltage operating fully-differential CMOS OTA construction, which uses dual-input CMOS cascode inverters, is proposed. The OTA is a two-stage configuration with dual-input CMOS cascode inverters at the input stage, and traditional CMOS inverters in the output stage, with a common-mode feedback path from the output terminals to one of the input terminals of cascode inverters. In order to effectively reduce its threshold voltages by bulk bias technique, the OTA has been designed and fabricated by using a 0.15 μm triple-well CMOS process. The OTA successfully operated from 1-V power supply, with 59 dB of differential voltage gain, 80.9 dB of CMRR and 25 MHz of unity gain frequency, at 60 μA of current consumption.     

A 0.8-V 0.25-mW Current-Mirror OTA With 160-MHz GBW in 0.18-μm CMOS

A low-voltage low-power CMOS operational transconductance amplifier (OTA) with near rail-to-rail output swing is presented in this brief. The proposed circuit is based on the current-mirror OTA topology. In addition, several circuit techniques are adopted to enhance the voltage gain. Simulated from a 0.8-V supply voltage, the proposed OTA achieves a 62-dB dc gain and a gain-bandwidth product of 160 MHz while driving a 2-pF load. The OTA is designed in a 0.18-mum CMOS process. The power consumption is 0.25 mW including the common-mode feedback circuit     

On the design of a low-voltage two-stage OTA using bulk-driven and positive feedback techniques

This article presents the design and simulation of a fully differential two-stage operational transconductance amplifier (OTA) in a 0.18?µm CMOS process with a 0.9?V supply voltage. For this purpose, both the bulk-driven and positive feedback techniques are employed. These techniques increase the DC gain by about 18.5?dB without consuming more power and changing the unity-gain bandwidth and phase margin of the OTA.     

Improving GBW product on CMOS operational transconductance amplifiers by interleaved feedforward paths

This paper presents two Operational Transconductance Amplifier (OTA) compensation schemes for multistage topologies. The solutions are based on interleaved feedforward paths that cancel a non-dominant pole similarly to the zero nulling resistor technique with the advantage of avoiding resistors. Both schemes are designed in 90 nm CMOS process, the first one obtains 71 dB of DC gain, a gain bandwidth product (GBW) of 720 MHz with 360 μW of power consumption. The second proposed scheme obtains a similar DC gain and doubles the former proposed OTA GBW at the expense of 2.2 mW of power consumption for high speed applications. The compensation schemes are theoretically analyzed and the design guidelines are presented. The results of post layout simulations and corner analysis validate the new solutions.     

High current efficiency single-stage bulk-driven subthreshold-biased class-AB OTAs with enhanced transconductance and slew rate for large capacitive loads

This paper introduces two high-performance single-stage bulk-driven (BD) operational transconductance amplifiers (OTA) in weak-inversion with rail-to-rail input and output voltage ranges suited for the excessively low-voltage of 0.5 V supply. The strategy depends on adopting a modified bulk-driven non-tailed input core to achieve high input core transconductance with a minimum power supply and an enhanced input common-mode range. Moreover, a partial positive feedback loop provides an overall improved DC gain and effective transconductance further. The input core of OTA1, named composite class-AB OTA, comprises two combined non-tailed differential pairs as composite differential pairs. The proposed OTA2, named composite super class-AB BD-OTA, exploits a matched bulk-input Flipped voltage follower (FVF) pair to adaptively bias the input core used in the composite class-AB BD OTA. As a result, a significant increase in large-signal input current to the output side due to super class-AB behavior improves the slew rate. The post-layout simulation results using the Cadence Spectre simulator with UMC 0.18 µm process technology confirm that the proposed OTAs have improved small-signal and large-signal performances over the conventional OTA driving a high capacitive load of 5 nF. The proposed composite class-AB and super class-AB BD OTA deliver 2.29 times, and 3.77 times open-loop DC gain, 10.6 times, and 117 times unity-gain bandwidth with 2 times, and 12.03 times slew rate at the expense of almost 0.52 times and 1.21 times power consumed over conventional counterpart, respectively.

     

Design of 0.5 V voltage-combiner based OTA with 60 dB gain 250 kHz UGB in CMOS

A gain enhancement technique for a pseudo differential OTA based on voltage combiner, suitable for sub-1 V supply is presented in this letter. The proposed technique uses a G _m boosted voltage combiner. Unlike the typical voltage combiner which has an approximated gain of \(2\,\frac{{\text{V}}}{{\text{V}}}\), this voltage combiner can produce gain more than \(5\,\frac{{\text{V}}}{{\text{V}}}\). So it help us achieve nearly 60 dB DC gain with 250 kHz UGB for the pseudo differential OTA at a capacitive load of 10 pF. Power dissipation is very low i.e. 716 nW at supply of 0.5 V. So as to facilitate maximum swing at 0.5 V supply and lower the power consumption, MOS transistors are biased in weak/moderate inversion. The OTA is designed in standard 45 nm CMOS process. Phase margin of is more than \(55^{\circ }\) for a typical load of 10 pF. The input referred noise is \(150\,\upmu {\text{V}}{/}\sqrt{{\text{Hz}}}\) at 10 Hz and slew rate \(0.02\,{\text{V}}{/}\upmu{\text{s}}\) for 10 pF load.     

On the realization of electronically current-tunable CMOS OTA

A CMOS operational transconductance amplifier (OTA) called as an EOTA, where its transconductance gain can be electronically and linearly tuned is proposed in this paper. The realization method is achieved by squaring the transconductance gain of the balanced CMOS OTA. The EOTA transconductance gain can be linearly tuned by an external bias current for three decades. The linear input-voltage range of about 1 Vp with less than 1% nonlinearity is obtained. The usefulness of the proposed EOTA is demonstrated through application example with a current multiplier. The performance of the proposed circuit is discussed and confirmed through PSPICE-simulation results.     

应用于高Q跨导-电容带通滤波器的线性跨导运放设计

设计了一种具有高的直流增益的宽带线性全差分跨导运放.一方面,并联一个工作在线性区的场效应管来补偿直流三阶系数,得到了一种应用于连续时间滤波器、增加跨导器饱和区输入信号幅度的简单方法.另一方面,结合负电阻电路提高了输出阻抗,实现高的直流增益而不需要额外的内部结点,并减小了因有限直流增益和寄生电容引起的相位偏差.将此全差分跨导运放应用于0.18μmCMOS工艺二阶带通滤波器,在3.3V电源电压、输入峰峰值1V时,HSPICE仿真结果的总谐波失真小于40dB,中心频率为20MHz,3dB带宽为0.18MHz,即Q为110.     

10bit 100M低功耗时间交织运放共享模数转换器设计

本文设计了一个应用于3G接收机中频的10比特100兆采样率的双通道时间交织流水线模数转换器,为了降低功耗,运放在两通道间共享。针对通道间的直流失调失配,增益失配以及采样时间偏差,设计分别采用共享运放,增加每个通道转换精度以及全局采样技术来加以解决。通过改变时序,消除了输出开关电荷注入以及断开开关的电容造成的串扰,从而提高了整个模数转换器的线性度。整个模数转换器的供电电压为3.3V,功耗为70毫瓦,采用了180纳米CMOS工艺,面积为3×2mm2,在奈奎斯特频率以内,其杂散无失真动态范围大于70dB,其信杂比大于56dB。     

一种用于音频系统的1.1mW 87dB动态范围的ΔΣ调制器

本文描述了一款应用于音频系统的1.1mW 87dB动态范围的 Delta-Sigma 调制器的设计,设计采用0.18um CMOS工艺。由于采用带有前馈支路的多比特结构,第一级积分器的输出摆幅得到有效压缩。第一级积分器采用结构简单,直流增益仅34dB,工作在1V电压下的电流镜型跨导放大器。在3KHz信号输入下,该调制器可在100Hz~24KHz的频率范围内达到83.8dB的峰值SNDR和87dB的动态范围。     

An OTA gain enhancement technique for low power biomedical applications

The performance requirement of an operational trans-conductance amplifier (OTA) for the high gain and low power neural recording frontend has been addressed in this paper. A novel split differential pair technique is proposed to improve the gain of the OTA without any additional bias current requirements. The design demonstrates a significant performance enhancement when compared to existing techniques, such as gain-boosting and recycling. A qualitative and quantitative treatment is presented to explore the impact of the split ratio on the performance parameters of gain, bandwidth, and linearity. A prototype implemented in TSMC 65 nm CMOS technology achieved 68 dB open loop-gain (13 dB higher than the conventional circuit) and a 17 kHz 3-dB bandwidth. A linearity of ? 62 dB has been achieved with 7 mV pk–pk signal at the input. The circuit operates from a 1 V supply and draws 0.6 uA static current. The prototype occupies 3300 um² silicon area.     

A CMOS current-mode log(x) and log(1/x) functions generator

A novel Complementary Metal Oxide Semiconductor (CMOS) current-mode low-voltage and low-power controllable logarithmic function circuit is presented. The proposed design utilises one Operational Transconductance Amplifier (OTA) and two PMOS transistors biased in weak inversion region. The proposed design provides high dynamic range, controllable amplitude, high accuracy and is insensitive to temperature variations. The circuit operates on a ±0.6 V power supply and consumes 0.3 μW. The functionality of the proposed circuit was verified using HSPICE with 0.35 μm 2P4M CMOS process technology.     

A Low Power Dissipation Technique for a Low Voltage OTA

This paper proposes a novel low power dissipation technique for a low voltage OTA. A conventional low power OTA with a class AB input stage is not suitable for a low voltage operation (±1.5 V supply voltages), because it uses composite transistors (referred to CMOS pair) which has a large threshold voltage. On the other hand, the tail-current type OTA needs a large tail-current value to obtain a sufficient input range at the expense of power dissipation. Therefore, the conventional tail-current type OTA has a trade-off between the input range and the power dissipation to the tail-current value. The trade-off can be eliminated by the proposed technique. The technique exploits negative feedback control including a current amplifier and a minimum current selecting circuit. The proposed technique was used on Wang's OTA to create another OTA, named Low Power Wang's OTA. Also, SPICE simulations are used to verify the efficiency of Low Power Wang's OTA. Although the static power of Low Power Wang's OTA is 122 W, it has a sufficient input range, whereas conventional Wang's OTA needs 703 W to obtain a sufficient input range. However, we can say that as the input signal gets larger, the power of Low Power Wang's OTA becomes larger.     

增益提高型套筒式全差分跨导放大器的设计与分析

提出了一种应用于流水线型模数转换器(ADC)的增益提高型套筒式全差分跨导放大器(OTA)的设计与分析方法.通过ADC的性能要求推导出OTA的设计指标.该设计中OTA的架构由主运放、增益辅助运放及共模反馈电路3部分子电路组成.设计采用SMIC CMOS 0.18mm工艺平台.该设计方法的实验结果表明:1pF负载下,跨导放大器.的直流增益达到145dB,单位增益带宽超过750MHz,相位裕度达到58°.闭环增益为4时,放大器在20ns内稳定到0.05%的精度.