UWB radio module design for wireless sensor networks

In this paper, we describe an impulse-based ultra wideband (UWB) radio system for wireless sensor network (WSN) applications. Different architectures have been studied for base station and sensor nodes. The base station node uses coherent UWB architecture because of the high performance and good sensitivity requirements. However, to meet complexity, power and cost constraints, the sensor module uses a novel non-coherent architecture that can autonomously detect the UWB signals. The radio modules include a transceiver block, a baseband processing unit and a power management block. The transceiver block includes a Gaussian pulse generator, a multiplier, an integrator and timing circuits. For long range applications, a wideband low noise amplifier (LNA) is included in the transceiver of the sensor module, whereas in short range applications it is simply eliminated to further reduce the power consumption. In order to verify the proposed system concept, circuit level implementation is studied using 1.5 V 0.18 μm CMOS technology. Finally, the UWB radio modules have been designed for implementation in liquid-crystal-polymer (LCP) based System-on-Package (SoP) technology for low power, low cost and small size integration. A small low cost, double-slotted, Knight’s helm antenna is embedded in the LCP substrate, which shows stable characterization and a return loss better than ?10 dB over the UWB band.     

Improved structure for adiabatic CMOS circuits design

Two adiabatic circuits with complementary structure and operation are proposed in this paper. They employ two-phase sinusoidal power clock. The power consumption of the proposed circuits is comparable to that of some previously reported circuits. The problem of floating output nodes is solved by connecting two MOS transistors to the power clock. In particular, using the proposed architecture more than one stage of gates can be computed simultaneously within a single clock-phase, compared to only one stage is computed in every phase by most other adiabatic logic families. With this feature, the latency of the complex logic circuit is greatly improved and the number of buffers required for a pipelining circuit is also reduced. In this paper, a 2:1 multiplexer and full adder are illustrated and simulated. From the PSPICE simulation results, the effectiveness of the proposed approach and the low power characteristic of the designed circuits are validated.     

Fast clock synchroniser using initial phase presetting DPLL (IPP-DPLL) for burst signal reception

A fast clock synchroniser that quickly adjusts the initial phase of the DPLL output clock to the input signal (receiver detector output) at the beginning of acquisition is proposed for burst QDPSK signal reception. The synchroniser performance is given in terms of nondetection rate (NDR) of the unique word following the clock synchronisation preamble. Measured results clearly indicate that the proposed synchroniser achieves faster synchronisation than the conventional binary quantised DPLL clock synchroniser.<>     

A 2 Gbps to 12 Gbps Wide-Range CDR with Automatic Frequency Band Selector

The need for wide-band clock and data recovery(CDR) circuits is discussed.A 2 Gbps to 12 Gbps continuous-rate CDR circuit employing a multi-mode voltage-control oscillator(VCO),a frequency detector,and a phase detector(FD&PD) is described.A new automatic frequency band selection(FBS) without external reference clock is proposed to select the appropriate mode and also solve the instability problem when the circuit is powering on.The multi-mode VCO and FD/PD circuits which can operate at full-rate and half-rate modes facilitate CDR with six operation modes.The proposed CDR structure has been modeled with MATLAB and the simulated results validate its feasibility.     

Precise CMOS current sample/hold circuits using differential clockfeedthrough attenuation techniques

New CMOS current sample/hold (CSH) circuits capable of overcoming the accuracy limitations in conventional circuits without significantly reducing operating speed are proposed and analyzed. A novel differential clock feedthrough attenuation (DCFA) technique is developed to attenuate the signal-dependent clock feedthrough errors. Unlike conventional techniques, the DCFA circuit allows the use of dynamic mirror techniques, and results in no additional finite output resistance errors or device mismatch errors. The test chip of the proposed fully differential CSH circuit with multiple outputs has been fabricated in 1.2-μm CMOS technology. Using a single 5-V power supply, experimental results show that the signal-dependent clock feedthrough error current is less than ±0.4 μA for the input currents from -550 μA to 550 μA. The acquisition time for a 900-μA step transition to 0.1% settling accuracy is 150 ns. For a 410-μA_p-p input at 250 MHz with the fabricated fully-differential CSH circuit clocked at 4 MHz, a total harmonic distortion of -60 dB, and a signal-to-noise ratio of 79 dB have been obtained. The active chip area and power consumption of the fabricated CSH circuit are 0.64 mm² and 20 mW, respectively. Both simulation and experimental results have successfully verified the functions and performance of the proposed CSH circuits     

家用电热水器控制系统的实验研究

基于单片机AT89C52电热水器控制系统,该系统的功能是对电热水器进行温度采集与显示、时钟的显示、热水器的开机方式控制等。设计了系统硬件以微控制器为控制核心,由外围温度检测电路、实时时钟电路、键盘、热水器加热开关、LED显示电路、功能指示电路、报警电路等组成。其中温度测量是电热水器控制系统的重要组成部分,主要采用的是Pt1000铂电阻温度传感器进行温度采集。基于单片机控制的电热水器,具有反应灵敏,抗干扰能力强,稳态温度波动小,达到设定的温度时间短,节省电能等要求。     

新型相位式激光测距系统电路的设计

为了提高相位式激光测距系统的精度和可靠性,设计了一种新型的相位式激光测距系统的发射和两路几乎一致的接收电路。通过采用具有微小频差的低抖动时钟发生技术,差频测相技术等原理,系统可以实现特定环境下的高精度测量。系统由级联式PLL可编程时钟信号源、激光发射与接收模块、自动增益控制、混频滤波及数据采集组成。利用时钟源产生调制信号,并对反馈信号和接收信号进行放大、混频滤波等信号调理,进而采集数据并对数据进行处理分析。在电路的设计中,优化了激光的调制发射电路,采用低回波损耗的尾纤式激光器,增加简单实用的自动增益模块等。实验观察的波形和数据结果分析表明,此相位式激光测距系统电路简单实用,并且具有较高的稳定性和较高的测量精度。     

Design of a low-power CMOS transceiver for semi-passive wireless sensor network application

A 50 kbps/ISM band (902 − 926 MHz) low power transceiver for short-range wireless sensor networks (WSN) has been designed in 0.18 μm 1-poly-6 metal CMOS technology and occupy 950 μm × 800 μm. The proposed WSN transceiver designed based on an improved version of the Amplitude-Shift Keying communication scheme has a better continuous RF modulated carrier waveform as well as does not require complex modulator/demodulator circuits. In addition, to reduce power dissipation and increase power efficiency many circuit techniques have been adopted. The power dissipation and the power efficiency of the proposed WSN transceivers are 1.58 mW and 21%, respectively.     

BiCMOS circuit technology for a 704 MHz ATM switch LSI

This paper describes BiCMOS level-converter circuits and clock circuits that increase VLSI interface speed to 1 GHz, and their application to a 704 MHz ATM switch LSI. An LSI with a high speed interface requires a BiCMOS multiplexer/demultiplexer (MUX/DEMUX) on the chip to reduce internal operation speed. A MUX/DEMUX with minimum power dissipation and a minimum pattern area can be designed using the proposed converter circuits. The converter circuits, using weakly cross-coupled CMOS inverters and a voltage regulator circuit, can convert signal levels between LCML and positive CMOS at a speed of 500 MHz. Data synchronization in the high speed region is ensured by a new BiCMOS clock circuit consisting of a pure ECL path and retiming circuits. The clock circuit reduces the chip latency fluctuation of the clock signal and absorbs the delay difference between the ECL clock and data through the CMOS circuits. A rerouting-Banyan (RRB) ATM switch, employing both the proposed converter circuits and the clock circuits, has been fabricated with 0.5 μm BiCMOS technology. The LSI, composed of CMOS 15 K gate logic, 8 Kb RAM, I Kb FIFO and ECL 1.6 K gate logic, achieved an operation speed of 704-MHz with power dissipation of 7.2 W     

A wide-range programmable frequency synthesizer based on a finite state machine filter

In this article, an FPGA-based design and implementation of a fully digital wide-range programmable frequency synthesizer based on a finite state machine filter is presented. The advantages of the proposed architecture are that, it simultaneously generates a high frequency signal from a low frequency reference signal (i.e. synthesising), and synchronising the two signals (signals have the same phase, or a constant difference) without jitter accumulation issue. The architecture is portable and can be easily implemented for various platforms, such as FPGAs and integrated circuits. The frequency synthesizer circuit can be used as a part of SERDES devices in intra/inter chip communication in system-on-chip (SoC). The proposed circuit is designed using Verilog language and synthesized for the Altera DE2-70 development board, with the Cyclone II (EP2C35F672C6) device on board. Simulation and experimental results are included; they prove the synthesizing and tracking features of the proposed architecture. The generated clock signal frequency of a range from 19.8?MHz to 440?MHz is synchronized to the input reference clock with a frequency step of 0.12?MHz.     

2.488 Gbit/s时钟数据恢复电路的设计

利用Cadence集成电路设计软件,基于SMIC 0.18 μm 1P6M CMOS工艺,设计了一款2.488 Gbit/s三阶电荷泵锁相环型时钟数据恢复(CDR)电路.该CDR电路采用双环路结构实现,为了增加整个环路的捕获范围及减少锁定时间,在锁相环(PLL)的基础上增加了一个带参考时钟的辅助锁频环,由锁定检测环路实时监控频率误差实现双环路的切换.整个电路由鉴相器、鉴频鉴相器、电荷泵、环路滤波器和压控振荡器组成.后仿真结果表明,系统电源电压为1.8V,在2.488 Gbit/s速率的非归零(NRZ)码输入数据下,恢复数据的抖动峰值为14.6 ps,锁定时间为1.5μs,功耗为60 mW,核心版图面积为566 μm×448μm.     

Novel broad-band bit-synchronization circuit module for optical interconnections

A novel broad-band and ultrafast bit-synchronization circuit module is proposed and fabricated for optical interconnections. In optical packet switch fabric or optical interconnection between electric circuit boards, instantaneous bit synchronization is crucial to properly retime incoming packets with a random phase and reduce the number of preamble overhead bits. The developed bit-synchronization circuit module has a new clock selection circuit, which is configured with a phase comparator and an amplitude comparator. Since device-dependent delay circuits, such as buffer amplifiers or RC phasors, are not adopted, the newly developed clock selection circuit can operate under broad-band frequencies. The bit-synchronization circuit module was fabricated with a Si-bipolar gate array and it can operate at broad-band bit rates of up to 10.5 Gb/s. It also exhibits a power sensitivity penalty as low as 3 dB for 10-Gb/s input signals. The synchronization acquisition time of less than 9 b over the entire 360/spl deg/ phase range was confirmed by experiment.     

用于锁相环快速锁定的鉴频鉴相器设计

针对鉴频鉴相器(PFD)的盲区现象对锁相环路的锁定速度的影响,设计了一种PFD结构,可以实现锁相环路的快速锁定。该结构在传统PFD的基础上,利用内部信号的逻辑关系进行逻辑控制,其输出特性呈现非线性;在输入相位差大于π时,抑制了复位脉冲的产生,避免了输入时钟边沿的丢失,有效消除了盲区,加快了锁相环的锁定速度。设计采用SMIC 0.18μm标准CMOS工艺,采用全定制设计方法对该PFD结构进行了设计、仿真分析和验证。结果表明,采用该PFD结构的锁相环,在400 MHz工作频率下锁定时间为2.95μs,锁定速度提高了34.27%。     

A DLL-Based Variable-Phase Clock Buffer

A variable-phase clock buffer that uses a delay-locked loop (DLL) is presented. The variable-phase clock is achieved by switching the multiphase outputs of the divider in the DLL. The output phase is adjustable in a step of where pi/n is the ratio of two voltage-controlled delay lines in the proposed circuit. The prototype has been fabricated in a 0.18- CMOS process to realize the output phases of 0deg, 90deg, 180deg, and 270deg. The corresponding measured phase error is 3.24deg, 3.46deg, 3.89deg, and 1.94deg, respectively. The measured root-mean-squared jitter is 1.81 ps. The clock buffer consumes 67 mW including I/O circuits from a single 1.8-V supply at 600 MHz.     

A high speed GaAs error-detection circuit for fiber-optictransmission systems

A high-speed GaAs IC for detection of line code vibrations is described. This 144-gate error-detection circuit for monitoring a high-bit-rate fiber-optic link has been designed and fabricated using a high-yield titanium tungsten nitride self-aligned gate MESFET process. This process routinely provides a wafer-averaged gate delay (fan-in=fan-out=2) of less than 70 ps with a power dissipation of 0.5 mW/gate. The error-detection circuits were tested on-wafer using high-frequency probe cards at a clock rate of 1.4 GHz, with a yield of 64%. Packaged circuits worked at a clock frequency of over 2.5 GHz and consumed 200-mW power at a fixed power supply voltage of 1.5 V. The circuits operate over a wide variation in power supply voltage and temperature. When operated at a package temperature of 125°C, the circuits show less than a 12% degradation in their maximum clock frequency. The circuit was inserted into a 565-Mb/s system currently using a silicon ECL part, and full functionality was verified with no necessary modifications     

Clock recovery circuits with instantaneous locking

Clock recovery circuits based on matched gated oscillators are proposed. Lock is acquired on the first data transition, even with non-return-to-zero line coding and with instantaneous and arbitrarily large phase shifts of the incoming signal. Simulated results of a fully integrated 650 Mbit/s clock recovery circuit designed in an existing 0.9 mu m CMOS technology are also presented.<>     

A 40 Gb/s Clock and Data Recovery Module with Improved Phase‐Locked Loop Circuits

A 40 Gb/s clock and data recovery (CDR) module for a fiber‐optic receiver with improved phase‐locked loop (PLL) circuits has been successfully implemented. The PLL of the CDR module employs an improved D‐type flip‐flop frequency acquisition circuit, which helps to stabilize the CDR performance, to obtain faster frequency acquisition, and to reduce the time of recovering the lock state in the event of losing the lock state. The measured RMS jitter of the clock signal recovered from 40 Gb/s pseudo‐random binary sequence (2³¹‐1) data by the improved PLL clock recovery module is 210 fs. The CDR module also integrates a 40 Gb/s D‐FF decision circuit, demonstrating that it can produce clean retimed data using the recovered clock.     

A low-power half-delay-line fast skew-compensation circuit

A fast skew-compensation circuit is useful for a chip to safely recover from the halt state because it can quickly compensate the clock skew induced by the on-chip clock driver. A low-power half-delay-line fast skew-compensation circuit (HDSC) is proposed in this work. The HDSC circuit features several new design techniques. The first is a new measure-and-compensate architecture, with which the HDSC circuit gains advantages including an enlarged operation frequency range, more robust operation, more accurate phase alignment, higher scalability for using advanced technologies, and lower power consumption, as compared to the conventional fast skew-compensation circuits. The second is a frequency-independent phase adjuster, with which the delay line can be shortened by half and the maximal power consumption is reduced accordingly if the clock signal has a 50% duty cycle. The third is a fine delay cell, which is used to accompany the half-delay-line, comprising of minimum-sized coarse delay cells, to effectively reduce the static phase error. Extensive circuit simulations are carried out to prove the superiority of the proposed circuit. In addition, an HDSC test chip is implemented for performance verification at high frequencies. The test chip is designed based on a 0.35-/spl mu/m CMOS process, and has a coarse cell delay of 220 ps. It works successfully between 600/spl sim/800 MHz, as designed, with a power consumption of 25/spl sim/36 /spl mu/W/MHz. When measured at 616.9 and 791.6 MHz, the static phase error is 76.8 and 124.5 ps, respectively.     

Performance analysis of an all-digital BPSK direct-sequencespread-spectrum IF receiver architecture

A VLSI architecture for an all-digital binary phase shift keying (BPSK) direct-sequence (DS) spread spectrum (SS) intermediate frequency (IF) receiver is presented, and an in-depth performance analysis is given. The all-digital architecture incorporates a Costas loop for carrier recovery and a delay-locked loop for clock recovery. For the pseudorandom noise (PN) acquisition block, a robust energy detection scheme is proposed to reduce false PN locks over a broad range of signal-to-noise ratios. The proposed architecture is intended for use in the 902-928 MHz unlicensed spread spectrum radio band. A 100 kbs information rate and a 12.7 Mchips/second PN code rate are assumed. The IF center frequency is 12.7 MHz and the IF sampling rate is 50.8 Msamples/second, which is the Nyquist rate for the 25.4 MHz bandwidth signal. Finite wordlength effects have been simulated to optimize the architecture, thereby minimizing the chip area, and results of the finite wordlength simulations demonstrate that the chip architecture achieves a bit error rate performance within 1 dB of theory in an additive white Gaussian noise channel     

一种有载频超宽带脉冲源设计

针对无载频脉冲低频分量大、辐射效率低、频带可调性差等问题,设计了一种以阶跃恢复二极管、D触发器及超宽带调制器为主的宽频带、高重复频率、低振铃水平的有载频超宽带脉冲源。该脉冲源电路由驱动电路、高速开关电路、整形电路、超宽带调制器及振荡器电路组成。实测结果表明,脉冲源输出脉冲信号重复频率可达125 MHz,脉冲宽度600 ps（底宽）,脉冲振铃水平低于10%,峰-峰值为5.4 V,-10 dB带宽可达4.2 GHz。脉冲信号中心频率与载频相同,可在6.6~8.5 GHz之间灵活设置。利用所设计的脉冲源进行时域测量,其结果与矢量网络分析仪频域测量结果相比幅频特性均方根误差小于0.21 dB。该脉冲源可应用于超宽带时域测量、短距离高速无线通信、高精度室内定位等应用。