The synthesis method of logic circuits based on the iMemComp gates

The iMemComp is a family of logic gates based on RRAM devices. It has potential advantage on the design of high-performance logic circuits, since the NAND, AND, NOT and transmission iMemComp gates only consume single cycle, respectively. However, the synthesis method of logic circuits based on the iMemComp gates has not been systematically studied before. This work proposes the synthesis method of the row-oriented logic circuits based on the multi-input single-cycle iMemComp gates. The synthesis results show that the circuits generated from the proposed method outperform most of those RRAM based counterparts generated from the previous methods. Furthermore, the synthesis method of the array-oriented iMemComp logic circuits is proposed. The proposed array-oriented method generates the relatively high-performance logic circuits since both the row-based and the column-based single-cycle iMemComp gates are applied, and the generated circuits are relatively area-efficient because the intra-row and inter-row redundancies are utilized in the circuit mapping.     

Debugging reversible circuits

A strong driving force for research of post-CMOS technologies is the fact that silicon-based transistors cannot be arbitrarily scaled down. Furthermore, power dissipation is a major barrier in the development of smaller and more efficient computer chips. In contrast, reversible logic with its applications e.g. in low-power design or quantum computation provides a promising alternative to traditional technologies. While there have been investigations in the domain of reversible logic synthesis, testing, and verification; debugging of reversible circuits has not yet been considered. The goal of debugging is to determine gates of an erroneous circuit that explain the observed incorrect behavior.In this paper, we propose the first approach for automatic debugging of reversible Toffoli circuits. Our method uses a formulation for the debugging problem based on Boolean satisfiability. We show the differences to traditional (irreversible) debugging. In addition, we introduce an improved approach that strengthens error candidate identification. This overcomes the limitations from traditional debugging, i.e. that error candidates are only an approximation of the real source of the error. Furthermore, observations are presented that can be applied to automatically fix an erroneous circuit just by replacing a single gate by a cascade. Due to reversibility this cascade can be efficiently computed. Experimental results show the quality and efficiency of our debugging approaches.     

Improving the energy efficiency of reversible logic circuits by the combined use of adiabatic styles

One of the most prominent issues in fully adiabatic circuits is the breaking reversibility problem; i.e., non-adiabatic energy dissipation in the last stage adiabatic gates whose outputs are connected to external circuits. In this paper, we show that the breaking reversibility problem can result in significant energy dissipation. Subsequently, we propose an efficient technique to address the breaking reversibility problem, which is applicable to the usual fully adiabatic logic such as 2LAL, SCRL, and RERL. Detailed SPICE simulations are used to evaluate the proposed technique. The experimental results show that the proposed technique can considerably reduce (e.g., about 74% for RERL, 35% for 2LAL, and 17% for SCRL) the energy dissipation arising from the breaking reversibility problem.     

Optimized reversible arithmetic logic units

Arithmetic Logic Unit(ALU) as one of the main parts of any computing hardware plays an important role in digital computers. In quantum computers which can be realized by reversible logics and circuits, reversible ALUs should be designed. In this paper, we proposed three different designs for reversible 1-bit ALUs using our proposed 3×3 and 4×4 reversible gates called MEB3 and MEB4(Moallem Ehsanpour Bolhasani) gates, respectively. The first proposed reversible ALU consists of six logical operations. The second proposed ALU consists of eight operations, two arithmetic, and six logical operations. And finally, the third proposed ALU consists of sixteen operations, four arithmetic operations, and twelve logical operations. Our proposed ALUs can be used to construct efficient quantum computers in nanotechnology, because the proposed designs are better than the existing designs in terms of quantum cost, constant input, reversible gates used, hardware complexity, and functions generated.     

Modeling and simulation of combinational CMOS logic circuits by ANFIS

In this paper, application of adaptive neuro-fuzzy inference system (ANFIS) in modeling of CMOS logic gates as a tool in designing and simulation of CMOS logic circuits is presented. Structures of the ANFIS are developed and trained in MATLAB 7.0.4 program. We have used real hardware data for training the ANFIS network. A hybrid learning algorithm consists of back-propagation and least-squares estimation is used for training. Influence of the structure of the proposed ANFIS model on accuracy and network performance has been analyzed through some combinational circuits. For the comparison of the ANFIS simulation results, we have simulated the circuits in HSPICE environment with 0.35 μm process nominal parameters. The comparison between ANFIS, HSPICE, and real hardware shows the feasibility and accuracy of the proposed ANFIS modeling procedure. The results show the proposed ANFIS simulation has much higher speed and accuracy in comparison with HSPICE simulation and it can be simply used in software tools for designing and simulation of complex CMOS logic circuits.     

Novel design of a fast reversible Wallace sign multiplier circuit in nanotechnology

Today, reversible logic is emerging as an intensely studied research topic, having applications in diverse fields, such as low-power design, optical information processing, and quantum computation. In this paper, we have proposed two reversible Wallace signed multiplier circuits through modified Baugh-Wooley approach, which are much better than the two available counterparts in all the terms. The multiplier is an essential building block for the construction of computational units of quantum computers. Besides, we need signed multiplier circuits for numerous operations. However, only two reversible signed multiplier circuits have been presented so far. In the first proposed architecture, our goals are to decrease the depth of the circuit and to increase the speed of the circuit. In the second proposed circuit, we aimed to improve the quantum cost, garbage outputs, and other parameters. All the proposed circuits are in the nanometric scales and can be used in the design of very complex systems.     

Efficient reversible NOR gates and their mapping in optical computing domain

Reversible logic is a computing paradigm in which there is a one to one mapping between the input and the output vectors. Reversible logic gates are implemented in an optical domain as it provides high speed and low energy computations. In the existing literature there are two types of optical mapping of reversible logic gates: (i) based on a semiconductor optical amplifier (SOA) using a Mach–Zehnder interferometer (MZI) switch; (ii) based on linear optical quantum computation (LOQC) using linear optical quantum logic gates. In reversible computing, the NAND logic based reversible gates and design methodologies based on them are widely popular. The NOR logic based reversible gates and design methodologies based on them are still unexplored. In this work, we propose two NOR logic based n-input and n-output reversible gates one of which can be efficiently mapped in optical computing using the Mach–Zehnder interferometer (MZI) while the other one can be mapped efficiently in optical computing using the linear optical quantum gates. The proposed reversible NOR gates work as a corresponding NOR counterpart of NAND logic based Toffoli gates. The proposed optical reversible NOR logic gates can implement the reversible boolean logic functions with a reduced number of linear optical quantum logic gates or reduced optical cost and propagation delay compared to their implementation using existing optical reversible NAND gates. It is illustrated that an optical reversible gate library having both optical Toffoli gate and the proposed optical reversible NOR gate is superior compared to the library containing only the optical Toffoli gate: (i) in terms of number of linear optical quantum gates when implemented using linear optical quantum computing (LOQC), (ii) in terms of optical cost and delay when implemented using the Mach–Zehnder interferometer.     

Trading off circuit lines and gate costs in the synthesis of reversible logic

Motivated by its application in several emerging technologies, the synthesis of reversible circuits has received significant attention in the last decade. The proposed methods can roughly be divided into two different categories: (A) approaches ensuring the minimal number of circuit lines and (B) hierarchical approaches. Both synthesis paradigms have significant differences with respect to the gate costs and the number of lines in the resulting circuits. Hence, designers often have to deal with unsatisfactory results were either the gate costs or the number of circuit lines is disproportionately large.     

A library-based synthesis methodology for reversible logic

Synthesis of reversible logic has received significant attention in the recent years and many synthesis approaches for reversible circuits have been proposed so far. In this paper, a library-based synthesis methodology for reversible circuits is proposed where a reversible specification is considered as a permutation comprising a set of cycles. To this end, a pre-synthesis optimization step is introduced to construct a reversible specification from an irreversible function. In addition, a cycle-based representation model is presented to be used as an intermediate format in the proposed synthesis methodology. The selected intermediate format serves as a focal point for all potential representation models.In order to synthesize a given function, a library containing seven building blocks is used where each building block is a cycle of length less than 6. To synthesize large cycles, we also propose a decomposition algorithm which produces all possible minimal and inequivalent factorizations for a given cycle of length greater than 5. All decompositions contain the maximum number of disjoint cycles. The generated decompositions are used in conjunction with a novel cycle assignment algorithm which is proposed based on the graph matching problem to select the best possible cycle pairs. Then, each pair is synthesized by using the available components of the library. The decomposition algorithm together with the cycle assignment method are considered as a binding method which selects a building block from the library for each cycle. Finally, a post-synthesis optimization step is introduced to optimize the synthesis results in terms of different costs.To analyze the proposed methodology, various experiments are performed. Our analyses on the available reversible benchmark functions reveal that the proposed library-based synthesis methodology can produce low-cost circuits in some cases compared with the current approaches. The proposed methodology always converges and it typically synthesizes a give function fast. No garbage line is used for even permutations.     

Exact synthesis of three-qubit quantum circuits from non-binary quantum gates

Because of recent nano-technological advances, nano-structured systems have become highly ordered, making it quantum computing schemas possible. We propose an approach to optimally synthesise quantum circuits from non-permutative quantum gates such as controlled-square-root-of-not (i.e., controlled-V). Our approach reduces the synthesis problem to multiple-valued optimisation and uses group theory. We devise a novel technique that transforms the quantum logic synthesis problem from a multi-valued constrained optimisation problem to a permutable representation. The transformation enables us to use group theory to exploit the symmetric properties of the synthesis problem. Assuming a cost of one for each two-qubit gate, we found all reversible circuits with quantum costs of 4, 5, 6, etc., and give another algorithm to realise these reversible circuits with quantum gates. The approach can be used for both binary permutative deterministic circuits and probabilistic circuits such as controlled random-number generators and hidden Markov models.     

线性最近邻量子电路状态分析及最优逻辑综合

综合量子电路时必须考虑量子电路实现时的约束与限制.某些量子技术中只允许物理上相邻的量子比特有相互作用,实现时必须采用线性最近邻架构.通常通过添加交换门使任意一个量子门的控制位与目标位相近邻,并保证电路的功能不受影响.在分析电路中量子比特状态的基础上,提出了一种新的线性最近邻量子电路构造方法.结果表明:对于所有40320个三比特量子电路,提出方案比已有方案的量子代价优化了约30％.     

基于NCV门的量子电路故障的检测与定位研究

为了确保基于NCV门库的量子电路的正确性和有效性,给出了量子电路故障定位树的生成算法和量子电路黑盒检测算法来定位量子电路中的门丢失故障。该故障定位树算法去除约98%的无用输出向量,提取输出表中有效的输入向量以及对应的故障输出向量,逐层生成故障定位树。结合量子电路黑盒检测算法对量子电路进行故障定位时不需要访问输出表就能够有效定位量子电路中的丢失门。对benchmarks部分电路进行实验,结果验证了该算法定位单故障门的有效性。     

三种基于EDFA的全光逻辑门及其应用

利用掺铒光纤放大器的增益缓变吸收和放大光脉冲信号的特性,结合光纤耦合器和萨格纳克干涉仪,提出了三种的不同结构的全光逻辑门,并分析了此三种全光逻辑门的优缺点和各自的用途。     

基于遗传算法的量子可逆逻辑电路综合方法研究

量子可逆逻辑电路综合主要是研究在给定的量子门和量子电路的约束条件及限制下,找到最小或较小的量子代价实现所需量子逻辑功能的电路。把量子逻辑门的功能用矩阵的数学模型表示,用遗传算法作全局搜索工具,将遗传算法应用于量子可逆逻辑电路综合,是一种全新的可逆逻辑电路综合方法,实现了合成、优化同步进行。四阶量子电路实验已取得了很好的效果,并进一步分析了此方法在高阶量子电路综合问题上的应用前景。     

Balance testing and balance-testable design of logic circuits

We propose a low-cost method for testing logic circuits, termed balance testing, which is particularly suited to built-in self testing. Conceptually related to ones counting and syndrome testing, it detects faults by checking the difference between the number of ones and the number of zeros in the test response sequence. A key advantage of balance testing is that the testability of various fault types can be easily analyzed. We present a novel analysis technique which leads to necessary and sufficient conditions for the balance testability of the standard single stuck-line (SSL) faults. This analysis can be easily extended to multiple stuck-line and bridging faults. Balance testing also forms the basis for design for balance testability (DFBT), a systematic DFT technique that achieves full coverage of SSL faults. It places the unit under test in a low-cost framework circuit that guarantees complete balance testability. Unlike most existing DFT techniques, DFBT requires only one additional control input and no redesign of the underlying circuit is necessary. We present experimental results on applying balance testing to the ISCAS 85 benchmark circuits, which show that very high fault coverage is obtained for large circuits even with reduced deterministic test sets. This coverage can always be made 100% either by adding tests or applying DFBT.This research was supported by the National Science Foundation under Grant No. MIP-9200526. Parts of this paper were published in preliminary form in Proc. 23rd Symp. Fault-Tolerant Computing, Toulouse, June 1993, and in Proc. 31st Design Automation Conf, San Diego, June 1994.     

Comparison of fully printed unipolar and complementary organic logic gates

We compare the static and dynamic behavior of fully printed organic inverters based on unipolar and complementary transistor logic. The latter show a better static as well as dynamic behavior with a superior voltage gain, noise margin and switching speed. Finally the first fully printed complementary NAND-gate is demonstrated.     

Transistor realization of reversible “ZS” series gates and reversible array multiplier

In order to reduce the redundant Toffoli gates and the line-crossings in the classical reversible full adder appearing in the present literatures, this paper gives a reconstructive structure of Fredkin gate, called RF gate, the corresponding quantum equivalent realization and electronic circuitry construction based on CMOS technology and pass-transistor of this gate are also designed in this paper. With the assistance of the RF gate and the basic reversible gates (including NOT gate, CNOT gate and Toffoli gate), we design new 4×4 reversible gates called “ZS” series gates and its corresponding electronic circuitry construction. The proposed “ZS” series gates have the ability to operate reversible add operation between two signed numbers by a single gate and at lower power consumption. At the same time, as an application of “ZS” series gates, this paper also designs reversible array multiplier in order to achieve the signed multiplication. It can be theoretically proved that the proposed reversible array multiplier can eliminate power loss associated with the irreversible operation of classical computer, and will be exponentially lower than reversible parallel multiplier with respect to time complexity.     

综合法研究量子可逆逻辑电路

摘 要：量子可逆逻辑电路优化与综合主要是研究在给定的量子门和量子电路的约束条件下,找到最小或较小的量子代价电路以实现所需电路逻辑功能。量子逻辑真值表综合法是量子电路可逆逻辑综合中最有效的方法之一,它包括正向综合、逆向综合和双向综合。本文推广和定义了横向汉明距离、纵向汉明距离和交叉汉明距离,使用广义汉明距离提出了一种量子电路优化与综合的新方法。研究表明,此方法使量子逻辑电路得到了更好的优化。     

Fault detection for multiple-valued logic circuits with fanout-free

The single fault and multiple fault detections for multiple-valued logic circuits are studied in this paper. Firstly, it is shown that the cardinality of optimal single fault test set for fanout-free m-valued circuits with n primary inputs is not more than n + 1, for linear tree circuits is two, and for multiplication modulo circuits is two if n is an odd number or if n is an even number and m > 3, where the optimal test set of a circuit has minimal number of test vectors. Secondly, it is indicated that the cardinality of optimal multiple fault test set for linear tree circuits with n primary inputs is 1 + [n/(m - 1)], for multiplication modulo circuits is n + 1, for fanout-free circuits that consist of 2-input linear tree circuits and 2-input multiplication modulo circuits is not greater than n+ 1, where [x] denotes the smallest integer greater than or equal to x. Finally, the single fault location approaches of linear tree circuits and multiplication modulo circuits are presented, and all faults in th