A compact ADPLL based on symmetrical binary frequency searching with the same circuit

A compact all-digital phase-locked loop (C-ADPLL) based on symmetrical binary frequency searching (BFS) with the same circuit is presented in this paper. The minimising relative frequency variation error Δη (MFE) rule is derived as guidance of design and is used to weigh the accuracy of the digitally controlled oscillator (DCO) clock frequency. The symmetrical BFS is used in the coarse-tuning process and the fine-tuning process of DCO clock frequency to achieve the minimum Δη of the locked DCO clock, which simplifies the circuit architecture and saves the die area. The C-ADPLL is implemented in a 0.13 μm one-poly-eight-metal (1P8M) CMOS process and the on-chip area is only 0.043 mm², which is much smaller. The measurement results show that the peak-to-peak (Pk-Pk) jitter and the root-mean-square jitter of the DCO clock frequency are 270 ps at 72.3 MHz and 42 ps at 79.4 MHz, respectively, while the power consumption of the proposed ADPLL is only 2.7 mW (at 115.8 MHz) with a 1.2 V power supply. The measured Δη is not more than 1.14%. Compared with other ADPLLs, the proposed C-ADPLL has simpler architecture, smaller size and lower Pk-Pk jitter.     

Bidirectional hybrid OFDM based Wireless-over-fiber transport system using reflective semiconductor amplifier and polarization multiplexing technique

In this paper, a bidirectional hybrid OFDM based Wireless-over-fiber architecture has been investigated and demonstrated to transmit 10 Gbps as well as 6.25 Gbps OFDM data for downlink transmission and 5 Gbps as well as 2.5 Gbps OFDM data for uplink transmission over 50-km single mode fiber (SMF) employing polarization multiplexing technique (POLMUX) at optical line terminal (OLT) and optical network unit (ONU). The POLMUX technique is exercised by polarization beam splitters and polarization beam combiners. Mach-Zehnder modulator and RSOA have been used for modulation at OLT and ONU respectively. Transmission performances are observed by constellation diagrams, EVM and BER values. For 10 Gbps, 6.25 Gbps down-link signal and 5 Gbps, 2.5 Gbps up-link signal the power penalty of 3 dBm, 2.3 dBm and 4 dBm, 3.2 dBm at a BER of 10⁻⁹ between back-to-back and over 50-km SMF plus 10-m and 5-m wireless link, are observed respectively. For 32-QAM < 10.5% EVM and for 16-QAM < 13% EVM are recorded. Our architecture is a prominent alternative, not only due to its have potential of both optical and wireless technology but also it is offers a powerful platform to communicate high data rates and support various type of future unforeseen applications and services.     

A 400 MHz–1.5 GHz all digital integer-N PLL with a reference spur reduction technique

In this Letter, 400 MHz–1.5 GHz all digital integer-N PLL with a reference spur reduction is proposed. A reference spur is occurred by updating DCO control code at every reference clock period. To reduce a reference spur component, the phase detector which transfers phase error information only when phase error is detected has been designed. The measured clock jitter is 2.528 ps_rms at 1.5 GHz operation, and 3.991 ps_rms at 400 MHz operation. The ADPLL occupies 0.088 mm², and consumes 1.19 mW at 1.5 GHz. This ADPLL is implemented in 65 nm CMOS technology.     

A flicker-free CMOS LED driver control circuit for visible light communication enabling concurrent data transmission and dimming control

Recent breakthroughs in solid-state lighting technology have opened the door to a variety of applications using light-emitting diodes (LED’s) for not only illumination, but also optical wireless communication. Low-power CMOS technology enables realization of system-on-chip driver circuits integrating multiple functions to control LED device performance, luminance, and data modulation for “intelligent” visible light networking. This paper presents an LED driver circuit architecture, incorporating analog and digital circuit blocks to deliver concurrent dimming control, and data transmission. This is achieved by independent control of output voltage and current using buck converter and current control loops, respectively. This integrated system incorporates the feedback mechanisms to provide uniform light output together with the peak current control, which also prevents flickering. The proposed architecture is flexible enough to take any digital base band modulation format. Designed and implemented in a 180 nm CMOS process, it provides linear 10–90 % dimming control while transmitting data. It also introduces a mechanism which can be applied to the off-the-shelf LED drivers and make them applicable for the visible light communication applications. The power consumption of on-chip circuitry, is negligible compared to the overall power consumption which yields an efficiency of 89 % at 120 mA of load current. The measured bit error rate (BER) varies from 10^?6 at the data rate of 2.5 Mbps to 10^?2 at the data rate of 7 Mbps. All control functions integrated on-chip with the total power consumption of 5 mW.     

System simulations of a 1.5 V SiGe 81–86 GHz E-band transmitter

This paper presents simulation results for a sliding-IF SiGe E-band transmitter circuit for the 81–86 GHz E-band. The circuit was designed in a SiGe process with f _T  = 200 GHz and uses a supply of 1.5 V. The low supply voltage eliminates the need for a dedicated transmitter voltage regulator. The carrier generation is based on a 28 GHz quadrature voltage oscillator (QVCO). Upconversion to 84 GHz is performed by first mixing with the QVCO signals, converting the signal from baseband to 28 GHz, and then mixing it with the 56 GHz QVCO second harmonic, present at the emitter nodes of the QVCO core devices. The second mixer is connected to a three-stage power amplifier utilizing capacitive cross-coupling to increase the gain, providing a saturated output power of +14 dBm with a 1 dB output compression point of +11 dBm. E-band radio links using higher order modulation, e.g. 64 QAM, are sensitive to I/Q phase errors. The presented design is based on a 28 GHz QVCO, the lower frequency reducing the phase error due to mismatch in active and passive devices. The I/Q mismatch can be further reduced by adjusting varactors connected to each QVCO output. The analog performance of the transmitter is based on ADS Momentum models of all inductors and transformers, and layout parasitic extracted views of the active parts. For the simulations with a 16 QAM modulated baseband input signal, however, the Momentum models were replaced with lumped equivalent models to ease simulator convergence. Constellation diagrams and error vector magnitude (EVM) were calculated in MATLAB using data from transient simulations. The EVM dependency on QVCO phase noise, I/Q imbalance and PA compression has been analyzed. For an average output power of 7.5 dBm, the design achieves 7.2% EVM for a 16 QAM signal with 1 GHz bandwidth. The current consumption of the transmitter, including the PA, equals 131 mA from a 1.5 V supply.     

A self-duty-cycled 7.2–8.5 GHz IR-UWB receiver for low power and low data rate applications

A self-duty-cycled non-coherent impulse radio-ultra wideband receiver targeted at low-power and low-data-rate applications is presented. The receiver is implemented in a 130 nm CMOS technology and works in the 7.2–8.5 GHz UWB band, which covers the IEEE 802.15.4a and 802.15.6 mandatories high-band channels. The receiver architecture is based on a non-coherent RF front-end (high gain LNA and pulse detector) followed by a synchronizer block (clock and data recovery or CDR function and window generation block), which enables to shut down the power-hungry LNA between pulses to strongly reduce the receiver power consumption. The main functions of the receiver, i.e. the RF front-end and the CDR block, were measured stand-alone. A maximum gain of 40 dB at 7.2 GHz is measured for the LNA. The RF front-end achieves a very low turn-on time (<1 ns) and an average sensitivity of ?92 dBm for a 10^?3 BER at a 1 Mbps data rate. A root-mean-square (RMS) jitter of 7.9 ns is measured for the CDR for a power consumption of 54 µW. Simulation results of the fully integrated self-duty-cycled 7.2–8.5 GHz IR-UWB receiver (that includes the measured main functions) confirm the expected performances. The synchronizer block consumes only 125 µW and the power consumption of the whole receiver is 1.8 mW for a 3% power duty-cycle (on-window of 30 ns).     

Neural network implementation of a fade countermeasure controller for a VSAT link

In this paper, an algorithm and its practical implementation to activate adaptive modulation as a fade countermeasure (FCM) is presented. Characteristics of the algorithm are derived from the propagation studies and the algorithm uses a simple four parameter model. A neural network architecture was used to implement the decision making block of the controller. The algorithm has been implemented on a fixed point DSP. An experimental set‐up with an emulated K_a‐band satellite link and a terrestrial return path connection has been used with previously recorded propagation data for experimental verification and performance analysis. Performance of the implemented FCM system is compared with that of fixed, non‐adaptive systems. Over concatenated rain events, the adaptive system yields better throughput at or below a given BER than any fixed mode system and only marginally worse BER availability than the most robust scheme in the system. The FCM is thus essential if throughput is of importance as well as availability. The added complexity of the FCM system is not great by contemporary technology standards and is, in authors' opinion, well worth the investment. Copyright © 2002 John Wiley & Sons, Ltd.     

EVM and BER Simulation of an NADC-TDMA Radiophone Influenced by the Operator's Body in Urban Mobile Environments

This paperpresents the performance evaluation of a portable digital radiophoneinfluencedby the operator's body in urban mobile environments, based on the EVM (errorvector magnitude) and BER (bit error rate) simulation. The type of digitalmodulation follows to the NADC-TDMA standard. A new probability densityfunction(pdf) is proposed to describe the statistic of the EVM in an AWGNchannelunder frequency non-selective slowly fading situation. The simulation combinesthe modified Doppler power spectrum (MDPS) method and a gray coding(/4-DQPSK modulation with square-root raised cosine (SRRC) shaping filter.The performance evaluation based on BER uses an ideal matched-filter-basedreceiver. The results show that the closer of the distance between theradiophone antenna and the operator's head, the poorer of the EVM and BERperformance.     

DIFFS: A Low Power,Multi-Mode,Multi-Standard Flexible Digital Front-End for Sensing in Future Cognitive Radios

Cognitive Radios provide communication devices with the flexibility to adjust to varying network and channel conditions. For this to be fully realizable spectrum sensing and signal reception have to happen simultaneously and have to require as little power as necessary to function in handheld devices. This work argues for the need of flexible digital-front ends as indispensable building block, able to perform control operations over the analog front-end and to perform sensing and synchronization procedures without the need of power consuming baseband processors. A low power, reconfigurable digital front-end that supports concurrent synchronization and sensing of high-throughput wireless standards is presented. Multiple operating modes, useful for various communication standards, such as LTE, WLAN and DVB-T are introduced and analyzed. The digital front-end has been implemented in 65 nm CMOS technology resulting in a chip area of 6.4 mm2. Fine grain clock gating allows synchronization at 4 mW and sensing at 7 mW power consumption. Experiments in combination with a reconfigurable analog front-end show that a 1.7 GHz wide frequency band can be scanned based on energy detection in an exceptionally low time window of 10 ms while consuming 13 mW power and that coarse energy detection can speed-up the sensing process. Furthermore, advanced feature detection for DVB-T and LTE signals is implemented and measured. Low power sensing of DVB-T signals shows that a target false alarm rate of 10 % and a detection probability of 90 % at an input power level of?106 dBm while consuming 7 mW power are possible. Synchronization-aided FFT-based LTE sensing with leakage cancellation was experimentally validated for various bandwidths showing a power consumption of maximum 20 mW.     

Low-power CMOS distributed amplifier using new cascade gain cell for high and low gain modes

A CMOS distributed amplifier (DA) with low-power and flat and high power gain (S₂₁) is presented. In order to decrease noise figure (NF) an RL terminating network used for the gate transmission line instead of single resistance. Besides, a flat and high S₂₁ is achieved by using the proposed cascade gain cell consist of a cascode-stage with bandwidth extension capacitor. In the high-gain mode, under operation condition of V _dd  = 1.2 V and the overall current consumption of 7.8 mA, simulation result shown that the DA consumed 9.4 mW and achieved a flat and high S₂₁ of 20.5 ± 0.5 dB with an average NF of 6.5 dB over the 11 GHz band of interest, one of the best reported flat gain performances for a CMOS UWB DA. In the low-gain mode, the DA achieved average S₂₁ of 15.5 ± 0.25 dB and an average NF of 6.6 dB with low power consumption (P_DC) of 3.6 mW, the lowest P_DC ever reported for a CMOS DA or LNA with an average gain better than 10 dB.     

New fully-differential amplifier-less pipelined ADC with wide power scalability and ERBW

A 24 GHz power amplifier for direct-conversion transceiver using standard 0.18 μm CMOS technology is reported. The three-stage power amplifier comprises two cascaded cascode stages for high power gain, followed by a common-source stage for high power linearity. To increase the saturated output power (P_sat) and power-added efficiency (PAE), the output stage adopts a Wilkinson-power-divider- and combiner-based two-way power dividing and combining architecture. The power amplifier consumes 163.8 mW and achieves power gain (S₂₁) of 22.8 dB at 24 GHz. The corresponding 3-dB bandwidth of S₂₁ is 4.2 GHz, from 22.7 to 26.9 GHz. At 24 GHz, the power amplifier achieves P_sat of 15.9 dBm and maximum PAE of 14.6 %, an excellent result for a 24 GHz CMOS power amplifier. In addition, the measured output 1-dB compression point (OP_1dB) is 7 dBm at 24 GHz. These results demonstrate the proposed power amplifier architecture is very promising for 24 GHz short-range communication system applications.     

Current-mode analogue interface for high-speed low-current differential signalling

In this work, we propose high-speed low-current differential signalling (LCDS) over an electrical chip-to-chip interconnect by using a common-gate transimpedance amplifier followed by a common-source TIA stage. LCDS uses a current-mode receiver compared to a conventional voltage-mode receiver used in most of the signalling technologies such as low-voltage differential signalling, voltage-mode signalling and current-mode logic. The minimum detectable signal level possible with a current-mode receiver for the targeted bit-error rate (BER) makes LCDS an attractive choice. Also the input impedance of the LCDS receiver can be made equal to 100 Ω differential for matching the characteristic impedance of electrical chip-to-chip interconnect. The complete design, analysis and noise characterisation of the TIA front-end is presented. The CGCSTIA is implemented in 1.8 V, 0.18 μm digital CMOS technology. The input-referred noise current and 3-dB bandwidth of the receiver are 1.57 μA and 5.75 GHz, respectively. For the targeted BER of 10^?12, a data transfer rate of 6 Gb/s is achieved, while transmitting the data over a FR4 PCB trace of length 20 cm. The power dissipated in the current-mode receiver is 3.6 mW.     

CMOS electrochemical measurement circuit for biomolecular detection

This paper presents a three-electrode potentiostat transducer circuit for electrochemical sensing system designed for biomolecular detection. Melatonin has been found to be used as a significant index of potential breast cancer risk. The proposed chip automatically measures the redox current which depends on the concentration of melatonin in the analyte solution. Moreover, a current-to-time converter is designed to convert the sensed current into the proportional digitized time signal for back-end signal processing. Cyclic voltammetry and molecularly imprinted polymers were used in the experiments. The sensing electrodes were coated with a thin film imprinted with the target molecule. Fabricated in the TSMC CMOS 0.18 μm 1P6M technology, the proposed chip has a core chip size of 0.083 mm² and a power consumption of 1.143 mW with a 1.8 V supply voltage. This chip can measure the sensed current from ±15 to ±1500 µA with a linearity of R² = 0.999. In the cyclic voltammetry measurement, this chip has an error of less than 0.7%. The urine measurement results of the proposed chip were compared with that of enzyme-linked immune sorbent assay. Verified by melatonin concentration measurement, the proposed chip with high sensitivity demonstrates the feasibility of melatonin concentration detection, which contributes to the examination of breast cancer.     

Room-Temperature Quantum Cascade Laser: ZnO/Zn1−x Mg x O Versus GaN/Al x Ga1−x N

A ZnO/Zn_1?x Mg _x O-based quantum cascade laser (QCL) is proposed as a candidate for generation of THz radiation at room temperature. The structural and material properties, field dependence of the THz lasing frequency, and generated power are reported for a resonant phonon ZnO/Zn_0.95Mg_0.05O QCL emitting at 5.27 THz. The theoretical results are compared with those from GaN/Al _x Ga_1?x N QCLs of similar geometry. Higher calculated optical output powers [ $ {P}_{\rm{ZnMgO}} $  = 2.89 mW (nonpolar) at 5.27 THz and 2.75 mW (polar) at 4.93 THz] are obtained with the ZnO/Zn_0.95Mg_0.05O structure as compared with GaN/Al_0.05Ga_0.95N QCLs [ $ {P}_{\rm{AlGaN}} $  = 2.37 mW (nonpolar) at 4.67 THz and 2.29 mW (polar) at 4.52 THz]. Furthermore, a higher wall-plug efficiency (WPE) is obtained for ZnO/ZnMgO QCLs [24.61% (nonpolar) and 23.12% (polar)] when compared with GaN/AlGaN structures [14.11% (nonpolar) and 13.87% (polar)]. These results show that ZnO/ZnMgO material is optimally suited for THz QCLs.     

Design and analysis of negative capacitor by using MOSFETs

In this paper, a new circuit to synthesise negative capacitor by using MOSFETs is proposed. This circuit has been analysed exactly. Output admittance, value of negative capacitor and frequency limitations of proposed architecture, has been investigated accurately and related equations are obtained theoretically in presence of all parasitic capacitors. Also, this new negative capacitor structure is simulated in TSMC 0.13 µm CMOS Technology. Simulation results confirm the analytical predictions. By variation of g_m and C_X in proposed architecture, negative capacitor can be obtained in higher frequencies up to 15 GHz.     

L, C and X band integrated synthetic aperture radar (SAR) receiver

An integrated receiver consisting of RF front ends, analog baseband (BB) chain with an analog to digital converter (ADC) for a synthetic aperture radar (SAR) implemented in 130 nm CMOS technology is presented in this paper. The circuits are integrated on a single chip with a size of 10.88 mm². The RF front end consists of three parallel signal channel intended for L, C and X-band of the SAR receiver. The BB is selectable between 50 and 160 MHz bandwidths through switches. The ADC has selectable modes of 5, 6, 7 and 8 bits via control switches. The receiver has a nominal gain of 40 and 37 dB and noise figure of 11 and 13.5 dB for 160 MHz BB filter at room temperature for L-band and C-band, respectively. The circuits, which use a 1.2 V supply voltage, dissipate maximum power of 650 mW with 50 MHz BB and 8 bit mode ADC, and maximum power of 800 mW with 160 MHz BB and 8 bit mode ADC.     

High Efficiency and Wideband 300 GHz Frequency Doubler Based on Six Schottky Diodes

A high efficiency and wideband 300 GHz frequency doubler based on six Schottky diodes is presented in this paper. This balanced doubler features a compact and robust circuit on a 5-μm-thick, 0.36-mm-wide, and 1-mm-long GaAs membrane, fabricated by LERMA-C2N Schottky process. The conversion efficiency is mainly better than 16% across the wide bandwidth of 266–336 GHz (3 dB fractional bandwidth of 24%) when pumping with 20–60 mW input power (P _in) at the room temperature. A peak output power of 14.75 mW at 332 GHz with a 61.18 mW P _in, an excellent peak efficiency of 30.5% at 314 GHz with 43.86 mW P _in and several frequency points with outstanding efficiency of higher than 25% are delivered. This doubler served as the second stage of the 600 GHz frequency multiplier chain is designed, fabricated, and measured. The performance of this 300 GHz doubler is highlighted comparing to the state-of-art terahertz frequency doublers.     

Energy efficient collaborative communications in AWGN and Rayleigh fading channel in wireless sensor networks

Collaborative communication produces high power gain and significantly reduces bit error rate (BER) if both frequency and phase synchronization are achieved. In this paper, a novel collaborative communication system with imperfect phase and frequency synchronization that includes the influence of noise and fading is proposed, modeled, theoretically analyzed, and simulated. Mathematical expressions are derived for the received power as a function of number of collaborative nodes and BER as a function of signal to noise ratio (E_b ∕ N₀). To analyze the energy efficiency of our proposed collaborative communication system, energy consumption of the system is modeled, simulated, and analyzed by considering the parameters of the off‐the‐shelf products. Analytical and simulation results showed that the proposed system produces significant power gain and reduction in BER in the presence of phase errors, frequency errors, additive white Gaussian noise, and Rayleigh fading. A detailed theoretical analysis and Monte Carlo simulation revealed that the proposed collaborative communication system is an energy efficient communication system that can be implemented in sensor networks, as approximately N (number of collaborative nodes) times less total transmitted power is required than for the single input single output communication for a specifies transmission range. Copyright © 2012 John Wiley & Sons, Ltd.     

A direct-conversion CMOS transceiver for the 802.11a/b/g WLAN standard utilizing a Cartesian feedback transmitter

A fully integrated dual-band transceiver is implemented in 0.18-/spl mu/m CMOS and is compliant with the IEEE 802.11a/b/g standards. The direct-conversion transceiver occupies 12 mm/sup 2/ in a QFN-40 package. A fractional-N synthesizer operates at twice the channel frequency, covering continuously bands from 4.9 to 5.9 GHz, as well as the 2.4-GHz band. The 5- and 2.4-GHz receivers achieve a sensitivity level below -73 dBm in the 54-Mb/s mode and below -93 dBm in the 6-Mb/s mode, while consuming 230 mW. A fast RSSI-channel power-detection system allows to power-down signal processing in the listen mode. The 5- and 2.4-GHz transmitters implement a wideband Cartesian feedback loop for enhanced EVM performances and improved spectrum masks compliance. The transmitters deliver -2-dBm average power with an EVM of 3% in the 54-Mb/s mode while consuming 300 mW.     

Equalization and pre-emphasis based LVDS transceiver

This work presents an area-efficient, low-power, high data rate low voltage differential signal (LVDS) transmitter and receiver with signal quality enhancing techniques. The proposed common mode feedback scheme significantly reduces the size of the LVDS transmitter by eliminating the use of area consuming passive resistor and capacitor used for close loop stability compensation. A preemphasis technique has been introduced to enhance the transmitter output’s signal quality without significantly increasing the power draw. On the receiver part, an equalization technique has also been introduced to further enhance signal quality, increases data rate and improved jitter with relatively low power consumption. The LVDS transmitter consumes 5.4 mA of current while driving an external 100 ohm resistor with an output voltage swing of 440 mV. The chip consumes an area of 0.044 mm². This LVDS receiver has an input common mode range from 0.1 to 1.6 V. It consumes 34 mW of power with a maximum data rate of 2 Gbps. It consumes an area of 0.147 mm² a jitter of 11.74 ps rms. A test chip is implemented using 0.18 μm CMOS process.