Wideband and multiband CMOS LNAs: State-of-the-art and future prospects

The realization of Software Defined Radio (SDR) requires flexible RF front-end to accommodate multiple standards in different frequency bands. In this review paper, we survey the literature over the period 1995–2011 and discuss the state-of-the-art multiband and wideband LNAs in context of different receiver architectures suitable for SDR. Wideband and multiband LNA designs reported in open literature are categorized on the basis of their circuit architecture. Measured results of the sample LNA designs from each category are tabulated and discussed with emphasis on power consumption, NF, gain, linearity, and impedance matching tradeoffs. We have also discussed our own three wideband inductorless LNA design prototypes which are manufactured in 0.13 µm and 90 nm CMOS. This review infers that future LNAs suitable for SDR must be highly linear and scalable with future technology nodes.     

Low-Area Active-Feedback Low-Noise Amplifier Design in Scaled Digital CMOS

The emerging concept of multistandard radios calls for low-noise amplifier (LNA) solutions able to comply with their needs. Meanwhile, the increasing cost of scaled CMOS pushes towards low-area solutions in standard, digital CMOS. Feedback LNAs are able to meet both demands. This paper is devoted to the design of low-area active-feedback LNAs. We discuss the design of wideband, narrowband and multiband implementations. We demonstrate that competitive RF performance is achievable thanks to CMOS downscaling, pleasing many applications because of their low cost (digital CMOS) and low area (bondpad size).      

A 0.3–3.5 GHz active-feedback low-noise amplifier with linearization design for wideband receivers

LNAs for wideband receivers usually require a high linearity to protect the desired signals from out-band interference. Active feedback LNAs always suffer from the nonlinear feedback of source follower, and present a poor linearity. In order to solve this problem, a complementary source follower (CSF) is proposed, which utilizes the different characteristic of NMOS and PMOS to linearize the source follower, leading to an improvement of LNA’s IIP₃ and IIP₂ by about 10 dBm and 21 dBm respectively. In addition, a post-distortion technique is also used on the common source stage, which further enhances the IIP₃ by about 2 dBm and IIP₂ by 11 dBm. After using the two techniques, the noise figure (NF) does not deteriorate; instead it achieves a 0.3 dB improvement. A prototype is designed in TSMC 0.18 μm CMOS process, and a 14.8 mW power is dissipated from a 1.6 V supply. In typical process corner, across 0.3 to 3.5 GHz, this LNA achieves a 14.6 dB gain, a 2.9 dB minimum NF, and an IIP₂ larger than +22 dBm and IIP₃ larger than +1.2 dBm.     

Ultra-low power LNA design technique for UWB applications

In this paper, a design technique to improve low noise amplifier (LNA) performance is proposed. This technique is based on a new operating parameter (OP) of MOSFETs for radio frequency (RF) applications. This technique is used to optimize low noise amplifier (LNA) parameters for Ultra-Wideband (UWB) applications. The presented methodology predicts the optimum biasing point to maximize LNA performance. Simulation results show that the proposed methodology can increase the figure of merit (FoM) by 70% compared to traditional methodologies, without having a significant effect on either noise figure (NF) or linearity characteristics.     

Low power high gain CMOS LNA based on inverter cell and self-body bias for UWB receivers

A low-power low-noise amplifier (LNA) utilized a resistive inverter configuration feedback amplifier to achieve the broadband input matching purposes. To achieve low power consumption and high gain, the proposed LNA utilizes a current-reused technique and a splitting-load inductive peaking technique of a resistive-feedback inverter for input matching. Two wideband LNAs are implemented by TSMC 0.18 μm CMOS technology. The first LNA operates at 2–6 GHz. The minimum noise figure is 3.6 dB. The amplifier provides a maximum gain (S₂₁) of 18.5 dB while drawing 10.3 mW from a 1.5-V supply. This chip area is 1.028×0.921 mm². The second LNA operates at 3.1–10.6 GHz. By using self-forward body bias, it can reduce supply voltage as well as save bias current. The minimum noise figure is 4.8 dB. The amplifier provides a maximum gain (S₂₁) of 17.8 dB while drawing 9.67 mW from a 1.2-V supply. This chip area is 1.274×0.771 mm².     

An inductorless wideband common-gate LNA with dual capacitor cross-coupled feedback and negative impedance techniques

A wideband common-gate (CG) low-noise amplifier (LNA) with dual capacitor cross-coupled (CCC) feedback and negative impedance techniques is presented for multimode multiband wireless communication applications. Double CCC technique boosts the input transconductance of the LNA, and low power consumption is obtained by using current-reuse technique. Negative impedance technique is employed to alleviate the correlation between the transconductance of the matching transistors and input impedance. Meanwhile, it also allows us to achieve a lower noise figure (NF). Moreover, current bleeding technique is adopted to allow the choice of a larger load resistor without sacrificing the voltage headroom. The proposed architecture achieves low noise, low power and high gain simultaneously without the use of bulky inductors. Simulation results of a 0.18-μm CMOS implementation show that the proposed LNA provides a maximum voltage gain of 25.02 dB and a minimum NF of 2.37 dB from 0.1 to 2.25 GHz. The input-referred third-order intercept point (IIP3) and input 1-dB compression point (IP_1dB) are better than –7.8 dBm and –19.2 dBm, respectively, across the operating bandwidth. The circuit dissipates 3.24 mW from 1.8 V DC supply with an active area of 0.03 mm².     

S-band low noise amplifier using 1 μm InGaAs/InAlAs/InP pHEMT

This paper discusses the design of a wideband low noise amplifier (LNA) in which specific architecture decisions were made in consideration of system-on-chip implementation for radio-astronomy applications. The LNA design is based on a novel ultra-low noise InGaAs/InAlAs/InP pHEMT. Linear and non-linear modelling of this pHEMT has been used to design an LNA operating from 2 to 4 GHz. A common-drain in cascade with a common source inductive degeneration, broadband LNA topology is proposed for wideband applications. The proposed configuration achieved a maximum gain of 27 dB and a noise figure of 0.3 dB with a good input and output return loss (S₁₁ < -10 dB, S₂₂ < -11 dB). This LNA exhibits an input 1-dB compression point of -18 dBm, a third order input intercept point of 0 dBm and consumes 85 mW of power from a 1.8 V supply.     

1MHz～40GHz超宽带分布式低噪声放大器设计

为满足宽带系统中低噪声放大器(LNA)宽带的要求,采用0.15μm GaAs赝配高电子迁移率晶体管(PHEMT)工艺,设计了两款1 MHz^40 GHz的超宽带LNA,分别采用均匀分布式放大器结构及渐变分布式放大器结构,电路面积分别为1.8 mm×0.85 mm和1.8 mm×0.8 mm。电磁场仿真结果表明,1 MHz^40 GHz频率范围内,均匀分布式LNA增益为15.3 dB,增益平坦度为2 dB,噪声系数小于5.1 dB;渐变分布式LNA增益为14.16 dB,增益平坦度为1.74 dB,噪声系数小于3.9 dB。渐变分布式LNA较均匀分布式LNA,显著地改善了增益平坦度、噪声性能和群延时特性。     

Performance analysis of impulse‐radio ultra‐wideband energy detector system using cooperative dual‐hop amplify and forward strategy

A novel analytical representation of bit error rate (BER) performance of an impulse‐radio ultra‐wideband energy detector on–off keying system using cooperative dual‐hop amplify and forward relay technology, with various diversity combining schemes over IEEE 802.15.4a environment is presented in this paper. In particular, the approximate expressions based on energy detection principle are derived for various diversity combining cases, namely linear optimal combining, linear combining, and selective combining. Simulation results depict an improvement in BER performance, with increase in number of relay paths (L ) and decrease in number of frames per symbol (N _f ). Furthermore, the BER performance of the impulse‐radio ultra‐wideband energy detector on–off keying system improves substantially using dual‐hop cooperative amplify and forward scheme, compared with that of non‐cooperative or single link scenario. Among the diversity combining schemes, linear optimal diversity combining performs better when compared with linear diversity combining and selective combining. The analytical BER expressions are validated with the simulation results, which confirm the accuracy and precision in approximation used in the investigation of BER. Copyright © 2015 John Wiley & Sons, Ltd.     

Device and technology evolution for Si-based RF integrated circuits

The relationships between device feature size and device performance figures of merit (FoMs) are more complex for radio frequency (RF) applications than for digital applications. Using the devices in the key circuit blocks for typical RF transceivers, we review and give trends for the FoMs that characterize active and passive RF devices. These FoMs include transit frequency at unity current gain f/sub T/, maximum frequency of oscillation f/sub MAX/ at unit power gain, noise, breakdown voltage, capacitor density, varactor and inductor quality, and the like. We use the specifications for wireless communications systems to show how different Si-based devices may achieve acceptable FoMs. We focus on Si complementary metal-oxide-semiconductor (CMOS), Si Bipolar CMOS, and Si bipolar devices, including SiGe heterojunction bipolar transistors, RF devices, and integrated circuits (ICs). We analyze trends in the FoMs for Si-based RF devices and ICs and show how these trends relate to the technology nodes of the 2003 International Technology Roadmap for Semiconductors. We also compare FoMs for the best reported performance of research devices and for the performance of devices manufactured in high volumes, typically more than 10 000 devices. Certain commercial equipment, instruments, or materials are identified in this article to specify adequately the experimental or theoretical procedures. Such identification does not imply recommendation by any of the host institutions of the authors, nor does it imply that the equipment or materials are necessarily the best available for the intended purpose.     

High Performance Millimeter‐Wave Image Reject Low‐Noise Amplifier Using Inter‐stage Tunable Resonators

A Q‐band pHEMT image‐rejection low‐noise amplifier (IR‐LNA) is presented using inter‐stage tunable resonators. The inter‐stage L‐C resonators can maximize an image rejection by functioning as inter‐stage matching circuits at an operating frequency (F_OP) and short circuits at an image frequency (F_IM). In addition, it also brings more wideband image rejection than conventional notch filters. Moreover, tunable varactors in L‐C resonators not only compensate for the mismatch of an image frequency induced by the process variation or model error but can also change the image frequency according to a required RF frequency. The implemented pHEMT IR‐LNA shows 54.3 dB maximum image rejection ratio (IRR). By changing the varactor bias, the image frequency shifts from 27 GHz to 37 GHz with over 40 dB IRR, a 19.1 dB to 17.6 dB peak gain, and 3.2 dB to 4.3 dB noise figure. To the best of the authors' knowledge, it shows the highest IRR and F_IM/F_OP of the reported millimeter/quasi‐millimeter wave IR‐LNAs.     

一种具有新型增益控制技术的CMOS宽带可变增益LNA

高速超宽带无线通信的多标准融合是未来射频器件的发展趋势,该文提出一种基于CMOS工艺、具有新型增益控制技术的宽带低噪声放大器(LNA),采用并联电阻反馈实现宽带输入匹配,并引入噪声消除技术来减小噪声以提高低噪声性能;输出带有新型6位数字可编程增益控制电路以实现可变增益。采用中芯国际0.13m RF CMOS工艺流片,芯片面积为0.76 mm2。测试结果表明LNA工作频段为1.1-1.8 GHz,最大增益为21.8 dB、最小增益8.2 dB,共7种增益模式。最小噪声系数为2.7 dB,典型的IIP3为-7 dBm。     

Design of low power UWB LNA based on common source topology with current-reused technique

This paper presents two low power UWB LNAs with common source topology. The power reduction is achieved by the current-reused technique. The gain and noise enhancement of the proposed circuit is based on an output buffer which is used by a common source amplifier with shunt–shunt feedback. Chip1 is an adopted T-match input network of 50 Ω matching in the required band. Measurements show that the S₁₁ and S₂₂ are less than −10 dB, and the maximum amplifier gain S₂₁ gives 9.7 dB, and the noise figure is 4.2 dB, the IIP3 is −8.5 dBm, and the power consumption is 11 mW from 1.1 V supply voltage. The input matching of chip2 is adopted from a LC high pass filter and source degenerated inductor. The output buffer with the RC-feedback topology can improve the gain, increase the IIP3, restrain the noise, improve the noise figure and decrease the DC power dissipation. Measurements show 13.2 dB of power gain, 3.33 dB of noise figure, and the IIP3 is −3.3 dBm. It consumes 9.3 mW from 1.5 V supply voltage. These two chips are implemented in a 0.18 μm TSMC CMOS process.     

超宽带射频接收机的研制

超宽带(UWB)短距离无线通信技术是当前国内外研究的热点,直接序列超宽带(DS-UWB)方案和多带－正交频分复用(MB-OFDM UWB)方案是两个主要候选方案,其中多带-正交频分复用方案是较受重视的方案.本文针对MB-OFDM UWB系统,提出了一种双载波-正交频分复用(DC-OFDM UWB)的射频解决方案.该方案采用了两个相邻的子载波实现宽带通信,两个子载波是在中频部分采用合路/分路的方式,以降低硬件实现难度和系统的复杂度.设计了UWB射频接收机中的低噪声放大器(LNA)、频率合成器和解调器等关键部件,并建立了DC-OFDM UWB接收机实验演示平台.测试结果表明,研制的射频接收机满足FCC规定的射频指标要求,该方案也适用于其它的宽带通信系统中.     

SiGe LNAs for UMTS System

Three LNAs at 2 GHz frequency range have been implemented in a SiGe Bipolar process targeted for a universal mobile telecommunications system. The LNAs are operating in two gain modes and they include a power-down mode. Both on-wafer and packaged LNAs were measured. Noise figure below 2 dB with IIP3 of 1 dBm and gain exceeding 15 dB has been achieved. LNAs work from a 2.7–5.5 V power supply. A figure of merit method is used to compare this work to other published LNAs.     

Noise current feedforward for noise cancellation in the wideband transformer shunt feedback low noise amplifier

A noise current feedforward (NCF) technique for noise cancellation in the wideband transformer shunt feedback (TSF) low noise amplifier (LNA) is proposed. The NCF can detect and cancel the thermal noise of the TSF network. It is also suitable to cancel those noise contributed by the passive unilateral shunt feedback networks in common current mode LNAs. Implemented in SMIC 0.18 μm CMOS process and operated in the typical radio astronomy frequency range from 0.6 GHz to 1.6 GHz, the TSF LNA that employs the NCF shows approximately 0.2–0.5 dB lower noise figure than the overwhelming resistive shunt feedback LNA that exploits a conventional noise voltage feedforward technique when consuming the same power.     

宽带数字接收机中ADC的设计与应用

宽带数字化接收机是当前无线通信领域的一个研究热点,高速模拟/数字转换器ADC又是实现数字化接收机的核心部件。首先简述了宽带数字接收机与传统窄带数字接收机结构上的差别,然后着重研究了ADC对接收机性能的影响。最后还列举了AD9042芯片在宽带数字接收机中的设计与应用。     

CMOS低噪声放大器的噪声系数优化研究

由于CMOS晶体管的特征尺寸急速的缩放,CMOS晶体管的参数不断改进,使得最新CMOS晶体管获得的噪声系数足够低到足以应用到无线电天文学,因此,在本研究课题中选用CMOS晶体管。目前的低噪声放大器的最小噪声系数是在室温环境下,通过宽带CMOS低噪声放大器的功率匹配来获得。在本研究课题中,CMOS低噪声放大器以共源共栅极结构为基本拓扑结构,主要研究LNA的几种常用的噪声系数优化方法。通过建立小信号模型,对LNA的噪声系数进行分析,得出相应的表达式。     

Analysis of Joint Multiband Sensing‐Time M‐QAM Signal Detection in Cognitive Radios

We analyze a wideband spectrum in a cognitive radio (CR) network by employing the optimal adaptive multiband sensing‐time joint detection framework. This framework detects a wideband M‐ary quadrature amplitude modulation (M‐QAM) primary signal over multiple nonoverlapping narrowband Gaussian channels, using the energy detection technique so as to maximize the throughput in CR networks while limiting interference with the primary network. The signal detection problem is formulated as an optimization problem to maximize the aggregate achievable secondary throughput capacity by jointly optimizing the sensing duration and individual detection thresholds under the overall interference imposed on the primary network. It is shown that the detection problems can be solved as convex optimization problems if certain practical constraints are applied. Simulation results show that the framework under consideration achieves much better performance for M‐QAM than for binary phase‐shift keying or any real modulation scheme.