Three novel single-stage full swing 3-input XOR

In this paper, three novel designs for single-stage, 3-input XOR logic cells are proposed. The design uses either Transmission Gate (TG) or Pass Transistor (PT) on similar topologies. The proposed circuits are area and power efficient because minimum-sized transistors are used in ratioless realisations. At the output, the designs give strong logic-levels. The topologies have minimised delay because the critical path consists of only three minimum-sized transistors. The delay estimation is presented. The circuits are simple and layouts are easy to build. Further, rail-to-rail voltage-swing at the output ensures good driving capability even at low voltages and at high frequencies ranging up to 10 GHz with minimum transistor count. The proposed designs and other existing candidate designs are simulated in a pragmatic condition on Cadence 90 nm CMOS technology at various supply voltages ranging from +0.8 V to +1.2 V. The simulation results illustrate that the proposed designs have comparable delay time to most candidate designs while it outperform all of them on total power consumption and PDP. As expected, the TG-based design reports best performance while the PT-based design follow as closed second with better component economy and control input overload. An application of the proposed XORs in ripple carry adders confirms the functionality of the cells in circuit implementation.     

一种低资源消耗的运动估计VLSI实现算法

现有的VLSI(verylarge scale integration)视频编码芯片多使用全搜索运动估计(ME)方法,且没有搜索中心偏移(CB)的并行实现方法。本文提出一种适合VLSI的H.264、AVS CB并行搜索方案,减少搜索点数量,降低逻辑资源的消耗,并且使用预测高概率区域的方法,保证ME精度。实验表明,本方法具备较好的率失真性能。在现场可编程门阵列(FPGA)平台上实现了本算法,逻辑综合的数据表明,硬件资源消耗降低了64%。本算法可应用于标清和高清电视(HDTV,hign-definition television)视频编码器。     

超大规模集成电路的可制造性设计

以Synopsys推出的TCAD软件TSUPREM-Ⅳ和Medici为蓝本,结合100nm栅长PMOSFET的可制造性联机仿真与优化实例,阐述了超大规模集成电路DFM阶段所进行的工艺级、器件物理特性级优化及工艺参数的提取。     

Fast low-power full-adders based on bridge style minority function and multiplexer for nanoscale

Full-adders are essential parts of digital circuits whereby many arithmetic circuits can be implemented by applying these cells. Therefore speed and power consumption of full-adders affect the performance of digital circuits, FA cell performs a predominant arithmetic operation in them. We utilise carbon nanotube field effect transistors for implementing our proposed designs due to their unique mechanical and electrical properties such as lower delay, lower power consumption, very dense and lower current off. Extensive simulation results using HSpice are reported to demonstrate the acquired significant improvement in performance of FA circuit design in comparison with the state-of-the-art work.     

一种电迁移测试失效时间判定方法

采用铜大马士革工艺制备了用于电迁移测试的样品,对电迁移测试过程中存在的两类电阻-时间(R-t)特征曲线进行了研究.研究发现采用固定电阻变化率作为失效判定标准所得的失效时间分布曲线不能真实地反映样品的实际寿命,而采用第一次阻值跳变点对应的时间作为失效时间所得的分布曲线则更符合电迁移理论.针对两种失效判定方法所得到的不同结果进行了机理分析,结果表明,采用第一次阻值跳变点对应的时间作为失效时间分析电迁移失效更合理.     

CDPD系统中RS译码器的改进设计与实现

以蜂窝数字分组数据(CDPD)系统中的RS(63,47)码为例,提出了一种建立在伽罗华域(GaloisFields)广义三角基乘法器基础上的改进的Reed-Solomon译码器电路。在该译码器的设计中,针对CDPD系统中RS(63,47)码的特点,采用了改进的快速钱氏-BRS根搜索算法来求解它的根并且应用流水线等技术来优化系统设计,从而节省了硬件资源并且提高了速度,使得译码器的性能得到很大的改善。所设计的译码器不但完全满足CDPD系统的设计要求,而且电路结构易于超大规模集成电路(VLSI)的实现,具有广泛的适用范围。     

Edge‐Preserving Algorithm for Block Artifact Reduction and Its Pipelined Architecture

This paper presents a new edge‐protection algorithm and its very large scale integration (VLSI) architecture for block artifact reduction. Unlike previous approaches using block classification, our algorithm utilizes pixel classification to categorize each pixel into one of two classes, namely smooth region and edge region, which are described by the edge‐protection maps. Based on these maps, a two‐step adaptive filter which includes offset filtering and edge‐preserving filtering is used to remove block artifacts. A pipelined VLSI architecture of the proposed deblocking algorithm for HD video processing is also presented in this paper. A memory‐reduced architecture for a block buffer is used to optimize memory usage. The architecture of the proposed deblocking filter is verified on FPGA Cyclone II and implemented using the ANAM 0.25 µm CMOS cell library. Our experimental results show that our proposed algorithm effectively reduces block artifacts while preserving the details. The PSNR performance of our algorithm using pixel classification is better than that of previous algorithms using block classification.     

High-speed optical binary data pattern recognition for network security applications

All-optical high-speed binary data pattern recognition is one of the key technologies in network security applications.A serial pattern recognition scheme is presented,which can detect and locate a spe...     

多通道PCI总线DMA控制器的软硬件联合设计

对一种支持128个用户的PCI(Peripheral Component Interconnect)总线直接存储器访问控制器(DMAC：Direct Memoory Access Controller)电路所采用的电路结构进行了分析，在任务级上对电路的功能进行了划分，并通过仿真得到了不同任务分别在采用嵌入式软件和硬件逻辑电路实现时的时间开销和硬件资源开销。在此基础上，采用面向软件的软硬件联合设计方法，以13．5万等效门实现了整个设计，并通过现场可编程门阵列(FPGA)在实际应用系统中进行了功能验证。     

OFDM系统同步算法研究及其VLSI实现

针对正交频分复用（OFOM, Orthogonal Frequency Division Multiplex）无线传输系统,提出并设计了一种适用于802．11a标准前导序列的同步算法。首先基于接收基带数据能量判断信道空闲状态,再计算数据归一化自相关值检测帧起始位置,最后利用基带数据与参考训练序列的互相关运算检测OFDM符号的起始位置,实现同步功能。算法的硬件实现采用移位加和流水线技术来提高系统的性能与效率。实践表明,所提算法能有效地实现同步并且硬件实现复杂度低,适合于超大规模集成电路（VLSI,Very LargeScale Integration）的实现。     

High Throughput Parallel-Pipeline 2-D DCT/IDCT Processor Chip

This paper presents a 2-D DCT/IDCT processor chip for high data rate image processing and video coding. It uses a fully pipelined row–column decomposition method based on two 1-D DCT processors and a transpose buffer based on D-type flip-flops with a double serial input/output data-flow. The proposed architecture allows the main processing elements and arithmetic units to operate in parallel at half the frequency of the data input rate. The main characteristics are: high throughput, parallel processing, reduced internal storage, and maximum efficiency in computational elements. The processor has been implemented using standard cell design methodology in 0.35 μm CMOS technology. It measures 6.25 mm² (the core is 3 mm²) and contains a total of 11.7 k gates. The maximum frequency is 300 MHz with a latency of 172 cycles for 2-D DCT and 178 cycles for 2-D IDCT. The computing time of a block is close to 580 ns. It has been designed to meets the demands of IEEE Std. 1,180–1,990 used in different video codecs. The good performance in the computing speed and hardware cost indicate that this processor is suitable for HDTV applications. This work was supported by the Spanish Ministry of Science and Technology (TIC2000-1289).

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Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m)

An error tolerant hardware efficient very large scale integration (VLSI) architecture for bit parallel systolic multiplication over dual base, which can be pipelined, is presented. Since this architecture has the features of regularity, modularity and unidirectional data flow, this structure is well suited to VLSI implementations. The length of the largest delay path and area of this architecture are less compared to the bit parallel systolic multiplication architectures reported earlier. The architecture is implemented using Austria Micro System's 0.35 m CMOS (complementary metal oxide semiconductor) technology. This architecture can also operate over both the dual-base and polynomial base.     

Low power & mobile hardware accelerators for deep convolutional neural networks

This article provides a comprehensive review of recent developments in the field of computational hardware for mobile low power machine learning hardware accelerators. The article provides an introduction to neural networks, convolutional neural networks and details recent developments in state of the art deep convolutional neural networks. The key considerations in the design of low power hardware accelerators are discussed with reference to a conceptual system. Strategies for reducing the energy cost of memory access and computation in state of the art hardware accelerators are detailed. This includes techniques such as dataflow, reduced precision, model compression and sparsity. Recent reported digital mobile accelerators for deep convolutional neural networks with power consumptions of less than 3.3 W are observed to have 4x-20x better efficiency than the reference GPU accelerator at 16-bit precision, and can achieve 20x-1171x better efficiency at less than 4-bit precision. Efficiency improvements of 20x-1171x over a GPU is observed for reported mobile accelerators with reduced precision.     

Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF（2^m）

An error tolerant hardware efficient verylarge scale integration （VLSI） architecture for bitparallel systolic multiplication over dual base, which canbe pipelined, is presented. Since this architecture has thefeatures of regularity, modularity and unidirectionaldata flow, this structure is well suited to VLSIimplementations. The length of the largest delay pathand area of this architecture are less compared to the bitparallel systolic multiplication architectures reportedearlier. The architecture is implemented using Austria Micro System＇s 0.35 μm CMOS （complementary metaloxide semiconductor） technology. This architecture canalso operate over both the dual-base and polynomialbase.     

超大规模集成电路多孔电介质介电常数与分形维数

技术的发展要求超大规模集成电路的特征尺寸进一步降低以提高元件密度,这就需要低介电常数(k)的多孔电介质的应用.而多孔介质的输运物理性质通常与其微结构有密切关系.本文在综述多孔电介质利用分形模型分析方法的基础上,利用分形几何理论,进一步把多孔电介质介电常数(k)与反映孔微结构的分形维数联系起来,更好地适应于实际中不均一不规则的多孔电介质介电常数的分析计算.     

Parametrized and reusable VLSI macro cells for the low-power realization of 2-D discrete-cosine-transform

The problem of an efficient VLSI realization of the 2-D discrete-cosine-transform and its inverse is addressed in this paper. Two circuits implementing both functions are discussed and characterized from the high-level architectural choices down to the gate-level synthesis on different standard-cell target technologies. The circuits are designed as parametric intellectual property (IP) cells according to a design reuse policy that allows the user to select the most convenient solution for the considered application. Synthesis results show that the circuits are suitable for real time processing of various image formats adopted in H.263/MPEG compression standards. Power consumption reduction methods (clock gating, switching activity reduction) are used according to the statistics of the input signals to reduce the dissipated power. The effects of supply voltage scaling and its consequence on circuit performance are examined in detail, as well as the use of different target technologies. Finally, a comparison with dedicated full-custom low-power circuits presented in the literature show that these IP cells stand for flexibility, parametrization and reusability, still maintaining comparable power consumption and area occupation.     

Characteristics of PECVD grown tungsten nitride films as diffusion barrier layers for ULSI DRAM applications

We have developed tungsten nitride (W-Nitride) films grown by plasma enhanced chemical vapor deposition (PECVD) for barrier material applications in ultra large scale integration DRAM devices. As-deposited W-Nitride films show an amorphous structure, which transforms into crystalline, β-W₂N and α-W phases upon annealing at 800°C. The resistivity of the as-deposited films grown at the NH₃/WF₆ gas flow ratio of 1 is about 160 μω-cm, which decreases to 50 μω-cm after an rapid thermal annealing treatment at 800°C. In the contact holes with the size of 0.35 μm and aspect ratio of 3.5, the bottom step coverage of the tungsten nitride films is about 60%, which is about three times higher than that of collimated-TiN films. We obtained contact resistance and leakage current with the tungsten nitride barrier layer comparable to those with conventional collimated TiN films. The contact resistance and leakage current are stable upon thermal stressing at 450°C up to 48 h.     

An advanced finite element strategy for thermal stress field investigation in aluminium interconnections during processing of very large scale integration multilevel structures

An advanced strategy for modelling the thermal stress induced in aluminium interconnections during processing of multilevel structures is presented. The advantage of the approach described is that it allows the residual stresses from one processing step to be used as the initial conditions for a subsequent step. 2D elasto-plastic model (von Mises plastic criterion) is implemented in Finite Element Code and it is shown that even after significant relaxation by plastic deformation, high thermal stress resides in the aluminium line in both width and thickness directions. The technique demonstrated here is for a silicon-glass–aluminium-glass structure. However, it is readily extended to more complex situations and material combinations.     

Process and device modeling for VISI

The appearance of Very Large Scale Integration caused a pronounced interest in concentrating on process and device modeling. The fundamental properties which represent the basis for all device modeling activities are summarized. The sensible use of physical and technological parameters is discussed and the most important physical phenomena which are required to be taken into account are scrutinized. The assumptions necessary for finding a reasonable trade-off between efficiency and effort for a model synthesis are recollected. Methods to bypass limitations induced by these assumptions are pin-pointed. Formulae that are applicable in a simple and easy way for the physical parameters of major importance are presented. The necessity of a careful parameter-selection, based on physical information, is shown. Some glimpses on the numerical solution of the semiconductor equations are given. The discretisation of the partial differential equations with finite differences is outlined. Linearisation methods and algorithms for the solution of large sparse linear systems are sketched. Results of our two dimensional MOSFET model — MINIMOS — are discussed. Much emphasis is laid on the didactic potential of such a complex high order model.     

一种高能效低时延的LLN路由修复算法

由于低功耗有损网络(LLN)中无线链路的不稳定性和有损性,外部环境的干扰极易导致网络出现故障,从而严重影响网络性能,而LLN网络中现有路由修复算法存在控制开销冗余和修复时延较大等问题。为此,提出了一种高能效低时延的LLN路由修复算法(EELDR-RPL)。该算法通过采用“零额外控制开销通告链路故障及邻居节点信息”机制,使得链路故障节点的子节点能够及时获知链路故障以及链路故障节点的邻居情况;通过采用“自适应调整节点网络深度值”机制,使得链路故障节点能够快速地重新接入网络;通过采用“链路故障节点子节点自适应切换”机制,能够达到优化网络拓扑的目的。仿真结果表明,与现有路由修复算法相比,EELDR-RPL算法能够有效地降低路由修复时延和减少控制开销。