22nm技术节点异质栅MOSFET的特性研究

研究了22 nm栅长的异质栅MOSFET的特性,利用工艺与器件仿真软件Silvaco,模拟了异质栅MOSFET的阈值电压、亚阈值特性、沟道表面电场及表面势等特性,并与传统的同质栅MOSFET进行比较。分析结果表明,由于异质栅MOSFET的栅极由两种不同功函数的材料组成,因而在两种材料界面附近的表面沟道中增加了一个电场峰值,相应地漏端电场比同质栅MOSFET有所降低,所以在提高沟道载流子输运效率的同时也降低了小尺寸器件的热载流子效应。此外,由于该器件靠近源极的区域对于漏压的变化具有屏蔽作用,从而有效抑制了小尺寸器件的沟道长度调制效应,但是由于其亚阈值特性与同质栅MOSFET相比较差,导致漏致势垒降低效应(DIBL)没有明显改善。     

Design and optimization analysis of dual material gate on DG-IMOS

An impact ionization MOSFET (IMOS) is evolved for overcoming the constraint of less than 60 mV/decade sub-threshold slope (SS) of conventional MOSFET at room temperature.In this work,first,the device performance of the p-type double gate impact ionization MOSFET (DG-IMOS) is optimized by adjusting the device design parameters.The adjusted parameters are ratio of gate and intrinsic length,gate dielectric thickness and gate work function.Secondly,the DMG (dual material gate) DG-IMOS is proposed and investigated.This DMG DG-IMOS is further optimized to obtain the best possible performance parameters.Simulation results reveal that DMG DG-IMOS when compared to DG-IMOS,shows better ION,ION/IOFF ratio,and RF parameters.Results show that by properly tuning the lengths of two materials at a ratio of 1.5 in DMG DG-IMOS,optimized performance is achieved including ION/IoFF ratio of 2.87 × 109 A/μm with ION as 11.87 × 10-4 A/μm and transconductance of 1.06 × 10-3 S/μm.It is analyzed that length of drain side material should be greater than the length of source side material to attain the higher transconductance in DMG DG-IMOS.     

一种非对称双栅应变硅HALO掺杂沟道MOSFET阈值电压解析模型

提出了一种非对称双栅应变硅HALO掺杂沟道金属氧化物半导体场效应管结构.该器件前栅和背栅由两种不同功函数的金属构成,沟道为应变硅HALO掺杂沟道,靠近源区为低掺杂区域,靠近漏区为高掺杂区域.采用分区的抛物线电势近似法和通用边界条件求解二维泊松方程,分别求解了前背栅表面势、前背栅表面电场及前背栅阈值电压,建立了双栅器件的表面势、表面电场和阈值电压解析模型.详细讨论了物理参数对解析模型的影响.研究结果表明,该器件能够很好的抑制短沟道效应、热载流子效应和漏致势垒降低效应.模型解析结果与DESSIS仿真结果吻合较好,证明了该模型的正确性.     

An analytical drain current model for dual material engineered cylindrical/surrounded gate MOSFET

In this paper, a drain current model incorporating drain-induced barrier lowering (DIBL) has been developed for Dual Material gate Cylindrical/Surrounding gate MOSFET (DMG CGT/SGT MOSFET) and the expressions for transconductance and drain conductance have been obtained. It is shown that DMG design leads to drain current enhancement and reduced output conductance. The effectiveness of DMG design was scrutinized by comparing with single metal gate (SMG) CGT/SGT MOSFET. Moreover, the effect of technology parameters variations workfunction difference has also been presented in terms of gate bias, drain bias, transconductance and drain conductance. Results reveal that the DMG SGT/CGT devices offer superior characteristics as compared to single material gate CGT/SGT devices. A good agreement between modeled and simulated results has also been obtained thus providing the validity of proposed model.     

A surface potential and quasi-Fermi potential based drain current model for pocket-implanted MOS transistors in subthreshold regime

A subthreshold drain current model for pocket-implanted MOS transistors, incorporating both the drift and diffusion currents, is presented in this paper. In this model, the concept of splitting of the quasi-Fermi energy levels under nonequilibrium condition is used. It is well known that the surface potential based drain current models strongly depend on the potential profile of the channel. For short-channel devices, the end effect at the source and drain ends on the surface potential, and consequently on the drain current, cannot be ignored. The end effect gives rise to a position dependent potential profile, in contrast to a flat 1D profile in a long-channel device; which implies that both the drift and diffusion components are required to be considered for an accurate drain current. The concept of the gradient in the quasi-Fermi level is a convenient way to do so. In this work, a pseudo 2D potential profile which takes into account the vertical field due to the gate and the lateral field due to the source and drain junctions in addition to the difference in the flat-band voltage along the channel is used. Moreover, the mobility and the effective conduction layer depth used are also position dependent since the channel doping varies along the channel. Model predictions are compared with the results predicted by the 2D numerical device simulator DESSIS, and a very good agreement between the two are observed.     

A new symmetrical double gate nanoscale MOSFET with asymmetrical side gates for electrically induced source/drain

In this paper, we present the unique features exhibited by a novel double gate MOSFET in which the front gate consists of two side gates as an extension of the source/drain. The asymmetrical side gates are used to induce extremely shallow source/drain regions on either side of the main gate. Using two-dimensional and two-carrier device simulation, we have investigated the improvement in device performance focusing on the threshold voltage roll-off, the drain induced barrier lowering, the subthreshold swing and the hot carrier effect. Based on our simulation results, we demonstrate that the proposed symmetrical double gate SOI MOSFET with asymmetrical side gates for the induced source/drain is far superior in terms of controlling the short-channel effects when compared to the conventional symmetrical double gate SOI MOSFET. We show that when the side gate length is equal to the main gate length, the device can be operated in an optimal condition in terms of threshold voltage roll-off and hot carrier effect. We further show that in the proposed structure the threshold voltage of the device is nearly independent of the side gate bias variation.     

Bias temperature instability from gate charge characteristics investigations in N-Channel Power MOSFET

This paper reports the effects of bias temperature stress (positive and negative bias temperature instabilites, PBTI–NBTI) on threshold voltage, input capacitance and Miller capacitance of N-Channel Power MOSFET. The device is stressed with gate voltage under precision temperature forcing system. The bias temperature cycling also induces instabilities N-Channel Power MOSFET. The gate charge characteristics have been investigated before and after stress. The capacitances (the drain–gate and drain–source capacitances) are shifted due to the degradation of device physical properties under different stress time and stress temperature conditions. Bi-dimensional simulations have been performed for the 2D Power MOSFET structure and accurately analyzed. Gate charge characteristics of the device have been correlated to physical properties to analyze mechanisms responsible of parameter degradations. It is shown that the main degradation issues in the Si Power MOSFET are the charge trapping and the trap creation at the interface of the gate dielectric performed by energetic free carriers, which have sufficient energy to cross the Si–SiO₂ barrier.     

Investigation of the novel attributes of a fully depleted dual-material gate SOI MOSFET

The novel features of a fully depleted (FD) dual-material gate (DMG) silicon-on-insulator (SOI) MOSFET are explored theoretically and compared with those of a compatible SOI MOSFET. The two-dimensional numerical simulation studies demonstrate the novel features as threshold voltage roll-up and simultaneous transconductance enhancement and suppression of short-channel effects offered by the FD DMG SOI MOSFET. Moreover, these unique features can be controlled by engineering the workfunction and length of the gate material. This work illustrates the benefits of high-performance FD DMG SOI MOS devices over their single material gate counterparts and provides an incentive for further experimental exploration.     

A DC model for asymmetric trapezoidal gate MOSFET's in stronginversion

Asymmetric trapezoidal gate (ATG) MOSFET is an innovative device having a structure of a relatively narrow drain-side width in order to reduce parasitic effects for enhancing device performance. In this paper, we develop a DC model for ATG MOSFET's. We use a charge-based approach to explore the asymmetric feature between source and drain of ATG MOSFET's, and obtain analytic formulae for threshold voltage, body effect, drain current, and channel length modulation effect in linear and saturation regions for both forward and reverse modes of operations. The model provides a physical analysis of the ATG structure, shows good agreement with measurement data, and is useful in circuit simulation with ATG devices     

Physics-based analytical modeling of potential and electrical field distribution in dual material gate (DMG)-MOSFET for improved hot electron effect and carrier transport efficiency

We propose a new two-dimensional (2-D) analytical model of a dual material gate MOSFET (DMG-MOSFET) for reduced drain-induced barrier lowering (DIBL) effect, merging two metal gates of different materials, laterally into one. The arrangement is such that the work function of the gate metal near the source is higher than the one near the drain. The model so developed predicts a step-function in the potential along the channel, which ensures screening of the drain potential variation by the gate near the drain. The small difference of voltage due to different gate material keeps a uniform electric field along the channel, which in turn improves the carrier transport efficiency. The ratio of two metal gate lengths can be optimized along with the metal work functions and oxide thickness for reducing the hot electron effect. The model is verified by comparison to the simulated results using a 2-D device simulator ATLAS over a wide range of device parameters and bias conditions.     

Full quantum simulation study of a nano tri-material double gate silicon-on-insulator MOSFET

We present 2D full quantum simulation based on the self-consistent solution of 2D Poisson–Schrödinger equations, within the nonequilibrium Green’s function formalism, for a novel multiple region silicon-on-insulator (SOI) MOSFET device architecture – tri-material double gate (TMDG) SOI MOSFET. This new structure has three materials with different work functions in the front gate, which show reduced short-channel effects such as the drain-induced barrier lowering and subthreshold swing, because of a step function of the potential in the channel region that ensures the screening of the drain potential variation by the gate near the drain. Also, the quantum simulations show the new structure significantly decreases leakage current and drain conductance and increases on–off current ratio and voltage gain as compared to conventional and dual material DG SOI MOSFET.     

Investigation of the novel attributes of a single-halo double gate SOI MOSFET: 2D simulation study

The novel features of an asymmetric double gate single halo (DG-SH) doped SOI MOSFET are explored theoretically and compared with a conventional asymmetric DG SOI MOSFET. The two-dimensional numerical simulation studies demonstrate that the application of single halo to the double gate structure results in threshold voltage roll-up, reduced DIBL, high drain output resistance, kink free output characteristics and increase in the breakdown voltage when compared with a conventional DG structure. For the first time, we show that the presence of single halo on the source side results in a step function in the surface potential, which screens the source side of the structure from the drain voltage variations. This work illustrates the benefits of high performance DG-SH SOI MOS devices over conventional DG MOSFET and provides an incentive for further experimental exploration.     

Simulation of hot-electron trapping and aging of nMOSFETs

An analysis of the degradation of 1-μm-gate-length nMOSFET operating under normal biasing conditions at room temperature is reported. A physical model of hot-electron trapping in SiO₂ is developed and is used with a two-dimensional device simulator (PISCES) to simulate the aging of the device under normal biasing conditions. The initial degradation takes place near the high-field drain region and spreads over a long time toward the source. The degraded I-V characteristics of the MOSFET exhibit a shift of the pinchoff voltage and a compression of the transconductance, for forward and reverse operation, respectively. The simulated degradation qualitatively agrees with reported experimental data. Large shifts of the MOSFET threshold voltage for small drain voltages result as the degradation is spreading toward the source. An inflection point arises for low gate and drain voltages in the drain I-V characteristics of the MOSFET. This inflection point originates when the pinchoff of the channel-induced trapped-electron charge is overcome by the drain voltage; the drain acts as a second gate (short-channel effect). The estimation of the device's lifetime by simulated aging is proposed     

Subthreshold surface potential and drain current models for short-channel pocket-implanted MOSFETs

An analytical subthreshold surface potential model for short-channel pocket-implanted (double-halo) MOSFET is presented. The effect of the depletion layers around the source and drain junctions on channel depletion layer depth, which is very important for short-channel devices, is included. Using this surface potential, a drift-diffusion based analytical subthreshold drain current model for short-channel pocket-implanted MOSFETs is also proposed. A physically-based empirical modification of the channel conduction layer thickness that was originally proposed for relatively long-channel conventional device is made for such short-channel double-halo devices. Very good agreement for both the surface potential and drain current is observed between the model calculation and the prediction made by the 2-D numerical device simulation using Dessis.     

Analytical modelling of threshold voltage for underlap Fully Depleted Silicon-On-Insulator MOSFET

In this article, surface-potential-based analytical threshold voltage model for underlap Fully Depleted Silicon-On-Insulator MOSFET (underlap-SOI) is developed by solving two-dimensional Poisson equation. The gate underlap at source/drain (S/D) has different boundary conditions as compared to channel region under the gate dielectric that divide the whole channel into three regions. It leads us to derive the new surface potential model for three different channel regions, i.e. the region under the gate dielectric and two gate underlap regions at S/D. The effects of underlap length, channel length, body thickness, channel doping concentration, metal gate work function and gate dielectric constant on threshold voltage have been included in our model. The threshold voltage dependence on different device parameters has been studied using analytical model and simulations. The closeness between the simulation results and model results show that the analytical model accurately calculate the threshold voltage values for large range of device parameters.     

Two-dimensional analytical threshold voltage model for DMG Epi-MOSFET

A two-dimensional (2-D) analytical model of a dual material gate (DMG) epitaxial (Epi)-MOSFET for improved, SCEs, hot electron effects, and carrier transport efficiency is presented. Using a two-region polynomial potential distribution and a universal boundary condition, we calculated the 2-D potential and electric field distribution along the channel. An expression for threshold voltage for short-channel DMG Epi-MOSFETs is also derived. The ratio of gate lengths has been varied to show which gate length ratio gives the best performance. The analytical results have been validated by the 2-D device simulator ATLAS over a wide range of device parameters and bias conditions.     

A threshold voltage model for short-channel MOSFETs taking into account the varying depth of channel depletion layers around the source and drain

In this paper, an analytical model for threshold voltage of short-channel MOSFETs is presented. For such devices, the depletion regions due to source/drain junctions occupy a large portion of the channel, and hence are very important for accurate modeling. The proposed threshold voltage model is based on a realistic physically-based model for the depletion layer depth along the channel that takes into account its variation due to the source and drain junctions. With this, the unrealistic assumption of a constant depletion layer depth has been removed, resulting in an accurate prediction of the threshold voltage. The proposed model can predict the drain induced barrier lowering (DIBL) effect and hence, the threshold voltage roll-off characteristics quite accurately. The model predictions are verified against the 2-D numerical device simulator, DESSIS of ISE TCAD.     

凹槽栅MOSFET凹槽拐角的作用与影响研究

短沟道效应是小尺寸ＭＯＳＦＥＴ中很重要的物理效应之一，凹槽栅ＭＯＳＦＥＴ对短沟道效应有很强的抑制能力，通过对凹槽栅ＭＯＳＦＥＴ结构，特性的研究，发现凹槽拐角对凹槽栅ＭＯＳＦＥＴ的阈值电压及特性有着显著的影响，凹槽拐角处的阈值电压决定着整个凹槽栅ＭＯＳＦＥＴ的阈值电压，凹槽拐角的曲率半径凹槽ＭＯＳＦＥＴ一个重要的结构参数，通过对凹槽拐角的曲率半径，源漏结深及沟道掺杂浓度进行优化设计，可使凹槽栅ＭＯＳ     

双掺杂多晶Si栅MOSFET的截止频率研究

在前期对双掺杂多晶Si栅(DDPG)LDMOSFET的电场、阈值电压、电容等特性所作分析的基础上,仍然采用双掺杂多晶Si栅结构,以低掺杂漏/源MOS(LDDMOS)为基础,重点研究了DDPG-LDDMOSFET的截止频率特性.通过MEDICI软件,模拟了栅长、栅氧化层厚度、源漏区结深、衬底掺杂浓度以及温度等关键参数对器件截止频率的影响,并与相同条件下P型单掺杂多晶Si栅(p-SDPG)MOSFET的频率特性进行了比较.仿真结果发现,在栅长90 nm、栅氧厚度2 nm,栅极P,n掺杂浓度均为5×1019cm-3条件下,截止频率由78.74 GHz提高到106.92 GHz,幅度高达35.8%.此结构很好地改善了MOSFET的频率性能,得出的结论对于结构的设计制作和性能优化具有一定的指导作用,在射频领域有很好的应用前景.     

Dual-material gate (DMG) field effect transistor

A generic new type of field effect transistor (FET), the dual material gate (DMG) FET, is proposed and demonstrated. The gate of the DMGFET consists of two laterally contacting materials with different work functions. This novel gate structure takes advantage of material work function difference in such a way that the threshold voltage near the source is more positive than that near the drain (for n-channel FET, the opposite for p-channel FET), resulting in a more rapid acceleration of charge carriers in the channel and a screening effect to suppress short-channel effects. Using the heterostructure FET as a vehicle, the principle, computer simulation results, design guidelines, processing, and characterization of the DMGFET are discussed in detail