一种新的套筒式全差分跨导放大器设计

A novel fully differential telescopic operational transconductance amplifier （OTA） is proposed. An additional PMOS differential pair is introduced to improve the unit-gain bandwidth of the telescopic amplifier. At the same time, the slew rate is enhanced by the auxiliary slew rate boost circuits. The proposed OTA is designed in a 0.18 μm CMOS process. Simulation results show that there is a 49% improvement in the unit-gain bandwidth compared to that of a conventional OTA; moreover, the DC gain and the slew rate are also enhanced.     

A novel fully differential telescopic operational transconductance amplifier

w rate are also enhanced.     

一种应用于WiMAX协议的全集成3.5GHzCMOS功率驱动放大器

A fully integrated CMOS differential power amplifier driver(PAD) is proposed for WiMAX applications. In order to fulfill the differential application requirements,a transmission line transformer is used as the output matching network.A differential inductance constitutes an inter-stage matching network.Meanwhile,an on chip balun realizes input matching as well as single-end to differential conversion.The PAD is fabricated in a 0.13μm RFCMOS process.The chip size is 1.1×1.1 mm~2 with all of the matching network integrated on chip. The saturated power is around 10 dBm and power gain is about 12 dB.     

一种新颖全差分光电集成接收机的标准CMOS实现

提出一种新颖的全差分光电集成接收机,它包含了全差分光电探测器和相应的差分接收电路,其中全差分光电探测器的作用是实现入射光信号到全差分光生电流信号的转换.采用特许3.3 V、0.35μm标准CMOS工艺,实现了一种相应的宽带、高灵敏度全差分光电集成接收机.测试结果表明:对于850 nm的入射光,集成全差分光电探测器的差分跨阻前置放大器(TIA)的工作速率可达到500 Mbit/s,而整个光接收机的带宽则达到了1.098 5 GHz;在10-12的误码率条件下,灵敏度可达到-12.3 dBm.     

一种集成MSM光电探测器的单片标准CMOS全差分光接收机

This paper presents a realization of a silicon-based standard CMOS,fully differential optoelectronic integrated receiver based on a metal–semiconductor–metal light detector（MSM photodetector）.In the optical receiver, two MSM photodetectors are integrated to convert the incident light signal into a pair of fully differential photogenerated currents.The optoelectronic integrated receiver was designed and implemented in a chartered 0.35μm, 3.3 V standard CMOS process.For 850 nm wavelength,it achieves a 1 GHz 3 dB bandwidth due to the MSM photodetector’s low capacitance and high intrinsic bandwidth.In addition,it has a transimpedance gain of 98.75 dBΩ, and an equivalent input integrated referred noise current of 283 nA from 1 Hz up to–3 dB frequency.     

A monolithic, standard CMOS, fully differential optical receiver with an integrated MSM photodetector

This paper presents a realization of a silicon-based standard CMOS, fully differential optoelectronic inte grated receiver based on a metal-semiconductor-metal light detector (MSM photodetector). In the optical receiver, two MSM photodetectors are integrated to convert the incident light signal into a pair of fully differential photo generated currents. The optoelectronic integrated receiver was designed and implemented in a chartered 0.35 μm, 3.3 V standard CMOS process. For 850 nm wavelength, it achieves a 1 GHz 3 dB bandwidth due to the MSM pho todetector's low capacitance and high intrinsic bandwidth. In addition, it has a transimpedance gain of 98.75 dBΩ, and an equivalent input integrated referred noise current of 283 nA from 1 Hz up to -3 dB frequency.     

A new high-performance CMOS fully differential second-generation current conveyor with application example of biquad filter realisation

In this article, a new complementary metal oxide semiconductor (CMOS) high-performance fully differential second-generation current conveyor (FDCCII) implementation is proposed. The presented FDCCII provides high-output impedance at terminals Z+ and Z?, good linearity and excellent output–input current gain accuracy. Also, the proposed FDCCII circuit operates at a supply voltage of ±1.3 V. The applications of the FDCCII to realise voltage-mode multifunction filters are given. Simulations are performed using TSMC CMOS 0.35-μm technology to verify theoretical results.     

应用于心电采集系统的低谐波失真全差分VGA测试验证

本文通过理论分析和流片测试验证了一个应用于心电采集系统的具有较低总谐波失真(THD)的全差分VGA。该VGA采用电容反馈技术来降低系统的非线性。本系统基于SMIC 0.18-μm CMOS工艺进行设计和流片,芯片面积仅为0.11 mm2。芯片测量结果同电路后仿真结果相吻合。测试结果表明VGA以3dB的增益步长由6.17dB到43.75dB变化,其高通角频率和低通角频率分别为0.22Hz和7.9kHz;各个增益级下获得最大的THD为-59.4dB。表明了该全差分VGA具有低的THD,其主要性能指标均满足心电采集系统在UWB健康监护与遥测系统中的应用要求。     

使用预失真技术的全集成线性CMOS功率放大器

本文使用了模拟预失真技术设计了用于2.5 GHz的m-WiMAX发射机系统的基于转换器的CMOS功率放大器,功率级和驱动级的三次谐波可以在特定功率范围内相互抵消。使用标准0.18μmCMOS工艺设计的两级功放在1 dB压缩点处的功率为27.5 dBm,功率增加效率为27%。在20.5 dBm的平均功率下可以满足功率谱的要求,EVM为5.5%。测试结果表明,与传统的使用三阶跨导零点偏置技术设计的功放相比,该功放具有良好的线性度和效率。     

A highly linear fully integrated CMOS power amplifier with an analog predistortion technique

A transformer-based CMOS power amplifier（PA） is linearized using an analog predistortion technique for a 2.5-GHz m-WiMAX transmitter.The third harmonic of the power stage and driver stage can be cancelled out in a specific power region.The two-stage PA fabricated in a standard 0.18μm CMOS process delivers 27.5 dBm with 27%PAE at the 1-dB compression point(P_1dB) and offers 21 dB gain.The PA achieves 5.5%EVM and meets the spectrum mask at 20.5 dBm average power.Another conventional PA with a zero-cross-point of g_m3 bias is also fabricated and compared to prove its good linearity and efficiency.     

一种低差分输出不匹配度的单转差分低噪声放大器

本文设计了一种应用于GPS接收机的单端输入差分输出低噪声放大器。我们提出了一种利用变压器或中心抽头差分电感中的电感耦合来降低差分输出不匹配度的方法。文中对降低不匹配度的原理进行了分析,并且讨论了如何选择电感尺寸。本文的LNA带ESD保护,使用TSMC 0.18um工艺实现,并且封装后在PCB上进行测试。LNA工作在1.575GHz,电压增益为24.6dB, 噪声系数为3.2dB,差分输出增益不匹配度小于0.2dB,相位不匹配度小于2度,LNA工作电压为1.8V,消耗5.2mA电流。     

A novel low-voltage low-power fully differential voltage and current gained CCII for floating impedance simulations

In this paper we present a new current-mode basic building block that we named voltage and current gained second generation current conveyor (VCG-CCII). The proposed active block allows to control and tune both the CCII current gain and the voltage gain through external control voltages. It has been designed, at transistor level in a standard CMOS technology (AMS 0.35 μm), with a low single supply voltage (2 V), as a fully differential active block. The proposed integrated solution, having both low-voltage (LV) and low-power (LP) characteristics, can be applied with success in suitable IC applications such as floating capacitance multipliers and floating inductance simulators, utilizing a minimum number of active components (one and two, respectively). Simulation results, related to floating impedance simulators, are in good agreement with the theoretical expectations.     

一种带增益提高技术的高增益CMOS运算放大器的设计

给出了一种用在高速高精度流水线型模数转换器中的具有高增益和高单位增益频率的全差动CMOS运算放大器的设计,电路结构主要采用折叠式共源共栅结构,并采用增益提高技术提高放大器的增益。共模反馈电路由开关电容共模反馈电路实现。模拟结果显示,其开环直流增益可达到106 dB,在负载电容为2 pF时单位增益频率达到了167 MHz,满足了对模数转换器的高速度和高精度的要求。     

A 65 nm CMOS fully-integrated dynamic reconfigurable differential power amplifier with high gain in both bands

A fully-integrated dual-band dynamic reconfigurable differential power amplifier with high gain in 65 nm CMOS is presented. A switchable shunt LC network is proposed to implement the dual-band reconfigurable operation and achieve high gain at both low and high frequency bands, and the high quality on-chip transformers are utilized to implement input/output impedance matching and single-ended to differential conversion. Measured results show that the dual-band dynamic reconfigurable power amplifier can provide 23 dB gain at 2.15 GHz and 21 dB gain at 4.70 GHz, and achieve more than 19 dBm saturated output power at 2.15 GHz and 13 dBm saturated output power at 4.70 GHz, respectively. The die area is about 1.7 mm×2.0 mm.     

基于前馈结构的宽带高线性低噪声放大器

设计制作了一款工作频率范围为0.5~30.0 MHz的短波宽带高线性低噪声放大器。采用前馈法线性化技术实现了放大器的高线性与低噪声,其中主放大器采用平衡式结构线性化技术大幅改善了放大器的二阶失真。由于主放大器和辅助放大器均采用Gain Block MMIC放大器,使得该放大器的物理尺寸为40 mm×25 mm,从而实现了小型化。测试结果表明,该放大器在0.5~30.0 MHz约5.9个倍频程的工作频率范围内实现了增益为12 dB,增益平坦度为0.35 dB,最大噪声系数为3.2 dB,输出三阶截点大于55 dBm,输出二阶截点大于100 dBm。     

一种中心频率和品质因子可调的全集成陷波器

介绍了一种新颖的全集成50/60Hz陷波器。该陷波器采用电流舵技术,克服了常规陷波器难以集成、线性失真大的缺点,并且中心频率和品质因子可分别通过偏置电压和编程调节。电路在SMIC 0.18μm CMOS工艺上设计并流片。测试结果表明中心频率调节范围为0.6 Hz~252Hz,品质因子可设为1、2、5或者10,总谐波失真仅有-76dB,远低于其他文献。最后,采用本陷波器对ECG信号进行了实时滤波,结果证明本电路可行。     

A fully integrated 23.2 dBm P1 dB CMOS power amplifier for the IEEE 802.11a with 29% PAE

A two-stage fully integrated power amplifier (PA) for the 802.11a standard is presented. The PA has been fabricated using UMC 0.18 μm CMOS technology. Measurement results show a power gain of 21.1 dB, a P_1 dB of 23.2 dBm and a P_SAT of 26.8 dBm. The PAE is 29% and it is kept high by means of several integrated inductors. These inductors present low-DC resistance and high Q characteristics. The inductors must include extra design considerations in order to withstand the high-current levels flowing through them, so that they have been called power inductors.     

多抽运宽带喇曼放大器模拟算法的研究

基于龙格-库塔-芬尔格(Runge-Kutta-Fehlberg)方法,提出了一种求解多抽运宽带喇曼放大器耦合方程的自适应步长算法。该算法根据每步计算中局部截断误差和精度的要求,合理调整步长大小。仿真结果表明,与其它算法相比,自适应步长算法能有效地提高计算精度和效率,适合于光纤喇曼放大器的模拟计算。