一种应用于图像传感器的全数字锁相环设计

针对图像传感器中传统锁相环(PLL)存在的功耗高、抖动大,以及锁定时长等问题,提出了一种基于计数器架构的低功耗、低噪声、低抖动、快速锁定的分数分频全数字锁相环(ADPLL)设计方法。首先,采用动态调节锁定控制算法来降低回路噪声,缩短锁定时间。其次,设计了一个通用单元来实现数字时间转换器(DTC)和时间数字转换器(TDC)的集成,以降低该部分由于增益不匹配引起的抖动。基于180nm CMOS工艺的仿真结果表明,在1.8V电源电压下,该ADPLL能够实现250MHz~2.8GHz范围的频率输出,锁定时间为1.028μs,当偏移载波频率为1MHz时,相位噪声为-102.249dBc/Hz,均方根抖动为1.7ps。     

基于65nm工艺的超高速全数字锁相环的设计和实现

论述了UMC 65nm CMOS工艺实现的全定制全数字锁相环.该锁相环用于提供高速嵌入武SRAM内建自测试所需的时钟.分析了全数字锁相环的工作原理和电路架构,并给出了整个锁相环系统的电路和版图实现.编码控制振荡器是全数字锁相环中的核心电路,提出了一种改进的编码控制振荡器,具有高线性度和高精度的特点.在理论上分析了全数字锁相环系统的稳定性,并给出所采用的锁相环架构的稳定性公式.该锁相环达最高输出频率为2GHz,抖动小于1%.     

Digital-only PLL with adaptive search step

In this paper, an all-digital phase-locked loop (PLL) with adaptively controlled up/down counter serves as the loop filter is presented, and it is implemented on a field-programmable gate array. The detailed circuit of the adaptive up/down counter implementing the adaptive search algorithm is also given, in which the search step for frequency acquisition is adaptively scaled down in half until it is reduced to zero. The phase jitter of the proposed PLL can be lowered, yet keeping with fast lock-in time. Thus, the dilemma between the low phase jitter and fast lock-in time of the traditional PLL can be resolved. Simulation results and circuit implementation show that the locked count, phase jitter and lock-in time of the proposed PLL are consistent with the theoretical predictions.     

一种应用于阵列TDC的低抖动锁相环设计

传统的PLL（Phase Locked Loop）电路受限于环路参数的选定,其相位噪声与抖动特性已经难以满足大阵列、高精度TDC（Time-to-Digital Converter）的应用需求.本文致力于PLL环路带宽的优化选取,采取TSMC 0.35μm CMOS工艺实现了一款应用于TDC的具有低抖动、低噪声特性的锁相环（Phase Locked Loop,PLL）电路,芯片面积约为0.745mm×0.368mm.实际测试结果表明,在外部信号源输入15.625MHz时钟信号的条件下,PLL输出频率可锁定在250.0007MHz,频率偏差为0.7kHz,输出时钟占空比为51.59%,相位噪声为114.66dBc/Hz@1MHz,均方根抖动为4.3ps,峰峰值抖动为32.2ps.锁相环的相位噪声显著降低,输出时钟的抖动特性明显优化,可满足高精度阵列TDC的应用需要.     

A low-jitter RF PLL frequency synthesizer with high-speed mixed-signal down-scaling circuits

A low-jitter RF phase locked loop (PLL) frequency synthesizer with high-speed mixed-signal down-scaling circuits is proposed.Several techniques are proposed to reduce the design complexity and improve the performance of the mixed-signal down-scaling circuit in the PLL.An improved D-latch is proposed to increase the speed and the driving capability of the DMP in the down-scaling circuit.Through integrating the D-latch with 'OR' logic for dual-modulus operation,the delays associated with both the 'OR' and D-flip-flop (DFF) operations are reduced,and the complexity of the circuit is also decreased.The programmable frequency divider of the down-scaling circuit is realized in a new method based on deep submicron CMOS technology standard cells and a more accurate wire-load model.The charge pump in the PLL is also realized with a novel architecture to improve the current matching characteristic so as to reduce the jitter of the system.The proposed RF PLL frequency synthesizer is realized with a TSMC 0.18-μm CMOS process.The measured phase noise of the PLL frequency synthesizer output at 100 kHz offset from the center frequency is only -101.52 dBc/Hz.The circuit exhibits a low RMS jitter of 3.3 ps.The power consumption of the PLL frequency synthesizer is also as low as 36 mW at a 1.8 V power supply.     

Design of high-frequency wide-range all digital phase locked loop in 90 nm CMOS

This paper presents a high-frequency wide tuning range all digital phase locked loop (ADPLL) designed using a 90 nm CMOS process with 1.2 V power supply. It operates in the frequency range of 1.9–7.8 GHz. The ADPLL uses a wide frequency range digital controlled oscillator (DCO) and a two stage acquisition process to obtain the fast lock time. The operation of the ADPLL includes both a frequency acquisition state and a phase acquisition state. A novel architecture is implemented which includes a coarse acquisition stage to obtain a monotonically increasing wide frequency range DCO for frequency acquisition and a fine control stage to achieve resolution of 18.75 kHz for phase tracking. Design considerations of the ADPLL circuit components and implementation using Cadence tools are presented. Spectre simulations demonstrate a peak-to-peak jitter value of <15 ps and a root mean square jitter value of 4 ps when locked at 5.12 GHz. The power consumption at 7.8 GHz is 8 mW and the frequency hopping time is 3.5 μs for a 3.2 GHz frequency change. Spectre simulations demonstrate ADPLL convergence to 5.12 GHz for the typical, fast, and slow process corners to support robust performance considering process variations.     

低抖动的480 MHz CMOS电荷泵式锁相环

本文设计了一款用于USB2.0时钟发生作用的低抖动、低功耗电荷泵式锁相环电路。其电路结构包含鉴频/鉴相器、电荷泵、环路滤波器、压控振荡器和分频器。电路设计是基于CSM0.18μmCMOS工艺,经HSPICE仿真表明,锁相环输出480MHz时钟的峰峰值抖动仅为5.01ps,功耗仅为8.3mW。     

Fast acquisition clock and data recovery circuit with low jitter

This paper presents a half-rate clock and data recovery circuit (CDR)that combines the fast acquisition of a phase selection (PS) delay-locked loop (DLL) with the low jitter of a phase-locked loop (PLL). The PLL acquisition time improves considerably with use of a phase frequency magnitude detector(PFMD) that feeds back an estimate of the magnitude of the frequency difference in addition to the sign. Measurements in 0.5/spl mu/m CMOS technology show operation up to 700 Mb/s, a 7% acquisition range, an initial acquisition time of 8 bit times with jitter of 30% bit time, and jitter of 16 ps after the PLL acquires lock. With a phase frequency detector (PFD), the PLL locks in about 700 ns from an initial frequency difference of 7%. Measurements using a PFMD show the 700 ns PLL acquisition time is reduced on average by about a factor of 5 to 140 ns from an initial 7% frequency difference. The power dissipation is 300mW.     

A 10 GHz Phase-Locked Loop With a Compact Low-Pass Filter in 0.18 $mu$ m CMOS

In this letter, a multi-gigahertz phase-locked loop (PLL) with a compact low-pass filter is presented. By using a novel dual-path control in the PLL architecture, the capacitance in the loop filter can be effectively reduced for high-level integration while maintaining the required loop bandwidth. Consequently, the noise resulted from off-chip components is therefore eliminated, leading to lower timing jitter at the PLL output waveforms. In addition, the timing jitter is further suppressed due to the use of decomposed phase and frequency detection. Based on the proposed techniques, a 10 GHz PLL is implemented in 0.18 mum CMOS for demonstration. Consuming a dc power of 113 mW from a 1.8 V supply, the fabricated circuit exhibits a locking range from 10.1 to 11 GHz. At an output frequency of 10.3 GHz, the measured peak-to-peak and rms jitter are 3.78 and 0.44 ps, respectively.     

一种基于电荷泵锁相环的时钟调节电路设计

设计了一种基于电荷泵锁相环(PLL)的独特时钟调节电路,可调节时钟频率和延时,可纠正时钟偏斜,能够输出不同相位(0°,90°,180°,270°)锁定且低抖动的各种频率信号,锁相环可外部动态配置。该电路可应用于FPGA系统集成电路的时钟发生源电路中,能够提供非常灵活的时钟调节功能。仿真结果表明,该电路满足设计需求。     

A low-jitter 125-1250-MHz process-independent and ripple-poleless0.18-μm CMOS PLL based on a sample-reset loop filter

This paper describes a low-jitter phase-locked loop (PLL) implemented in a 0.18-μm CMOS process. A sample-reset loop filter architecture is used that averages the oscillator proportional control current which provides the feedforward zero over an entire update period and hence leads to a ripple-free control signal. The ripple-free control current eliminates the need for an additional filtering pole, leading to a nearly 90° phase margin which minimizes input jitter peaking and transient locking overshoot. The PLL damping factor is made insensitive to process variations by making it dependent only upon a bandgap voltage and ratios of circuit elements. This ensures tracking between the natural frequency and the stabilizing zero. The PLL has a frequency range of 125-1250 MHz, frequency resolution better than 500 kHz, and rms jitter less than 0.9% of the oscillator period     

一个简单鉴频鉴相器结构实现的快速锁定低抖动锁相环

用简单的鉴频鉴相器结构实现了一个快锁定低抖动的锁相环.鉴频鉴相器仅仅由两个异或门组成,它可以同时获得低抖动和快锁定的性能.锁相环中的电压控制振荡器由四级环形振荡器来实现,每级单元电路工作在相同的频率,并提供45°的相移.芯片用0.18μm CMOS工艺来实现.PLL输出的中心频率为5GHz,在偏离中心频率500kHz处,测量的相位噪声为-102.6dBc/Hz.锁相环的捕获范围为280MHz,RMS抖动为2.06ps.电源电压为1.8V时,功耗仅为21.6mW(不包括输出缓冲).     

一种用于E1接口的全数字锁相环

提出了一种从E1信号中提取时钟的全数字锁相环。该锁相环结构简单、易于实现、可靠性高,提取的时钟信号的抖动和漂移均满足ITU-T G.823的要求。建立了相位传递数学模型,对电路的原理进行了分析。对该锁相环进行了实验验证,结果表明,在满足ITU-T相关建议的情况下,该电路完全可以从E1信号中提取时钟。     

Loop-parameter optimization of a PLL for a low-jitter 2.5-Gb/sone-chip optical receiver IC with 1: 8 DEMUX

A loop parameter optimization method for a phase-locked loop (PLL) used in wide area networks (WANs) is proposed as a technique for achieving good jitter characteristics. It is shown that the jitter characteristics of the PLL, especially jitter transfer and jitter generation, depend strongly on the key parameter ζω_n (ζ is a damping factor and ω_n is the natural angular frequency of the PLL), and that the optimization focusing on the ω_n dependence of the jitter characteristics make it possible to comprehensively determine loop parameters and loop filter constants for a PLL that will fully comply with ITU-T jitter specifications. Using the optimization method with the low-jitter circuit design technique, a low-jitter and low-power 2.5-Gb/s optical receiver IC integrated with a limiting amplifier, clock and data recovery (CDR), and demultiplexer (DEMUX) is fabricated using 0.5-μm Si bipolar technology (f_T = 40 GHz). The jitter characteristics of the IC meet all three types of jitter specifications given in ITU-T recommendation G.783. In particular, the measured jitter generation is 3.2 ps rms, which is lower than that of an IC integrated with only a CDR in our previous work. In addition, the pull-in range of the PLL is 50 MHz and the power consumption of the IC is only 0.68 W (limiting amplifier: 0.2 W, CDR (PLL): 0.3 W, DEMUX: 0.18 W) at a supply voltage of -3.3 V and only 0.35 W at a supply voltage of -2.5 V (without output buffers)     

Short locking time and low jitter phase-locked loop based on slope charge pump control

A novel structure of a phase-locked loop(PLL) characterized by a short locking time and low jitter is presented,which is realized by generating a linear slope charge pump current dependent on monitoring the output of the phase frequency detector(PFD) to implement adaptive bandwidth control.This improved PLL is created by utilizing a fast start-up circuit and a slope current control on a conventional charge pump PLL.First,the fast start-up circuit is enabled to achieve fast pre-charging to the loop filter...     

A 1-GHz Charge Pump PLL Frequency Synthesizer for IEEE 1394b PHY

The design procedure of an 1-GHz phase-locked loop (PLL)-based frequency synthesizer used in IEEE 1394b physical (PHY) system is presented in this paper. The PLL’s loop dynamics are analyzed in depth and theoretical relationships between all loop parameters are clearly described. All the parameters are derived and verified by Verilog-A model, which ensures the accuracy and efficiency of the circuit design and simulation. A 4-stage ring oscillator is employed to generate 1-GHz oscillation frequency and is divided into low frequency clocks by a feedback divider. The architecture is a third-order, type-2 charge pump PLL. The simulated settling time is less than 4μs. The RMS value of period jitter of the PLL’s output is 2.1 ps. The PLL core occupies an area of 0.12 mm2, one fourth of which is occupied by the MiM loop capacitors. The total current consumption of the chip is 16.5 mA. The chip has been sent for fabrication in 0.13 m complementary metal oxide semiconductor (CMOS) technology.     

A simple precharged CMOS phase frequency detector

We propose a simple precharged CMOS phase frequency detector (PFD). The circuit uses 18 transistors and has a simple topology. Therefore, the detector, in a 0.8-μm CMOS process, works up to clock frequencies of 800 MHz according to SPICE simulations on extracted layout. Further, the detector has no dead-zone in the phase characteristic which is important in low jitter applications. The phase and frequency characteristics are presented and comparisons are made to other PFDs. The phase offset of the detector is sensitive to differences of the duty-cycle between the inputs. Mixed-mode simulations are presented of the lock-in procedure for a phase-locked loop (PLL) where the detector is used. Measurements on the detector are presented for a test-chip with a delay-locked loop (DLL) where the phase detection ability of the detector has been verified