低电压高效率非晶硅发射极异质结UHF功率晶体管

本文报道了利用重掺杂氢化非晶硅作宽禁带发射极材料的低电压硅异质结UHF功率晶体管的实验结果.制备的器件在9伏电压、工作频率470MHz下,输出连续波功率4W,功率增益8.2dB,集电极效率72％.在迄今有关非晶硅发射极HBT的报道中。这是首次详细报道可工作于UHF频率的低电压非晶硅发射极异质结功率晶体管.文中还讨论了这种异质结构的低压功率器件的设计和制备应考虑的一些问题,并提出一些解决办法.     

基于65 nm CMOS工艺的2阶温度补偿全CMOS电压基准源

采用65 nm CMOS工艺,设计了一种基于MOS亚阈区特性的全CMOS结构电压基准源.首先利用工作在亚阈值区NMOS管的栅源电压间的差值得到具有特定2阶温度特性的CTAT电压,该CTAT电压的2阶温度特性与PTAT电压2阶温度特性的弯曲方向相反.再通过电流镜技术实现CTAT电压和PTAT电压求和,最终得到具有2阶温度...     

High voltage gain CMOS OTA for micropower SC filters

The letter describes a single stage operational transconductance amplifier (OTA) with cascoded output transistors, designed for micropower switched-capacitor filters. The device features high voltage gain (>90 dB) under capacitive load, large output swing, very low power consumption (5 ?W at 3 V supply voltage for 100 kHz bandwidth with 10 pF load) and reduced circuit area (<0.1 mm2).     

Base diffusion isolated transistors for low power integrated circuits

Base diffusion isolated transistors (BDI) designed for low power, nonsaturating, integrated circuits have been fabricated. Buried collectors are unnecessary in these low power devices, resulting in structures equivalent to discrete transistors in complexity of fabrication. A low-current power supply is required for isolation purposes. Transistor characteristics differ negligibly from those of standard transistors at collector currents <0.05 mA, and are satisfactory for application in linear circuits at currents up to at least 0.1 mA. Transistor fTis 80 MHz at 0.1 mA emitter current, 2 V collector voltage.     

1800 V NPN bipolar junction transistors in 4H-SiC

The first high voltage npn bipolar junction transistors (BJTs) in 4H-SiC have been demonstrated. The BJTs were able to block 1800 V in common emitter mode and showed a peak current gain of 20 and an on-resistance of 10.8 mΩ·cm² at room temperature (I_C=2.7 A @ V_CE=2 V for a 1 mm×1.4 mm active area), which outperforms all SiC power switching devices reported to date. Temperature-stable current gain was observed for these devices. This is due to the higher percent ionization of the deep level acceptor atoms in the base region at elevated temperatures, which offsets the effects of increased minority carrier lifetime at high temperatures. These transistors show a positive temperature coefficient in the on-resistance characteristics, which will enable easy paralleling of the devices     

High-efficiency dual transistor base drive circuit based on the Cukconverter topology

A dual transistor base drive circuit that unifies all important functions (on-state base current power supply for two power transistors, off-state negative U_be =-5 V base-emitter voltage, overcurrent and short-circuit protection scheme based on saturation voltage, and on- and off-state monitoring circuits) is described. The unit provides two base drive outputs using a single switching converter. It can be used to control two individual power transistors in different inverter configurations, e.g. common emitter or bridge configuration. The concept of a dual transistor base drive circuit using the Cuk switching regulator topology enables the low volume construction of a high-efficiency base drive unit for a high-power transistor inverter bridge leg. The circuit is powered from a common DC rail. The base current waveforms are characterized by steep slopes and an overcurrent peak at turn on     

Increasing the current density of dielectric-base transistors withan MgO emitter-base barrier

We measured the current-voltage characteristics of YBa₂Cu₃O_7-x/oxide/n-SrTiO₃ diodes using NdGaO₃, LaAlO₃, CeO₂, and MgO as the oxide. MgO films had the highest current density. We then fabricated dielectric-base transistors with a YBa₂Cu₃ O_7-x(YBCO) emitter/collector on a SrTiO₃ dielectric base with an MgO barrier. The transistors had both voltage and current gains exceeding unity at 4.2 K. The emitter current density was about 4×10³ A/cm² at a collector-emitter voltage of 10 V and base-emitter voltage 10 V; this is 2 to 3 orders of magnitude larger than that of transistors with NdGaO₃ emitter-base barrier. We obtained a transconductance of around 0.4 mS at a collector-emitter voltage of 10 V for a device with a 6-μm-diameter emitter     

High-Gain 15-W Monolithic Power Amplifier with Internal Fault Protection

A combination of circuit and device innovations has resulted in the development of a 15-W integrated-circuit power amplifier that incorporates a preamplifier on the same chip to give an overall closed-loop gain of 60 dB. Two novel devices used are a new high-frequency drift-lateral p-n-p to improve stability and a new 3-A n-p-n power transistor design with individual emitter ballasting to achieve a larger safe-operating area. Other interesting features are an externally adjustable short-circuit current limit, a built-in thermal shutdown circuit that automatically limits the junction temperature to 175/spl deg/C, an electronic shutdown control to mute the amplifier; a supply voltage range of 10-40 V, excellent power-supply rejection (55 dB), and a unique biasing technique that ensures that the output quiescent point remains at one-half the supply voltage with the total bias current changing only 3 mA over the complete supply voltage range (10-40 V).     

Reproducibility of thermionic performance

The performance of 12 identical thermionic converters fabricated to a given set of specifications, is reported. The converters were of planar geometry. The emitters were solid rhenium, and the collectors were arc-cast molybdenum. The average output power of the converters at an emitter temperature of 2000°K and an output voltage of 0.7 volt was 37.5 watts (18.75 W/cm²) with a standard deviation of 1.3 watts (0.65 W/cm²). Voltage-current characteristics of the converters at an emitter temperature of 1975°K are also presented.     

Design of Class-EM Power Amplifier at any DC voltage source considering nonlinear capacitances

In this paper, the effects of the DC input voltage source on the class-E_M power amplifier design and specifications at 4 MHz operating frequency are investigated. The most important parameters of the class-E_M power amplifier are the output power, output power capability, maximum voltage and current of the MOSFETs and power conversion efficiency which are all dependent on the input DC power supply. In this paper, IRFZ24N and IRF510 transistors have been used for the presented designs. The measured efficiency and output power at DC source voltage of the main circuit equal to 12 V for the proposed class-E_M power amplifier with IRFZ24N are 96.2% and 21.78 W, respectively. The measured results for IRFZ24N are consistent with simulation and analysis results.     

应用于TD-LTE的SiGe BiCMOS功率 放大器的设计

针对准第四代无线通信技术TD-LTE中2.570~2.620 GHz频段的应用,设计了一款基于IBM SiGe BiCMOS7WL工艺的射频功率放大器。该功率放大器工作于AB类,采用单端结构,由两级共发射极电路级联构成,带有基极镇流电阻,除两个谐振电感采用片外元件外,其他全部元件均片上集成,芯片面积为(1.004×0.736)mm2。测试结果表明,在3.3 V电源电压下,电路总消耗电流为109 mA,放大器的功率增益为16 dB,输出1 dB增益压缩点为15 dBm。该驱动放大器具有良好的输入匹配,工作稳定。     

一种阵列式版图布局的低温度系数CMOS带隙基准电压源

设计了一款低温度系数的自偏置CMOS带隙基准电压源电路,分析了输出基准电压与关键器件的温度依存关系,实现了低温度系数的电压输出。后端物理设计采用多指栅晶体管阵列结构进行对称式版图布局,以压缩版图面积。基于65 nm/3.3 V CMOS RF器件模型,在Cadence IC设计平台进行原理图和电路版图设计,并对输出参考电压的精度、温度系数、电源抑制比(PSRR)和功耗特性进行了仿真分析和对比。结果表明,在3.3 V电源和27℃室温条件下,输出基准电压的平均值为765.7 mV,功耗为0.75μW;在温度为-55~125℃时,温度系数为6.85×10~(-6)/℃。此外,输出基准电压受电源纹波的影响较小,1 kHz时的PSRR为-65.3 dB。     

L波段150W宽带硅脉冲功率晶体管

设计了一种称之为多晶硅覆盖树技状结构的双极型微波功率晶体管。该器件采用掺砷多晶硅发射极，同时具备有覆盖和树枝状两种图形结构的优点。器件引入扩散电阻和分布式多晶硅电阻组合而成的发射极复合镇流电阻，实现对发射极电流二次镇流，器件表现出良好的微波性能和高的可靠性。经内匹配，在L波段脉冲输出大于100W（36V），脉宽150μs，工作比10％，增益大于7．5dB，效率大于45％，器件最大输出达150W（42V）。     

Emitter-ballasting-resistor-free SiGe microwave powerheterojunction bipolar transistor

The emitter ballasting resistor is used to equalize the current distribution between the emitter stripes in power transistor, but it will degrade the output power, power gain, and power added efficiency. Experimental results indicate that the current gain of uniform-base SiGe heterojunction bipolar transistors (HBTs) decreases with the increase of the temperature above 160 K, so the current distribution is equalized by itself to some extent. Therefore, the microwave power SiGe HBTs without emitter ballasting resistor were fabricated for the first time, and the continuous output power of 5 W and power added efficiency of 63% were obtained under Class C operation at a frequency of 900 MHz. Hence, the emitter current density of the SiGe HBT's with emitter width of 6 μm is 0.79 A/cm     

Thermal properties of high-power transistors

The temperature of a transistor can be determined from the emitter-base voltage versus collector-current characteristic. This characteristic was used for studying the stability of parallel pairs of high-frequency high-power transistors. The thermal effect may cause the incremental emitter-base resistance to assume a negative value. This, in turn, will cause the current flow in a pair of transistors to be asymmetrical. The transition from symmetrical to asymmetrical current flow occurs at a power level which is determined by the nonshared thermal and electrical resistances. Stability to a higher current level can be obtained by increasing the nonshared emitter or base resistances or reducing the collector voltage. Higher currents can also be obtained by reducing the nonshared thermal resistances which indicates close thermal coupling between the two units is desirable.     

1 W Ku-band AlGaAs/GaAs power HBT's with 72% peak power-addedefficiency

High power and high-efficiency multi-finger heterojunction bipolar transistors (HBT's) have been successfully realized at Ku-band by using an optimum emitter ballasting resistor and a plated heat sink (PHS) structure. Output power of 1 W with power-added efficiency (PAE) of 72% at 12 GHz has been achieved from a 10-finger HBT with the total emitter size of 300 μm². 72% PAE with the output power density of 5.0 W/mm is the best performance ever reported for solid-state power devices with output powers more than 1 W at Ku-band     

High‐Gain Double‐Bulk Mixer in 65 nm CMOS with 830 pW Power Consumption

A low‐power down‐sampling mixer in a low‐power digital 65 nm CMOS technology is presented. The mixer consumes only 830 µW at 1.2 V supply voltage by combining an NMOS and a PMOS mixer with cascade transistors at the output. The measured gain is (19 °1 dB) at frequencies between 100 MHz and 3 GHz. An IIP3 of ?5.9 dBm is achieved.     

A 1.5-V high drive capability CMOS op-amp

A novel CMOS operational amplifier with a 1.5 V power supply is presented. It is based on a folded-mirror transconductance amplifier and a high-efficiency output stage. The amplifier achieves an open-loop gain and a gain-bandwidth product higher than 65 dB and 1 MHz, respectively. In addition, a 1 V peak-to-peak output voltage into a 500 Ω and 50 pF output load is provided with a total harmonic distortion of -77 dB. This performance was achieved using maximum aspect ratios of 120/1.2 and 360/1.2 for the NMOS and PMOS transistors, respectively, and a quiescent current as low as 60 μA for the driver transistors. The amplifier was implemented in a standard 1.2 μm CMOS process with threshold voltages around 0.8 V. It dissipates less than 300 μW     

A Comparator With Reduced Delay Time in 65-nm CMOS for Supply Voltages Down to 0.65 V

A comparator in a low-power 65-nm complementary metal–oxide–semiconductor process (only standard transistors with threshold voltage $V_{t} approx 0.4 hbox{V}$ were used) is presented, where the circuit of a conventional latch-type comparator consisting of two cross-coupled inverters is modified for fast operation, even with 0.6 GHz at a low supply voltage of 0.65 V. The advantages of a high-impedance input, rail-to-rail output swing, robustness against the influence of mismatch, and no static power consumption are kept. To achieve a bit error rate of $10^{-9}$ at 1.2-V supply, an amplitude at the input of 16.5 mV at 4 GHz has to be applied. If the supply voltage is lowered, 12.1 mV at 0.6 GHz/0.65 V is necessary. The power consumption of the comparator is 2.88 mW at 5 GHz (1.2 V) and 128 $muhbox{W}$ at 0.6 GHz (0.65 V). Simulations show an offset standard deviation of about 6.1 mV at 0.65-V supply. With an on-chip measurement circuit, the delay time of the comparator of, e.g., 104 ps for 15-mV input amplitude at 1.2-V supply, is obtained.      

Bulk-driven class AB fully-balanced differential difference amplifier

This paper presents a new low-voltage class AB fully-balanced differential difference amplifier (FB-DDA) employing the bulk-driven technique. At the FB-DDA differential pairs the bulk terminal of the MOS transistors are used as signal inputs in order to increase the common-mode input range under low supply voltage. At the class AB output stages the bulk terminal of the MOS transistors are used as control inputs in order to adjust the quiescent currents and compensate them against the process and temperatures (P/T) variation. The voltage supply of the FB-DDA is 0.7 V and the quiescent power consumption is 8.3 µW. The open loop voltage gain is 68 dB and the gain–bandwidth product is 168 kHz for 10 pF capacitive load. The circuit performance was simulated in Cadence/Spectre environment using the TSMC 0.18 µm CMOS process.