Frequency tunable low ripple and fast response on-chip DC–DC converter for DVFS

Dynamic voltage and frequency scaling (DVFS) is an efficient method to reduce the power consumption in system on-chip. To support DVFS, multiple supply voltages are generated based on different work load frequencies and currents using on-chip DC–DC voltage converter. In this paper a frequency tunable multiple output voltage switched capacitor based dc–dc converter is presented. An analog to digital converter and phase controller is used in the feedback to change the switching frequency and duty cycle of the converter. An input voltage of 1.8 V is converted to 0.6 and 0.8 V for low and high signal frequency respectively. The proposed 2-phase switched capacitor architecture with gain setting of 1:2 is designed with the 90 nm technology. An output ripple of 45 mV is observed and the maximum transient response time of the converter is 17.3 ns (= 58 MHz).     

A transient enhanced DVS DC–DC converter based on state trajectory analysis

Dynamic voltage scaling (DVS) can effectively reduce energy consumption by dynamically varying the supply voltage of the system accordingly to the clock frequency. A new DVS-enabled DC–DC converter is presented in this paper. State trajectory is employed to analyze the transient features of PWM and PFM Buck converters. A novel transient enhancement circuit is designed to improve the transient response of the DVS-enabled Buck converter. To further expand the output voltage range of the converter, a current-starved voltage controlled delay line is proposed in the controller of DC–DC converter to obtain an ultra low voltage of 0.5 V. When the input voltage is 3.3 V, the output voltage of the converter can be dynamically regulated from 0.5 to 2.0 V. The output voltage tracking speed is less than 7.5 μs/V and the recovery speed is 33 μs/A for a load current step from 0.6 to 0.2 A at output voltage of 0.5 V. The chip area is 1.75 mm × 1.33 mm in a 0.18 μm standard CMOS process.     

A wide supply voltage range and low-power all-digital clock generator

This study presents a low-power all-digital clock generator (ADCG) for a wide supply voltage range system. The proposed ADCG limits the maximum supply current to 100 μA at a supply voltage ranging from 1.6 to 3.6 V. The ADCG also uses a digitally controlled oscillator (DCO) to extend its operational frequency range. The proposed DCO controls the supply current and divider circuits for a wide supply voltage range. The output duty cycle of ADCG falls within 50 ± 1.9 % using a duty cycle corrector. The maximum peak-to-peak jitter is less than 2.7 % at 8.38 MHz for a digital water meter application (DWM). The operational frequencies of 1.45 and 8.38 MHz at 1.8 V are 3.1 and 36.7 μA, respectively. The core area of ADCG is 0.14 mm² for a 0.35 μm CMOS process. The operational frequency of ADCG ranges from 4.5 to 9.2 MHz at a supply voltage ranging from 1.6 to 3.6 V. This clock generator can also be applied to microcontroller applications.     

Freewheel charge-pump controlled single-inductor multiple-output step-up DC–DC converter

This paper presents a freewheel-charge-pump-controlled design for a single-inductor multiple-output (SIMO) DC–DC Converter. By applying the freewheel-charge-pump-controlled (FCPC) technique, the freewheel switching time is reused, and two extra charge-pump outputs are provided by time recycling, with no cost in time sequences. The converter has two step-up outputs and two charge-pump outputs that can be higher or lower than the input supply. The converter utilizes a 1 μH inductor, 4.7 μF charge-pump capacitors and 33 μF output capacitors at a frequency of 1 MHz. The proposed converter shows low cross-regulation and achieves a maximum loading current of 70 mA. Fabricated in a 0.18-μm CMOS process, the proposed circuit occupies 1.3 × 1.3 mm². Experimental results demonstrate that the converter successfully generates four well-regulated outputs with a single inductor. The supply voltage ranged from 1.6 to 2.5 V and the load regulation performance was 0.08, 0.05, 1.7, and 1.9 mV/mA for V_O1, V_O2, V_O3 and V_O4, respectively.     

Enhanced active feedback technique with dynamic compensation for low-dropout voltage regulator

This paper presents a novel frequency compensation technique for a low-dropout (LDO) voltage regulator. Enhanced active feedback frequency compensation is employed to improve the frequency response. The proposed LDO is capable of providing high stability for current loads up to 150 mA with or without loading capacitors. The proposed LDO voltage regulator provides a loop bandwidth of 7.8 MHz under light loads and 6.5 MHz under heavy loads. The maximum undershoot and overshoot are 59 and 90 mV, respectively, for changes in load current within a 200-ns edge time, while the compensation capacitors only require a total value of 7 pF. This enables easy integration of the compensation capacitors within the LDO chip. The proposed LDO regulator was designed using TSMC 0.35-μm CMOS technology. With an active area of 0.14 mm² (including feedback resistors), the quiescent current is only 40 μA. The input voltage ranges from 1.73 to 5 V for a loading current of 150 mA and an output voltage of 1.5 V. The main advantage of this approach is the stability of the LDO circuit when external load capacitors are connected, or even without load capacitors.     

A 0.5-bit step multi-resolution adjustable-input range reconfigurable noise-shaping TDC using multi-step quantizer gated-ring oscillators

A reconfigurable noise-shaping time-to-digital converter (TDC) with adjustable resolution and input range is presented as a solution to nonlinear multi-input readout systems. By varying the frequency of a multi-step quantizer gated-ring oscillator (MSQ-GRO), the resolution and input range are adjusted without affecting the acquisition time. A prototype of a standalone second-order MASH MSQ-GRO-TDC operating over a 34 μs adjustable input range and covering five resolution modes is presented. The MSQ-GRO frequency changes by a factor of approximately \(\sqrt 2\), thus adjusting the resolution in steps of 0.5-bit. With a 12 MHz sampling frequency, the MSQ-GRO-TDC consumes 0.85 mW from a 1.2 V supply and achieves integrated noise of 42.8 and 1.9 ps_rms in 500 and 1 kHz bandwidths, respectively. The measured resolution is 13.3-to-15.3 bits with a sampling signal of 200 kHz in a 5 kHz bandwidth. The input range/resolution optimization allows up to 51% of power saving under the same supply voltage, thus extending the battery lifetime in portable devices. The MSQ-GRO-TDC is used as a data converter for a nonlinear pressure sensor. It achieves a worst-case resolution of 24.5 μbar_rms. It is realized in a standard 0.13 μm CMOS technology and occupies an area of 0.145 mm².     

A CMOS micro power switched-capacitor DC–DC step-up converter for indoor light energy harvesting applications

This paper presents a micro power light energy harvesting system for indoor environments. Light energy is collected by amorphous silicon photovoltaic (a-Si:H PV) cells, processed by a switched capacitor (SC) voltage doubler circuit with maximum power point tracking (MPPT), and finally stored in a large capacitor. The MPPT fractional open circuit voltage (V_OC) technique is implemented by an asynchronous state machine (ASM) that creates and dynamically adjusts the clock frequency of the step-up SC circuit, matching the input impedance of the SC circuit to the maximum power point condition of the PV cells. The ASM has a separate local power supply to make it robust against load variations. In order to reduce the area occupied by the SC circuit, while maintaining an acceptable efficiency value, the SC circuit uses MOSFET capacitors with a charge sharing scheme for the bottom plate parasitic capacitors. The circuit occupies an area of 0.31 mm² in a 130 nm CMOS technology. The system was designed in order to work under realistic indoor light intensities. Experimental results show that the proposed system, using PV cells with an area of 14 cm², is capable of starting-up from a 0 V condition, with an irradiance of only 0.32 W/m². After starting-up, the system requires an irradiance of only 0.18 W/m² (18 μW/cm²) to remain operating. The ASM circuit can operate correctly using a local power supply voltage of 453 mV, dissipating only 0.085 μW. These values are, to the best of the authors’ knowledge, the lowest reported in the literature. The maximum efficiency of the SC converter is 70.3 % for an input power of 48 μW, which is comparable with reported values from circuits operating at similar power levels.     

A voltage mode buck DC–DC converter with automatic PWM/PSM mode switching by detecting the transient inductor current

This paper presents a voltage mode buck DC–DC converter that integrates pulse-width modulation (PWM) and pulse-skipping modulation (PSM) to achieve high efficiency under heavy and light load conditions, respectively. Automatic mode-switching is implemented simply by detecting the voltage drop of high-side power switch when it is on, which indicates the transient current flowing through the inductor. Unlike other methods based on average current sensing, the proposed auto-mode switching scheme is implemented based on voltage comparison and simple control logic circuit. In order to avoid unstable mode switching near the load condition boundary, the mode switching threshold voltage is set differently in PWM and PSM mode. Besides, a 16-cycle counter is also used to ensure correct detection of the change in the load condition and fast response of the converter. In addition, a dual-path error amplifier with clamp circuit is also adopted to realize loop compensation and ensure 100 % duty cycle operation. Fabricated in a 0.18-μm standard CMOS technology, the DC–DC converter is able to operate under supply voltage from 2.8 to 5.5 V with 3-MHz clock frequency. Measurement results show that the converter achieves a peak efficiency of 93 %, and an output voltage ripple of less than 40 mV, while the chip area is 1.02 mm².     

A CMOS MF energy harvesting and data demodulator receiver for wide area low duty cycle applications with 250 mV start-up voltage

A low voltage start-up energy harvesting medium frequency receiver is presented, for use as the power and synchronisation part of a remote sensor node in a wide area industrial or agricultural application. The use of embedded low bandwidth network synchronisation data permits very low operational duty cycle without the need for real time clocks or wake up receivers at each node with their associated continuous power drain. The receiver consists of a rectifier, a power management unit and a phase-shift keying demodulator. The rectifier is optimised for low start-up and operating voltage rather than power efficiency. With standard MOS thresholds the rectifier can cold start with only 250 mV peak antenna input, and useful battery charging is delivered with 330 mV peak input. The QPSK demodulator consumes 1.27 μW with a supply voltage of 630 mV at a data rate of 1.6 kbps with 1 MHz carrier frequency. The IC is implemented in a standard threshold 0.18 μm CMOS technology, occupies 0.54 mm² and can deliver 10.3 μW at 3 V to an external battery or capacitor.     

Integrated control circuit for adaptive sampling

A fully integrated controller for non-uniform data sampling suitable for the pre-processing of signals in a power- and size-restricted sensor front-end is presented. The sample rate is dynamically varied based on signal activity determined by the 2nd derivative of the input voltage. The derivative is realized with high-pass filters having 647 Hz cut-off frequency. A digital circuit generates the time-stamps and the trigger for an external analog-to-digital converter. Measured results of a 0.35 μm CMOS implementation show a sample rate variation of 7:1 and a system power advantage compared to conventional front-ends. The circuit dissipates 48 μW from ±1.5 V supplies and consumes an active area of 0.068 mm².     

Novel low-voltage folder for analogue-to-digital converter

A novel architecture of low-voltage folder is presented for folding analogue-to-digital (A/D) converter applications. With MOS transistors completely replacing the resistor load used in the conventional folder, this circuit has a good power-supply–rejection-ratio (PSRR) 21.2?dB for the output common voltage and can work well even under a very low power supply 1.0?V. A moderately high gain 14.5?dB and a wide input bandwidth 506?MHz are obtained. The circuit dissipates only 1.2?mW from 1.2?V power supply. The performance is verified by Hspice-Avanti-99.4 simulations on 0.18?µm digital CMOS technology.     

Low power FSK transmitter using all-digital PLL for IEEE 802.15.4g application

This paper presents low power frequency shift keying (FSK) transmitter using all-digital pll (ADPLL) for IEEE 802.15.4g application. In order to operate at low-power and to integrate a small die area, the ADPLL is adopted in transmitter. The phase noise of the ADPLL is improved by using a fine resolution time to digital converter (TDC) and digitally controlled oscillator (DCO). The resolution of the proposed TDC is improved by using a phase-interpolator, which divides the inverter delay time and the time amplifier, which amplifies the time difference between the reference frequency and the DCO clock. The phase noise of the proposed ADPLL is also improved by using a fine resolution DCO with an active capacitor. To cover the wide tuning range and to operate at a low-power, a two-step coarse tuning scheme with a metal insulator metal capacitor and an active inductor is used. The FSK transmitter is implemented in 0.18 μm 1-poly 6-metal CMOS technology. The die area of the transmitter including ADPLL is 2.2 mm². The power consumption of the ADPLL and transmitter is 12.43 and 22.7 mW when the output power level of the transmitter is ?1.6 dBm at 1.8 V supply voltage, respectively. The frequency resolution of the TDC is 1.25 ps. The effective DCO frequency resolution with the active capacitance and sigma-delta modulator is 2.5 Hz. The phase noise of the ADPLL output at 1.83 GHz is ?121.5 dBc/Hz with a 1 MHz offset.     

Fully digital fast transient phase-locked digital LDO-embedded-MDLL for DVFS applications

This paper presents a multiplying delay-locked loop (MDLL) embedded with a frequency-only reference (F_REF) based fully digital low-dropout regulator (DLDO) that outperforms conventional dynamic voltage and frequency scaling circuits when driving digital-load circuits that operate down to the near-threshold voltage level . We also propose a feed-forward acceleration (FFA) technique, which is dynamically activated only during the transient period to reduce the transient response time and voltage droop caused by the load current step. The proposed DLDO-embedded-MDLL was fabricated in a 40 nm CMOS process and occupies an active area of 0.02 mm². At the typical V_IN = 1.2 V and F_REF = 37.4 MHz, the regulated range of voltage was measured to be 0.56–1.16 V while the frequency being scaled from 0.411 to 2.35 GHz. With the proposed FFA technique, the load transient response and voltage droop were reduced by 61.5 and 35%, respectively, compared to the values during normal loop operation. In addition, the measured phase noise at 0.411 and 2.35 GHz was less than ?116 and ?104 dBc/Hz, respectively, both at 1 MHz offset.     

A combined low power SAR capacitance-to-digital analog-to-digital converter for multisensory system

A combined successive approximation (SAR) capacitance-to-digital converter (CDC)/analog-to-digital converter (ADC) for biomedical multisensory system is presented in this paper. The two converters have same circuit blocks and can be exchanged by four switches. Capacitance or voltage from different sensing elements can be measured and converted to digital output directly. This single chip takes place of separated CDC and ADC so that the power consumption of the multisensory system is reduced. The asynchronous SAR circuit has low power and small area. A dynamic comparator with zero-static power is adopted. Switches are carefully designed to reduce the non-idealities of the converter. Several techniques, such as bootstrapped switches, bottom-plate sampling, dummy switches are used to improve the performance of the circuit. The CDC/ADC is fabricated in 0.18 μm CMOS process. Measurement results show that the ENOB of this 11 bits converter is 10.15 bits and its FOM is 45 fJ/conversion-step under 200 kHz sampling. The power consumption is 9.4 μW with 1.4 V power supply voltage and the core area is 0.1764 mm².     

A rail-to-rail differential quasi-digital converter for low-power applications

This paper presents an ultra low power differential voltage-to-frequency converter (dVFC) suitable to be used as a part of a multisensory interface in portable applications. The proposed dVFC has been designed in 1.2-V 0.18-μm CMOS technology, and it works properly over the whole differential input range (0.6 ± 0.6 V) providing an output frequency range of 0.0–0.9 MHz. The system has been tested for temperature variations from ?40 to +120 °C and supply voltage variations of up to 30 %, being the maximum linearity error in the worse case of 0.017 %. Simulations against common mode voltage variations show a deviation in the output frequency of 0.4 %. This dVFC has power consumption below 60 μW, and it includes an enable terminal that sets the system in a sleep mode (180 nW) while no conversion is request. The dVFC occupies an active area of 250 μm × 150 μm.     

A 1-V low power gain boosted self-cascoding current mirror operational transconductance amplifier

A low-voltage, micro-power, low-noise, high-gain, high-output swing current mirror-based operational transconductance amplifier (OTA) is presented. The proposed OTA achieves high DC gain and output swing by the adoption of gain boosted current mirroring and self-cascoding techniques. From the simulation, the proposed OTA implemented on a 0.18 μm CMOS shows the DC gain up to 90 dB with a gain bandwidth of 700 KHz for a load capacitor of 1 pF and an output voltage swing of 600 mV. The OTA dissipates only 750 nW from 1.0 V supply.     

A compact 1–30 μH, 1–350 μF, 5–50 mΩ ESR compliant, 1.5% accurate 0.6 μm CMOS differential ΣΔ boost dc–dc converter

Emerging high-end portable electronics demand on-chip integration of high-performance dc–dc power supplies not only to save pin count, printed circuit board (PCB) real estate, and the cost of off-chip components but also to better regulate the point of load (PoL). In the face of a widely variable LC filter, however, integrating the frequency-compensation circuit is difficult without sacrificing stability performance, which is why integrated controller ICs only cater to relatively narrow LC ranges. While ΣΔ control addresses this LC compliance issue in buck dc–dc converters with high equivalent series resistance (ESR) output capacitors, it is not clear how it applies to ΣΔ boost converters. To that end, this paper discusses, analyzes, and experimentally evaluates a prototyped 0.6 μm CMOS differential ΣΔ boost converter. Experimental results verified the switching supply was stable across 1–30 μH, 1–350 μF, and 5–50 mΩ of inductance, capacitance, and ESR while keeping output voltage variations in response to 0.1–0.8 A load and 2.7–4.2 V line changes to less than ±1.5%, peak efficiency at 95%, and switching frequency variation to less than 27%.     

An area-and-power-efficient 8.4-bit ENOB 30 MS/s SAR ADC in 65 nm CMOS

Area and power consumption are two main concerns for the electronics towards the digitalization of in-probe 3D ultrasound imaging systems. This work presents a 10-bit 30 MS/s successive approximation register analog-to-digital converter, which achieves good area efficiency as well as power efficiency, by using a symmetrical MSB-capacitor-split capacitor array with customized small-value finger capacitors. Moreover, simplified dynamic digital logic and a dynamic comparator have been designed. Fabricated in a 65 nm CMOS technology, the core circuit only occupies 0.016 mm². The ADC achieves a signal-to-noise ratio of 52.2 dB, and consumes 61.3 μW at 30 MS/s from a 1 V supply voltage, resulting in a figure of merit (FoM) of 6.2 fJ/conversion-step. The FoM defined by including the area is 0.1 mm² fJ/conversion-step.     

A 4 μW dual-modulus frequency divider with 198 % locking range for MICS band applications

This paper presents the design and performance of an ultra-low-power 4/5 frequency divider based on a CMOS ring oscillator. Measurements show a 198 % locking range (6 MHz–1.3 GHz) for both division ratios at room temperature, covering the MICS band and 433 and 915 MHz ISM bands while consuming only 4.07 μW from a 1 V supply at 400 MHz. The wide locking range and low power consumption makes it very suitable for ultra-low-power wireless systems. The divider is fabricated in a 90 nm CMOS process and occupies 45 μm² of area.     

一种带有升压电路的0.5V 3GHz低功耗LC VCO设计

采用标准的0.13μm CMOS工艺实现了0.5V电源电压,3GHz LC压控振荡器。为了适应低电压工作,并实现低相位噪声,该压控振荡器采用了NMOS差分对的电压偏置振荡器结构,去除尾电流,以尾电感代替,采用感性压控端,增加升压电路结构使变容管的一端升压,这样控制电压变化范围得到扩展。测试结果显示,当电源电压为0.5V,振荡频率为3.126GHz时,在相位噪声为-113.83dBc/Hz@1MHz,调谐范围为12%,核心电路功耗仅1.765mW,该振荡器的归一化品质因数可达-186.2dB,芯片面积为0.96mm×0.9mm。