High Performance Process Variations Aware Technique for Sub-threshold 8T-SRAM Cell

The demand of low power high density integrated circuits is increasing in modern battery operated portable systems. Sub-threshold region of MOS transistors is the most desirable region for energy efficient circuit design. The operating ultra-low power supply voltage is the key design constraint with accurate output performance in sub-threshold region. Degrading of the performance metrics in Static random access memory (SRAM) cell with process variation effects are of major concern in sub-threshold region. In this paper, a bootstrapped driver circuit and a bootstrapped driver dynamic body biasing technique is proposed to assist write operation which improves the write-ability of sub-threshold 8T-SRAM cell under process variations. The bootstrapped driver circuit minimizes the write delay of SRAM cell. The bootstrapped driver dynamic body bias increases the output voltage levels by boosting factor therefore increasing in switching threshold voltage of MOS devices during hold and read operation of SRAM latch. The increment in threshold voltage improves the static noise margin and minimizing the process variation effects. Monte-Carlo simulation results with 3 \(\sigma \) Gaussian distributions show the improvements in write delay by 11.25 %, read SNM by 12.20 % and write SNM by 12.57 % in 8T-SRAM cell under process variations at 32 nm bulk CMOS process technology node.     

A 1.5-V differential cross-coupled bootstrapped BiCMOS logic forlow-voltage applications

Two new bipolar complementary metal-oxide-semiconductor (BiCMOS) differential logic circuits called differential cross-coupled bootstrapped BiCMOS (DC²B-BiCMOS) and differential cross-coupled BiCMOS (DC²-BiCMOS) logic are proposed and analyzed. In the proposed two new logic circuits, the novel cross-coupled BiCMOS buffer circuit structure is used to achieve high-speed operation under low supply voltage. Moreover, a new bootstrapping technique that uses only one bootstrapping capacitor is adopted in the proposed DC²B-BiCMOS logic to achieve fast near-full-swing operation at 1.5 V supply voltage for two differential outputs. HSPICE simulation results have shown that the new DC²B-BiCMOS at 1.5 V and the new DC²-BiCMOS logic at 2 V have better speed performance than that of CMOS and other BiCMOS differential logic gates. It has been verified by the measurement results on an experimental chip of three-input DC²B-BiCMOS XOR/XNOR gate chain fabricated by 0.8 μm BiCMOS technology that the speed of DC²-BiCMOS at 1.5 V is about 1.8 times of that of the CMOS logic at 1.5 V. Due to the excellent circuit performance in high-speed, low-voltage operation, the proposed DC²B-BiCMOS and DC²-BiCMOS logic circuits are feasible for low-voltage, high-speed applications     

A novel 2.2 Gbps LVDS driver circuit design based on 0.35μm CMOS

This paper presents a novel high-speed low voltage differential signaling(LVDS) driver design for point-to -point communication.The switching noise of the driver was greatly suppressed by adding a charge/discharge circuit and the operating frequency of the circuit was also increased.A simple and effective common-mode feedback circuit was added to stabilize the output common-mode voltage.The proposed driver was implemented in a standard 0.35μm CMOS process with a die area of 0.15 mm~2.The test result show...     

A 1.5-V full-swing bootstrapped CMOS large capacitive-load drivercircuit suitable for low-voltage CMOS VLSI

This paper reports a 1.5-V full-swing bootstrapped CMOS large capacitive-load driver circuit using two bootstrap capacitors to enhance the switching speed for low-voltage CMOS VLSI. For a supply voltage of 1.5 V, the full-swing bootstrapped CMOS driver circuit shows a 2.2 times improvement in switching speed in driving a capacitive load of 10 pF as compared to the conventional CMOS driver circuit. Even for a supply voltage of 1 V, this full-swing bootstrapped CMOS large capacitive-load driver circuit is still advantageous     

平板显示器驱动芯片高低电压转换电路

LCD、PDP、VFD等各类平板显示器已越来越受到人们关注与喜爱,但大多数平板显示器需要专用的功率驱动芯片来驱动其发光显示,各类专用功率驱动芯片又离不开高低电压转换电路,高低电压转换电路性能的好坏直接影响到驱动芯片的稳定性和功耗等。通过比较平板显示器驱动芯片的几种典型高低压转换电路,设计出一种带有电流源的CMOS型高低压转换电路,它具有最佳的性能指标,该电路不但可以为平板显示器驱动芯片使用,还可以作为其他各类驱动芯片的高低压转换模块使用,最后给出一种具体的平板显示驱动芯片高压CMOS器件结构。     

A Fully Differential CMOS Voltage Buffer for?Continuous- and Discrete-Time Applications

This paper presents a new CMOS analog fully differential voltage buffer, with large dynamic range and low harmonic distortion. Its design is based on the use of cross-coupled input differential pairs and internal current feedback. Two design approaches are proposed, with the objective of minimizing power consumption: one for switched-capacitor circuits and the other for Gm-C circuits. Design equations and simulation results are presented as well. Illustrative design examples are developed for a 0.35-μm CMOS technology using a power supply voltage of 2.5 V.     

Sub-1 V CMOS large capacitive-load driver circuit using directbootstrap technique for low-voltage CMOS VLSI

A novel sub-1 V CMOS large capacitive-load driver circuit using a direct bootstrap technique for low-voltage CMOS VLSI is reported. For a supply voltage of 1 V, the CMOS large capacitive-load driver circuit using the direct bootstrap technique shows a 3.3 times improvement in switching speed in driving a capacitive load of 2 pF compared to the conventional bootstrapped CMOS driver circuit using an indirect bootstrap technique. Even for a supply voltage of 0.8 V, this CMOS large capacitive load driver circuit using the direct bootstrap technique is still advantageous     

A 1.8 V low power 5 Gbps PMOS-based LVDS output driver with good return loss performance

This paper presents a novel design topology of a 5 Gbps PMOS-based low voltage differential signaling (LVDS) voltage mode output driver. The topology is designed to meet the requirements of low power consumption and high data rates applications. The driver consists of an output stage and a pre-driver stage where the driver’s swing and common-mode output voltage are set. The pre-driver and the output stage consume only 13.1 mW of power at 5 Gbps speed while operating from a 1.8 V voltage supply. Further, the design achieved ?21 dB return loss performance at DC. The driver was extracted and simulated using Mentor Graphics CAD tools and implemented in 180 nm CMOS technology. The output signal is fully compliant with the LVDS standard output swing and common-mode voltage specifications.     

A 1-mW K-band gate AC-coupled VCO with 0.25 V supply voltage

A K-band low-voltage voltage controlled oscillator (VCO) implemented in standard 65-nm bulk CMOS process is proposed. By using the proposed gate AC-coupling technique and biasing the cross-coupled transistors in moderate inversion region, the oscillator core operates under ultra low supply voltage with acceptable current efficiency. Reverse short-channel effect is also employed to reduce the threshold voltage of the cross-coupled transistors. Operating from 23.1 to 24.8 GHz, the fabricated VCO is able to work under supply voltage as low as 0.25 V with a core power consumption of 1 mW.     

适用于12 bit流水线ADC采样保持电路的设计

介绍了一种用于12 bit,20 MS/s流水线模数转换器前端的高性能采样/保持电路。该电路采用全差分结构、底极板采样来消除电荷注入和时钟馈通误差。采用栅压自举开关,并通过对电路中的开关进行组合优化,极大地提高了电路的线性性能。同时,运算放大器采用折叠式增益增强结构,以获得较高的增益和带宽。采用CSMC公司的0.5μm CMOS工艺库,对电路进行了仿真和流片。结果表明,在5 V电源电压下,采样频率为20 MHz,采样精度可达到0.012%,在输入信号为奈奎斯特频率时,无杂散动态范围(SFDR)为76 dB。     

A High-Performance CMOS Voltage-Controlled Oscillator for Ultra-Low-Voltage Operations

In this paper, a novel circuit topology of voltage-controlled oscillators (VCOs) suitable for ultra-low-voltage operations is presented. By utilizing the capacitive feedback and the forward-body-bias (FBB) technique, the proposed VCO can operate at reduced supply voltage and power consumption while maintaining remarkable circuit performance in terms of phase noise, tuning range, and output swing. Using a standard 0.18-mum CMOS process, a 5.6-GHz VCO is designed and fabricated for demonstration. Consuming a dc power of 3 mW from a 0.6-V supply voltage, the VCO exhibits a frequency tuning range of 8.1% and a phase noise of -118 dBc/Hz at 1-MHz offset frequency. With an FBB for the cross-coupled transistors, the fabricated circuit can operate at a supply voltage as low as 0.4 V. The measured tuning range and phase noise are 6.4% and -114 dBc/Hz, respectively     

一种新型的宽线性范围差分电压输入电流传输器及其应用

设计了一种带有共模检测电路的宽线性范围差分电压输入电流传输器(DVCCⅡ).所提出的电路具有动态的长尾电流的差分对,可获得较大的动态线性输入范围.所提出的电路可以得到精确跟随特性和宽线性输入范围,且比较已有电路具有低电压低功耗等特点.采用SMIC 0.18μm工艺,用Spectre对电路进行仿真,电源电压是1.8 V,...     

一种低压CMOS LDO稳压电源电路

提出了一种低压CMOS LDO稳压电源电路。与常规CMOS LDO稳压电源电路相比,该电路有两个主要特点:引入了低压带隙基准电路;将带隙基准电路置于串联稳压管后端。通过上述设计,提出的稳压电源电路能在输出电压较低的情况下提供较稳定的输出,同时也能提供稳定的偏置电压及具有较高PSRR的基准输出。对电路进行了仿真,并给出了仿真结果。     

一种高性能CMOS采样/保持电路

提出了一种高性能CMOS采样/保持电路,它采用全差分电容翻转型的主体结构有效减小了噪声和功耗。在电路设计中提出了新型栅源电压恒定的自举开关来极大减小非线性失真,并同时有效抑止输入信号的直流偏移。该采样/保持电路采用0.18μm1P-6M CMOS双阱工艺来实现,在1.8V电源电压、32MHz采样速率下,输入信号直到奈奎斯特频率时仍能达到86.88dB的无杂散动态范围(SFDR),电路的信号噪声失真比(SNDR)为73.50dB。最后进行了电路的版图编辑,并对样片进行了初步测试,测试波形表明,电路实现了采样保持的功能。     

42"PDP平板显示器扫描驱动IC及其生产工艺的实现

在自主研发国内BCD高压工艺的同时,设计并实现了一款用于42″数字电视PDP平板显示屏的扫描驱动芯片.该芯片及其制作工艺不仅实现了Bipolar,CMOS和高压功率DMOS器件的良好兼容（BCD工艺）,而且采用工艺与电路设计互相匹配的交互方式完成了高低电平位移电路和高压输出驱动电路及其器件的设计,有效提高了芯片的性能,减小了芯片的面积.测试结果表明该芯片功能正常,性能良好,各项技术参数基本达到国外同类产品指标.在低压5V和高压160V的情况下工作,完全满足42″PDP显示系统的需求.     

一种低功耗的13位100MS／s采样保持电路

采用TSMC0．18μm 1P6MCMOS工艺设计了一种高性能低功耗采样保持电路。该电路采用全差分折叠增益自举运算放大器和栅压自举开关实现。在3．3V电源电压下,该电路静态功耗仅为16．6mw。在100MHz采样频率时,输入信号在奈奎斯特频率下该电路能达到91dB的SFDR,其有效精度可以达到13位。     

A 1.5 V 10-b 30-MS/s CMOS pipelined analog-to-digital converter

A 1.5 V 10-b 30MS/s CMOS pipelined analog-to-digital converter (ADC) is described. Low-voltage techniques are proposed for pipelined analog-to-digital converter that avoids the use of low-threshold voltage process, on-chip clock voltage doubler, bootstrapped switch, or switched-opamp technique. At the front-end, a low-voltage S/H circuit with cross-coupled input sampling switch is employed to eliminate the input signal feedthrough and enhance the dynamic performance of the pipelined ADC. Multiplying digital-to-analog converter (MDAC) with cross-coupled configuration also provides an effective common-mode feedback to overcome the problem of common-mode accumulation. The prototype chips have been fabricated and experimental results confirm the feasibility of this new technique.     

低压CMOS带隙电压基准源设计

在对传统典型CMOS带隙电压基准源电路分析和总结的基础上,综合一级温度补偿、电流反馈技术,提出了一种1-ppm/°C低压CMOS带隙电压基准源。采用差分放大器作为基准源的负反馈运放,简化了电路设计。放大器输出用作电路中PMOS电流源偏置,提高了电源抑制比(PSRR)。整个电路采用TSMC0.35μmCMOS工艺实现,采用HSPICE进行仿真,仿真结果证明了基准源具有低温度系数和高电源抑制比。     

A feedback loop regulated bootstrap driver circuit with improved drive capability for high voltage buck DC–DC converter

A novel bootstrap driver circuit applied to high voltage buck DC–DC converter is proposed. The gate driver voltage of the high side switch is regulated by a feedback loop to obtain accurate and stable bootstrapped voltage. The charging current of bootstrap capacitor is provided by the input power of the DC–DC converter directly instead of internal low voltage power source, so larger driver capability of the proposed circuit can be achieved. The bootstrap driver circuit starts to charge the bootstrap capacitor before the switch node SW drop to zero voltage at high-side switch off-time. Thus inadequate bootstrap voltage is avoided. The proposed circuit has been implemented in a high voltage buck DC–DC converter with 0.6 µm 40 V CDMOS process. The experimental results show that the bootstrap driver circuit provides 5 V stable bootstrap voltage with higher drive capability to drive high side switch. The proposed circuit is suitable for high voltage, large current buck DC–DC converter.     

Design of a Low Voltage Highly Linear 2.4 GHz Up-Conversion Mixer in 0.18 μm CMOS Technology

This paper presents a low voltage highly linear up-conversion mixer for 2.4 GHz IEEE 802.11b WLAN transmitter applications based on a Chartered 0.18 μm CMOS technology. In the proposed mixer, the double balanced Gilbert cell topology was adopted and the dual resistive current-reuse and current-bleeding techniques in both the driver and switching stages with a capacitive cross-coupling technique were used. The up-conversion mixer can convert a 10 MHz intermediate frequency signal to a 2.4 GHz radio frequency signal, with a local oscillator power of 0 dBm at 2.39 GHz. A comparison with conventional CMOS mixer shows that this up-conversion mixer has advantages of low voltage, low power consumption and high performance. The post-layout simulation results demonstrate that at 2.4 GHz, the circuit provides 7.1 dB of conversion gain and the input-referred third-order intercept point of 11.3 dBm, while drawing only 5 mA for the mixer core under a supply voltage of 1.2 V. The chip area including testing pads is only 0.65 × 0.75 mm.