A novel ±0.5 V,high current drive,and rail to rail current operational amplifier

A current operational amplifier (COA) with very high current drive capability is presented in this paper. The principle of operation of this unique structure is discussed, its most important formulas are derived and its outstanding performance is verified by HSPICE simulation in TSMC 0.18 μm CMOS, BSIM3, and Level49 technology. Owing to the elaborately arranged components, the proposed circuit demonstrates very high frequency bandwidth, extremely high CMRR, high output impedance, and true rail to rail output voltage swing range while operating at very low power supply of ±0.5 V. The interesting results such as current drive capability of ±1 mA, high output impedance of 5 GΩ, wide gain bandwidth of 220 MHz, extremely high output voltage swing of ±0.45 V, which interestingly provides the highest yet reported output voltage compliance for current mode building blocks implemented by regular CMOS technology, low static power consumption of 159 μW, and very high CMRR of 155 dB is achieved utilizing standard CMOS technology. Full process, voltage, and temperature variation analysis of the circuit is also investigated in order to approve the well robustness of the structure. The transient stepwise and sinusoidal response analysis is also done to verify the proposed COA stability.     

Bulk-tuned Gm–C filter using current cancellation

A new approach for small transconductance (Gm) OTA designs, suitable for relatively low frequency filtering applications in the range of few kHz, is proposed. Small Gm values are achieved by a current cancellation technique, and are adjustable by bulk driving the MOS transistors of the input differential amplifier. The OTA design procedure takes into account Pelgrom׳s modeling of mismatch errors. A common-mode feedback control circuit based on floating gate common-mode voltage detector that shares the filter main capacitances is also presented. Experimental results obtained with a low-pass filter with tunable cutoff frequency implemented in a 0.35 μm CMOS process to verify the effectiveness of the design procedure have shown close agreement with the theory.     

CMOS current conveyor for ±3 v supply operation

The paper presents a precision CMOS current conveyor (CCII⁺), working in class A, suitable for low supply voltages (±3 V). Owing to a new solution of its input stage, a very lowx-input resistance (about 10 ) has been achieved without applying any loop of negative feedback. Since the circuit includes no high-gain feedback loop, there was no need to use a frequency-compensating capacitor (introducing a dominant pole) in order to ensure its stability. As a consequence, the conveyor is characterized by a higher bandwidth, for a given manufacturing process, compared to circuits including such capacitors. To ensure a high performance under the low supply conditions, a special cascode proposed in [1] has been applied which enables to realize precision current mirrors. PSPICE simulation studies based on detailed level-2 transistor-models are given. The obtained results are in a good agreement with the theory presented and show good properties and potentials of the conveyor.     

Characterization of CdMnTe radiation detectors using current and charge transients

Charge transport characteristics of Cd_0.95Mn_0.05Te:In radiation detectors have been evaluated by combining time resolved current transient measurements with time of flight charge transient measurements.The shapes of the measured current pulses have been interpreted with respect to a concentration of net positive space-charge, which has resulted in an electric field gradient across the detector bulk.From the recorded current pulses the charge collection efficiency of the detector was found to approach 100%.From the evolution of the charge collection efficiency with applied bias,the electron mobility-lifetime product ofμ_nτ_n =（8.5±0.4）×10^-4 cm²/V has been estimated.The electron transit time was determined using both transient current technique and time of flight measurements in the bias range of 100-1900 V.From the dependence of drift velocity on applied electric field the electron mobility was found to beμ_n =（718±55） cm²/（V·s） at room temperature.     

4H–SiC BJTs with current gain of 110

4H–SiC BJTs with a common emitter current gain of 110 have been demonstrated. The high current gain was attributed to a thin base of 0.25 μm which reduces the carrier recombination in the base region. The device open base breakdown voltage (BV_CEO) of 270 V was much less than the open emitter breakdown voltage (BV_CBO) of 1560 V due to the emitter leakage current multiplication from the high current gain by “transistor action” of BJTs. The device has shown minimal gain degradation after electrical stress at high current density of >200 A/cm²up to 25 h.     

Current‐mode quadrature oscillator using current differencing transconductance amplifiers

This article presents a new electronically tunable single‐element‐controlled current‐mode quadrature sinusoidal oscillator circuit using current differencing transconductance amplifiers (CDTAs). The proposed oscillator is consisted of two CDTAs, two grounded capacitors and one grounded resistor, which is beneficial to monolithic integrated circuit implementation both in CMOS and bipolar technologies. The condition of oscillation and the frequency of oscillation are independently controllable. The frequency of oscillation can also be electronically controlled by adjusting the bias current of CDTA. The circuit provides four quadrature current outputs and two quadrature voltage outputs. The current output terminals possess high impedance level. PSPICE simulation results are used to verify the performance of the proposed circuit implemented at the transistor level. The measurement results support the computer simulations.     

Why current secure scan designs fail and how to fix them?

Scan design has become another side channel of leaking confidential information inside cryptographic chips. Methods based on obfuscating scan chain order have been proposed as countermeasures for such scan-based attacks. In this paper, we first analyze the existing secure scan designs from the angle that whether they need a complete chain state or rely on any specific scan chain order. We show that all existing attacks do not rely on specific scan chain order and therefore any secure scan design with obfuscated scan chain order cannot provide sufficient security. We then propose a new approach which clears the states of all sensitive scan cells whenever the circuit under test is switched to test mode. It will also block the access to cipher key throughout the entire testing process. Our experimental results show that the proposed scan design can effectively insulate all the information related to cipher key from the scan chain with little design overhead, thus it can successfully defend all the existing scan-based attacks.     

Theory of tunneling current in metal-semiconductor contacts with subsurface isotype δ-doping

The theory of tunneling current in metal-semiconductor contacts with subsurface isotype δ-doping is developed. Analytical expressions for current that take into account the decrease in the potential barrier height due to the image forces are obtained using the Murphy-Good approach. Characteristics of δ-doping that provide effective thermal field emission at the metal-semiconductor contact and a decrease in the effective barrier height from the original value to several kT are calculated. It is established that the main voltage dependence of the current in a contact with isotype δ-doping is exponential. It is shown that the nonideality factor can remain small (n≤1.07) for all values of the barrier height. A dramatic increase in n to the values n≥1.5 is typical of contacts with a partially depleted layer.     

New dark current component of InGaAs/InP HPDs confirmed by DLTS

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Tiny-scale “stealth” current sensor to probe power semiconductor device failure

“Stealth” electric current probing technique for power electronics circuits, power device modules and chips makes it possible to measure electric current without any change or disassembling the circuit and the chip connection for the measurement. The technique consists of a tiny-scale magnetic-field coil, a high speed analog amplifier and a digitizer with numerical data processing. This technique can be applied to a single bonding wire current measurement inside IGBT modules, chip scale current redistribution measurement and current measurement for surface mount devices. The “stealth” current measurement can be utilized in the failure mechanism understanding of power devices including IGBT short circuit destruction.     

Investigation of current–voltage characteristics of vertically stacked all-NbCN Josephson junctions

Current–voltage characteristics of vertically stacked all-NbCN Josephson junctions has been investigated with a purpose to use them as an element of integrated circuits. It has been shown that increases of microwave power in the junction definition process using electron cyclotron resonance (ECR) etching causes reduction of the junction quality parameter. From results of a measurement of current–voltage characteristics for an array composed of five-fold vertically stacked NbCN/MgO/NbCN junctions, it has been found that a very high uniformity in critical currents can be achieved.     

New dark current component of InGaAs／InP HPDs confirmed by DLTS

The dark current of In_(0.47) Ga_(0.53) As/InP heterojunction photodiodes (HPDs) was analysed. We found that there exists a new dark current component-deep level-assisted tunnelling current.DLTS was used to measure the In_(0.47)Ga_(0.53)As/InP HPDs. An electronic trap which has a thermal activation energy of O.44 eV, level concentration of 3.10×10^(13)cm^(-3) and electronic capture cross section of 1.72×10^(12)cm^2 has been found.It s existence results in the new tunnelling current.     

Critical current–gate voltage characteristics in short- and long-gated Josephson junctions

We studied the gate controllability of the critical current and the normal resistance in superconductor–semiconductor–superconductor junctions. The junctions used a two-dimensional electron gas (2DEG) in the InAs-inserted InAlAs/InGaAs heterostructure. It is shown that the interface barrier between the superconductor and the 2DEG affects the controllability in a short-gated junction. In a split-gated junction, the critical current–normal resistance product is almost constant against gate voltage. This is due to quantization of both the critical current and the conductance in a narrow and short semiconductor channel. The long-gated junction in the quasi-ballistic transport regime shows rapid suppression of the critical current by gate voltage.     

Electron cyclotron current drive on WT-III by a 56 GHz gyrotron

Electron cyclotron current drive (EC-CD) experiments have been carried out at the fundamental and the second harmonics on the WT-III tokamak using extraordinary mode radiation at 56GHz launched from the low field side. The EC driven current of 24 kA is attained at the power level of 100 kW and the plasma with the density of 2 × 10¹²cm^?3 and the electron temperature of several hundreds eV can be sustained during the EC pulse. The efficiency of EC-CD is 1·0 × 10^?2 (10¹⁹m^?2 A W^?1) at the fundamental and 3·5 × 10^?2 at the second harmonic. The unidirectional high energy electrons in the initial target plasma is necessary for EC-CD     

High density and low leakage current based SRAM cell using 45 nm technology

This article is based on the observation of a Complementary Metal-Oxide Semiconductor (CMOS) five-transistor Static Random Access Memory (SRAM) cell (5T SRAM cell) for very high density and low power applications. This cell retains its data with leakage current and positive feedback without refresh cycle. This 5T SRAM cell uses one word-line and one bit-line and extra read-line control. The new cell size is 21.66% smaller than a conventional six-transistor SRAM cell using the same design rules with no performance degradation. Simulation and analytical results show purposed cell has correct operation during read/write and also the delay of new cell is 70.15% smaller than a six-transistor SRAM cell. The new 5T SRAM cell contains 72.10% less leakage current with respect to the 6T SRAM memory cell using cadence 45?nm technology.     

Modelling the current—voltage characteristic of a fluorescent lamp for computer-aided design

An empirical formula is presented for the voltage-current characteristics of a fluorescent lamp. The three parameters of the formula can easily be obtained from the measured characteristics of the fluorescent lamp without recourse to conventional curve-fitting techniques. By using this formula the analytical study of electronic circuits incorporating fluorescent lamps can be simplified.     

Leakage current mechanisms of ultrathin high-κEr_2O_3 gate dielectric film

A series of high dielectric material Er_2O_3 thin films with different thicknesses were deposited on p-type Si (100) substrate by pulse laser deposition at different temperatures. Phase structures of the films were determined by means of X-ray diffraction (XRD) and high resolution transmission electron microscopy (HRTEM). Leakage current density was measured with an HP4142B semiconductor parameter analyzer. The XRD and HRTEM results reveal that Er_2O_3 thin films deposited below 400 ℃ are amorphous, while films deposited from 400 to 840 ℃ are well crystallized with (111)-preferential crystallographic orientation. I-V curves show that, for ultrathin crystalline Er_2O_3 films, the leakage current density increases by almost one order of magnitude from 6.20 × 10~(-5) to 6.56×10~(-4) A/cm~2, when the film thickness decreases by only 1.9 nm from 5.7 to 3.8 nm. However the leakage current density of ultrathin amorphous Er_2O_3 films with a thickness of 3.8 nm is only 1.73×10~(-5) A/cm~2. Finally, analysis of leakage current density showed that leakage of ultrathin Er_2O_3 films at high field is mainly caused by Fowler-Nordheim tunneling, and the large leakage of ultrathin crystalline Er_2O_3 films could arise from impurity defects at the grain boundary.     

Analysis and design of low-voltage low-power high-speed double tail current dynamic latch comparator

The demanding need of ultra-high speed, area efficient and power optimized analog-to-digital converter is forcing towards the exploration and usage of the dynamic regenerative comparator to minimize the power, area and maximize the speed. In this paper, detailed analysis of the delay for the various dynamic latch based comparators is presented and analytical expressions are derived. With the help of analytical expressions, the designer can obtain insight view of the different parameters, which are the contributors of the delay in the dynamic comparator. Based on the findings, various tradeoffs can be explored. Based on the literature and presented analysis, a new dynamic latch based comparator is proposed. The basic double tail dynamic latch based comparator and shared charge logic are modified for low-power and high-speed with the reduced power supply in the proposed comparator. With the modified structure of double tail latch comparator and adding the shared charge logic, the regeneration delay is reduced, at the same time, power consumption is also reduced. Simulation results in 90 nm CMOS technology confirm the claimed reductions. The simulation is carried out using 90 nm technology with a supply voltage of 1 V, at 1 GHz of frequency resulting into the delay of 50.9 ps while consuming 31.80 μW of power.     

Integrated ZVS DC–DC converter with continuous input current and high voltage gain

An integrated zero-voltage-switching (ZVS) DC–DC converter with continuous input current and high voltage gain is proposed. The proposed converter can operate with soft switching, a continuous inductor current and fixed switching frequency. The voltage stress of the power switches is relatively low compared to the output voltage. Moreover, soft-switching characteristic of the proposed converter reduces switching loss of active power switches and raise the conversion efficiency. The reverse-recovery problem of output rectifiers is also alleviated by controlling the current changing rates of diodes with the use of the leakage inductance of a coupled inductor. The operation and performance of the proposed DC–DC converter were verified on an 115?W experimental prototype operating at 100?kHz.     

History,current developments,and future directions of near‐field optical science

This paper reviews the science of the optical near-field(ONF),which is created and localized in a nanometer-sized material(NM)or on its surface.It is pointed out that work on near-field optics was started in order to break through the diffraction limit in optical microscopy and had already come to an end without giving answers to the essential questions on the origin of the near-field optical interaction.However,recent studies have reincarnated these studies and identified the ONF as an off-shell quantum field.Based on this identification,a novel science called off-shell science has started on the basis that the dispersion relation between energy and momentum is invalid for the ONF.This quantum field is called the dressed photon because it is created as a result of the interaction between photons and electrons(or excitons)in a NM and,thus,it accompanies the energies of electrons or excitons.In reviewing current developments,this paper presents fifteen novel phenomena that are contrary to the common views in conventional optical science.Novel technologies developed by applying these phenomena are also reviewed.These include:nanometer-sized optical devices,nano-fabrication technology,and energy conversion technology.High-power Si light emitting diodes,Si lasers,and SiC polarization rotators are reviewed as examples of electrical to optical energy conversion.For future directions,this paper also reviews novel theoretical studies that have commenced recently by relying on physical and mathematical bases.