一种新型二元判定图器件和电路

提出了一种基于二元判定图(BDD)原理的新型逻辑器件和电路．BDD器件以电流模式的开关电流存储器为基本单元，具有符合二元判定图的两向通路的特点．用这种器件按照BDD树形图可以构成任意形式的组合逻辑电路．给出了或门、异或门及四位加法器电路的例子，并使用HSPICE仿真器进行了仿真，验证了这种器件及其电路的正确性．     

一种单刀双掷高速模拟开关的研制

介绍了一种单刀双掷高速模拟开关;描述了电路工作原理、线路设计、版图设计及可靠性设计。该高速模拟开关具有速度快、功耗低、隔离度高、关断漏电流小等特点。其内部电路设计有控制输入级、电平转换级、高速模拟开关管及静电保护电路。该电路可广泛应用于雷达接收机和发射机、通信系统和数据采集系统,以及通用模拟开关等领域。     

Low-voltage ULSI design

An overall view on low-voltage device and circuit design is presented, beginning with a discussion of the low-voltage limit. Low-voltage device design is then described. Low-voltage CMOS and BiCMOS logic circuits are discussed. Circuit techniques for the low-voltage DRAMs and SRAMs are presented. The low-voltage analog devices and circuits are considered. The future direction of the low-voltage and low-power ULSIs is discussed by comparing the switching energy of electronic devices and brain cells     

An improved GaAs device model for the simulation of analog integrated circuit

This paper describes an improved device model of GaAs MESFETs and heterojunction FETs for the design and analysis of analog integrated circuits. The proposed device model provides a new expression for the current and the capacitance of the device,which gives excellent agreements with experimental data for all regions of device operation. For the expression of the low frequency anomalies of GaAs devices, an improved technique with an equivalent circuit are presented to model the frequency dispersion of the transconductance and the drain conductance of the device, which give a good agreement with the experimental data of both the frequency dispersion and the lag effect of the device. The new device model proposed here clearly provides a superior prediction of the performance of GaAs analog integrated circuit.     

Mixed Mode VLSI Implementation of a Neural Associative Memory

A mixed mode digital/analog special purpose VLSI hardware implementation of an associative memory with neural architecture is presented. The memory concept is based on a matrix architecture with binary storage elements holding the connection weights. To enhance the processing speed analog circuit techniques are applied to implement the algorithm for the association. To keep the memory density as high as possible two design strategies are considered. First, the number of transistors per storage element is kept to a minimum. In this paper a circuit technique that uses a single 6-transistor cell for weight storage and analog signal processing is proposed. Second, the device precision has been chosen to a moderate level to save area as much as possible. Since device mismatch limits the performance of analog circuits, the impact of device precision on the circuit performance is explicitly discussed. It is shown that the device precision limits the number of rows activated in parallel. Since the input vector as well as the output vector are considered to be sparsely coded it is concluded, that even for large matrices the proposed circuit technique is appropriate and ultra large scale integration with a large number of connection weights is feasible.     

Impact of Scaling on Analog Performance and Associated Modeling Needs

This paper explores modeling and technology-scaling issues related to analog performance in advanced CMOS technologies. Performance metrics for analog circuits are defined, to provide insight into the impact of device scaling on power-constrained analog circuit design. Current and previous generation technologies (90 nm and older) are evaluated using standard compact models. Technology nodes below 90 nm are simulated at the device level to show trends in analog performance metrics and to evaluate the impact of nonminimum gate length and alternate doping profiles. Results indicate that the modeling of moderate-to-weak inversion behavior will continue to grow in importance. Simulations suggest that using nonminimum length and drain-side engineered devices at the 45-nm technology node offers an attractive degree of freedom for analog circuit design.     

Analog device design for low power mixed mode applications in deepsubmicron CMOS technology

Analog device design in the deep sub-micron regime is particularly challenging due to conflicting device performance requirements and the circuit requirements in analog applications. It is shown that novel single pocket devices improve the intrinsic analog performance compared to the conventional super steep retrograde devices, within the constraints imposed by circuit requirements. The effect of gate oxide thickness variation on the analog performance of the novel single pocket and conventional super steep retrograde n-channel MOSFETs is also evaluated. It is shown that for constraints on power supply scaling, single pocket structures offer a better option for low-power analog applications     

Impact of lateral straggle on analog and digital circuit performance using independently driven underlap DG-MOSFET

In this work, the effect of lateral straggle on independently driven underlap double gate MOSFET (IDUDGMOS) is presented based on analog and digital circuit performances. The lateral straggle in IDUDGMOS devices is due to process induced source/drain out diffusion and it varies the desired device characteristics. For the analysis of this variation on circuit performance of the device, an Amplitude Modulator (AM) circuit and a SRAM circuit is considered for analog and digital circuit application considerations respectively. For the analysis of the device in AM circuit the parameters studied are the bandwidth, the gain and the linearity, correspondingly for SRAM circuit the parameters studied are the Static Noise Margin (SNM) and the circuit delay. The analysis of the AM circuit designed using the IDUDGMOS suggested that the power loss and the bandwidth of the circuit degrade with increasing lateral straggle. For the SRAM circuit the analysis suggests that larger straggle lengths in the device results in reduced time delay but, the SNM is smaller as well.     

Design and Analysis of On-Chip ESD Protection Circuit with Very Low Input Capacitance for High-Precision Analog Applications

An ESD protection design is proposed to solve the ESD protection challenge to the analog pins for high-frequency or current-mode applications. By including an efficient power-rails clamp circuit into the analog I/O pin, the device dimension (W/L) of ESD clamp device connected to the I/O pad in the analog ESD protection circuit can be reduced to only 50/0.5 (m/m) in a 0.35-m silicided CMOS process, but it can sustain the human-body-model (machine-model) ESD level of up to 6 kV (400 V). With such a smaller device dimension, the input capacitance of this analog ESD protection circuit can be significantly reduced to only 1.0 pF (including the bond pad capacitance) for high-frequency applications. A design model to find the optimized layout dimensions and spacings on the input ESD clamp devices has been also developed to keep the total input capacitance almost constant (within 1% variation), even if the analog input signal has a dynamic range of 1 V.     

Net-Sensitivity-Based Optimization of Large-Scale Field-Programmable Analog Array (FPAA) Placement and Routing

Modern advances in reconfigurable technologies are allowing analog circuit designers to benefit from the computational flexibility provided by large-scale field-programmable analog arrays. With the component density of these devices, small analog circuits, as well as larger analog systems, can be synthesized and tested in a shorter time and at a lower cost, compared with the full design cycle. However, automated development platforms and computer-aided design tools for these devices are far fewer than the physical synthesis tools for their digital counterparts. One of the major reasons for this is the considerably higher impact of interconnect parasitics on circuit functionality in the analog domain; therefore, performance optimization must be recognized as an indispensable step of the analog physical synthesis flow. Our goal in this brief is to present a physical synthesis framework with an optimization core and an integrated simulation environment for verification of the synthesis results. Although SPICE has been used as the simulation tool for our experiments, there is no dependency on a particular circuit simulator. Our synthesis tool currently accepts SPICE netlists as input and gives priority to user-specified metrics when optimizing the synthesized circuit performance. Experimental results demonstrate the effectiveness of our approach.     

Automatic DC operating point computation and design plan generation for analog IPs

DC operating point computation is inescapable for both knowledge-based and simulation-based analog synthesis. In this perspective, this article presents the automatic computation of DC operating point and the?generation of suitable design plans for analog IPs. The analog IP is built as a hierarchy of subcircuits inside our dedicated framework CAIRO+. Leaf subcircuits are known as devices and higher-level subcircuits are known as modules. Each subcircuit is represented by a dependency graph. The?dependency graph expresses electrical dependencies of circuit parameters on a selected set of design parameters. The dependency graph of the analog IP is constructed, in a hierarchical bottom-up approach, by merging graphs of children devices and modules. The graph is converted to a directed acyclic graph (DAG) by detecting and removing existing directed cycles. The resulting DAG is the design plan for the analog IP. Upon construction, the DAG is executed, in a top-down approach, to compute the DC operating point and the dimensions of the transistors. The computed DC operating point is compared to a DC simulation to ensure its correctness. The proposed methodology has been successfully applied to size and bias two analog IPs: a single-ended two-stage operational amplifier and a?differential cascode current-mode integrator. The results prove the efficiency and accuracy of the proposed methodology.     

基于多软件平台协同工作的FIR滤波器设计

提出了利用多软件平台进行FIR数字滤波器的协同设计,改变了传统的只用硬件电路设计的方法,将整个数字滤波系统的硬件设计趋于软件化,采用Lattice公司的可编程模拟器件ispPAC20和Altera公司的FPGA设计架构整个FIR滤波器实验系统。由于ispPAC20和FPGA器件的高度集成化以及结构的可重构、可编程,使开发人员随时可重复配置满足各种性能要求的滤波器系统,将整个系统变得更小型化、更易于升级维护且更灵活。     

Design of sequential circuits by quantum-dot cellular automata

This paper proposes a detailed design analysis of sequential circuits for quantum-dot cellular automata (QCA). This analysis encompasses flip-flop (FF) devices as well as circuits. Initially, a novel RS-type FF amenable to a QCA implementation is proposed. This FF extends a previous threshold-based configuration to QCA by taking into account the timing issues associated with the adiabatic switching of this technology. The characterization of a D-type FF as a device consisting of an embedded wire is also presented. Unique timing constraints in QCA sequential logic design are identified and investigated. An algorithm for assigning appropriate clocking zones to a QCA sequential circuit is proposed. A technique referred to as stretching is used in the algorithm to ensure timing and delay matching. This algorithm relies on a topological sorting and enumeration step to consistently traversing only once the edges of the graph representation of the QCA sequential circuit. Examples of QCA sequential circuits are provided.     

Operational-amplifier compilation with performance optimization

A method for designing analog circuits in which topological design is followed by simultaneous device sizing and layout design is described. By merging circuit and layout design into a single design process, analog circuits can be optimally designed taking layout parasitics fully into account. Using the method, a CMOS operational-amplifier compiler (OAC) has been developed. Given a set of performance specifications and process parameters, OAC generates a layout with circuit performance optimized to meet specified performance constraints. A procedural layout technique is employed to generate a compact and practical layout. A nonlinear optimization method for device sizing which relies on the results of simulations based on the circuit extracted from the layout is applied. Design experiments have shown that OAC can produce satisfactory results with respect to both circuit performance and layout density     

一种新型色同步旗脉冲发生器的设计

提出了一种新型模拟电视信号色同步旗脉冲发生器，它采用脉宽调制的方法来产生模拟电视全电视信号编码中所需的色同步旗脉冲信号，充分利用ECL电路速度快的优点来得到准确的色同步旗脉冲信号，能充分满足模拟电视UV信号编码的要求。     

An Efficient Macromodeling Approach for Simulating Carbon-Nanotube Field-Emission Triode Devices in Display Applications

The advances of using carbon-nanotube (CNT) triode structure field-emission (FE) devices for display applications require an accurate and efficient SPICE-compatible device model for evaluating their electrical behaviors in the early circuit and system design stage. This letter presents a simple and efficient macromodeling approach that can accurately model the CNT triode FE devices independent of the device process and physical structures for circuit simulations.     

CMOS technology characterization for analog and RF design

The design of analog and radio-frequency (RF) circuits in CMOS technology becomes increasingly more difficult as device modeling faces new challenges in deep submicrometer processes and emerging circuit applications. The sophisticated set of characteristics used to represent today's “digital” technologies often proves inadequate for analog and RF design, mandating many additional measurements and iterations to arrive at an acceptable solution. This paper describes a set of characterization vehicles that can be employed to quantify the analog behaviour of active and passive devices in CMOS processes, in particular, properties that are not modeled accurately by SPICE parameters. Test structures and circuits are introduced for measuring speed, noise, linearity, loss, matching, and dc characteristics     

Rapid yield estimation as a computer aid for analog circuit design

A rapid yield estimation methodology that aids the analog circuit designer in making design tradeoffs that improve yield is presented. This methodology is based on using hierarchical evaluation of analysis equations, rather than simulations, to predict circuit performance. The new analog rapid yield estimation (ARYE) method has been used to predict the yield of two-stage operational amplifiers and has been incorporated into the Carnegie Mellon University (CMU) analog design system (ACACIA). An example of how ARYE allows analog designers to quickly explore the impact of design changes on yield is presented. The primary goal of ARYE is to make numerous early predictions of parametric yield economical for the analog circuit designer     

Causal reasoning mining approach to analog circuit verification

Functional errors in analog portion of mixed signal circuits become more severe and improvements in verification methods are increasingly important. Current verification methods fall into two categories, simulation-based verification and formal verification (Barke et al. [1]), focusing on verifying analog circuit function/performance. This paper proposes a novel approach verifying analog circuit design using causal reasoning. Causal reasoning is the inductive reasoning process to create a new design. The flow begins with mining the causal reasoning steps (design plan) that produced the circuit, including starting ideas, design step sequence, and their justifications (Jiao et al., 2015 [2]). Then, topological features corresponding to the starting ideas and design step sequence are verified individually by replacing the related devices with ideal behavior model. Performance is evaluated through Cadence Spectre simulation. Comparison with new circuit performance reveals incorrect functional issues and/or performance potentials for improvement. They are negative causes of certain starting ideas or design steps, which might have been omitted during the design process. The paper discusses three operational amplifier designs realized in 0.2-μm CMOS technology to illustrate the verification approach.