一个自偏压互补折叠式共源共栅放大器的设计

对传统CMOS折叠式共源共栅运算放大器进行分析和总结,利用自偏压互补折叠技术实现了一种高性能CMOS自偏压互补折叠式共源共栅运算放大器。这个设计消除了6个外部偏置电压,减小了供电电压,并且提高了输出摆幅和开环增益,同时,使用这个方案还可以使芯片面积、功耗、偏置部分对噪声和串扰的灵敏度降低,最后描述了设计过程并给出了设计的仿真结果,证实该结构的可行性。     

改进型折叠式共源共栅运算放大器电路的设计

在套筒式共源共栅、折叠式共源共栅运放中,折叠式共源共栅运算放大器凭借较大的输出摆幅和偏置电压的较低等优点而得到广泛运用。但是,折叠式的这些优势是以牺牲较大的功耗、较低的电流利用率而换取的。本文以提高电流利用率为着手点设计了一种改进的折叠式共源共栅运算放大器,在相同的电压和负载下改进的折叠式共源共栅运算放大器能显著提升跨导、压摆率和噪声性能。仿真结果表明在相同功耗和面积的条件下,改进的折叠式共源共栅运算放大器的单位增益带宽和压摆率是折叠式共源共栅运放的3倍。     

Double recycling technique for folded-cascode OTA

Presented is a double-recycling folded cascode (DRFC) operational transconductance amplifier (OTA), demonstrating another phase of significant performance enhancement over the existing folded cascode, recycling folded cascode and improved recycling folded cascode counterparts. Theoretical treatments and computer simulations under the same 65 nm CMOS technology justify fairly the merits of the proposed DRFC OTA.     

A fully-differential OTA based on CMOS cascode inverters operating from 1-V power supply

A low voltage operating fully-differential CMOS OTA construction, which uses dual-input CMOS cascode inverters, is proposed. The OTA is a two-stage configuration with dual-input CMOS cascode inverters at the input stage, and traditional CMOS inverters in the output stage, with a common-mode feedback path from the output terminals to one of the input terminals of cascode inverters. In order to effectively reduce its threshold voltages by bulk bias technique, the OTA has been designed and fabricated by using a 0.15 μm triple-well CMOS process. The OTA successfully operated from 1-V power supply, with 59 dB of differential voltage gain, 80.9 dB of CMRR and 25 MHz of unity gain frequency, at 60 μA of current consumption.     

CMOS CCII– based on modified dual output-OTA for high frequency applications

A negative CMOS second generation current conveyor (CMOS CCII–) based on modified dual output CMOS folded cascode operational transconductance amplifier (CMOS DO-OTA) is presented. The proposed folded cascode CMOS DO-OTA with attractive features for high frequency operation such as high output impedance, wide bandwidth, high slew rate, with low power consumption is used in the realisation. The proposed CMOS DO-OTA and CMOS CCII– with high performance parameters can be used in many high frequency applications. The proposed CMOS CCII– achieves 1.37 GHz (?3 dB BW), 1.8 ns settling time, 48 V/μs slew rate, and low power consumption around 3.25 mW for ±2.5 V supply. P-Spice simulation results are included for 0.5 μm MIETEC CMOS technology.     

Capacitor Cross-Coupled Fully-differential CMOS Folded Cascode LNAs with Ultra Low Power Consumption

This paper proposes a fully-differential folded cascode low noise amplifier (LNA) for 5.5 GHz receiver in 180 nm CMOS technology. By improving folded cascode with an additional inductance connected at the gate of CG stage to cancel parasitic capacitance and then employing capacitor cross-coupled technique as a negative feedback in the proposed LNA, the performance of the LNA can be improved significantly in terms of gain (S21) and noise figure (NF) compared with the conventional fold cascode LNA. Furthermore, the DC power consumption of the LNA is further reduced with forward body bias topology. The measurements show the proposed LNA achieves 16.5 dB power gain, a NF of 1.53 dB, good input/output matching with the S11 and S22 are less than \(-\) 15 dB. And the operating voltage is only 0.5 V with ultra-low power consumption of 0.89 mW.     

适用于高阶∑△调制器的全差分运算放大器的设计

比较了增益自举式共源共栅、折叠式共源共栅和套筒式A／A类三种常用的运算放大器结构．提出了一种可用于各种高阶∑△调制器的全差分运算放大器。采用SIMC0．35μm标准CMOS工艺．完成了含共模反馈电路的全差分套筒式运算跨导放大器的设计。仿真结果表明放大器的直流增益为84．5dB,单位增益带宽为199MHz,相位裕度为51°,电路工作可靠,性能优良。     

A very high performance self-biased cascode current mirror for CMOS technology

This paper presents a novel high performance self-biased cascode current mirror (CM) for CMOS technology. The proposed circuit shows a resistance compensated high bandwidth CM operating at low voltages. This circuit uses super cascode configuration to obtain high output impedance required for high performance of CM. Active implementation of passive resistances of the proposed circuit is shown. The simulations of proposed CM are carried out by Mentor Graphics Eldospice based on TSMC 0.18 μm CMOS technology, for input current range of 0–500 μA. A bandwidth of 2.26 GHz, input and output resistances of 679 Ω and 482 MΩ respectively, are obtained with a single supply voltage of ?1 V.     

Multipath recycling method for transconductance enhancement of folded cascade amplifier

A multipath recycling method to enhance transconductance of the folded cascode amplifier is presented in this paper. The proposed method utilizes two idle paths to conduct small signal current, which leads to significant enhancement of transconductance compared to conventional folded cascade structure. Moreover, the improved performance is almost at no expense of power dissipation. The proposed multipath recycling and the conventional amplifiers are all designed in UMC 0.18 μm CMOS technology. Simulation results demonstrate that the transconductance of the proposed amplifier is improved by 450% and dc gain enhances 16 dB when compared with the folded cascode counterpart.     

单片化低压低功耗Si CMOS运算放大器的实现

基于新型的折叠共栅共源PMOS差分输入级拓扑、轨至轨AB类低压CMOS推挽输出级模型、低压低功耗LV/LP技术特别考虑和EDA平台的实验设计与模拟仿真,并设计配置了先进的Si 2 mm P阱硅栅CMOS集成工艺技术。已经得到一种具有VT = 0.7 V、电源电压1.1~1.5 V、静态功耗典型值330 mW、75 dB开环增益和945 kHz单位增益带宽的LV/LP运算放大器。该运放可应用于ULSI库单元和诸多相关技术领域,其实践有助于Si CMOS低压低功耗集成电路技术的进一步开发与交流。     

A transconductance enhanced recycling structure for folded cascode amplifier

This letter is to present a transconductance enhanced recycling structure for folded cascode amplifier. The proposed structure introduces a positive feedback path to achieve a significant boost in transconductance without increasing power or area consumption. A folded cascode amplifier using the proposed structure was implemented in SMIC standard 65 nm CMOS process. Simulation results show that the proposed amplifier achieves 400% improvement in gain-bandwidth and 16.6 dB boost in DC gain compared to the conventional folded cascode.     

Robust design of low EMI susceptibility CMOS OpAmp

This paper addresses a new approach to design a CMOS operational amplifier which provides a good tradeoff between high gain and strong immunity to electromagnetic interferences. The proposed amplifier is based on two main blocks: the first is a fully differential folded cascode with modified input pair and the second is a source cross coupled AB class buffer. Thanks to the folded cascode stage and to the symmetrical output buffer, the amplifier exhibits both intrinsic robustness to interferences and good amplifier performances. The circuit was fabricated in a 0.8-/spl mu/m n-well CMOS technology (AMS CYE process). Experimental results, in terms of electromagnetic interference (EMI) immunity, are presented and successfully compared with commercial amplifiers. Measurements carried out on the chip and the amplifier overall performances are provided along with the corresponding simulation results.     

Post-linearization of cascode CMOS low noise amplifier using folded PMOS IMD sinker

A post-linearization technique for the cascode complementary metal oxide semiconductor (CMOS) low noise amplifier (LNA) is presented. The proposed method uses an additional folded cascode positive-channel metal oxide semiconductor field-effect transistor for sinking the third-order intermodulation distortion (IMD3) current generated by the common source stage, while minimizing the degradation of gain and noise figure. This technique is applied to enhance the linearity of CMOS LNA using 0.18-/spl mu/m technology. The LNA achieved +13.3-dBm IIP3 with 12.8-dB gain, 1.4dB NF at 2GHz consuming 8mA from a 1.8-V supply.     

A novel class of complementary folded-cascode opamps for low voltage

Three novel complementary folded-cascode operational amplifiers (opamps) with high gain, large bandwidth, and rail-to-rail input range for low-voltage operation will be presented. These opamps feature high bandwidth due to minimum internal nodes. The output swing is increased by properly adjusting the output cascode transistor gate voltages close to the power supply voltages. The opamps have been fabricated with a standard 0.8-/spl mu/m CMOS technology. Measurements show the amplification is between 60.1 and 72.4 dB, and the unity gain bandwidth is 14 MHz for a 5-pF load, 2.5-V power supply, and 150-/spl mu/A bias current.     

A power-efficient improved recycling folded cascode amplifier

An improved recycling folded cascode amplifier for wide-bandwidth ΣΔ modulator is presented in this article. The proposed amplifier introduces internal positive-feedback pairs to achieve a significant boost in transconductance and DC gain without increasing power or area budget. The proposed recycling folded cascode amplifier was implemented in SMIC standard 65?nm CMOS process. Compared to other recycling folded cascode structures, simulation results show that the proposed amplifier achieves the enhancement of gain-bandwidth and DC gain with the best figure-of-merits.     

A very high-frequency CMOS complementary folded cascode amplifier

A wide-band, fast settling CMOS complementary folded cascode (CFC) transconductance amplifier for use in analog VLSI high frequency signal processing applications is introduced. The superior performance of the CFC architecture over that of the folder cascode (FC) or mirrored cascode (MC) approaches for VLSI amplifiers is demonstrated. The symmetrically configured complementary input stage provides a wide common-mode input voltage range. The amplifier performs as an operational transconductance amplifier (OTA) and displays a first-order dominant pole when loaded by a shunt capacitor. The transconductance amplifier is small in area (0.016 mm²), and well suited for high frequency analog signal processing applications. Simulation and experimental results demonstrate a DC gain of approximately 50 dB, with a 0.1% settling response of under 10 ns for loads varied from 0 to 2 pF     

High-PSR sync separator for TV signals

This paper presents a novel NTSC video sync separator (NSS) with a high-PSR (power supply rejection) bias generation circuitry (BGC) which comprises a temperature compensation circuitry. The proposed BGC utilizes step-down regulators and a bandgap-based bias with cascode current control. The clamping voltages required for sync separation from an NTSC signal are generated. Detailed PSR analysis of the proposed BGC is also derived to circumscribe the clamping voltage variation. The proposed design is carried out using 0.35 μm 2P4M CMOS process. The measurement results verify that the HSYNC, the composite signal, and the Line 21 caption data can be separated successfully even if a 1 V noise is coupled in the supply voltage. The measured power consumption of the proposed chip is 31.92 mW.     

An Ultra-Wideband High-Linearity CMOS Mixer With New Wideband Active Baluns

A 2-11-GHz high linearity CMOS down-conversion mixer with wideband active baluns using 0.18-mum CMOS technology is demonstrated in this paper. The mixer employs a folded cascode Gilbert cell topology and on-chip broadband active baluns. The folded cascode approach is adopted to increase the output swing, and the linearity is enhanced by a harmonic distortion canceling technique derived from the harmonic balance analysis. The proposed configuration shows the highest IIP₃ and IP_{1 dB}, and exhibits more compact size than most published studies. A broadband active balun is used to generate wideband differential signals, together with the derivation of a closed-form expression for the phase imbalance. This single-ended wideband mixer has the conversion gain of 6.9plusmn1.5 dB, input 1-dB compression point (IP_{1 dB}) of - 3.5 dBm, single-sideband noise figure of 15.5 dB, and third-order input intercept point (IIP₃) of 6.5 dBm under the power consumption of 25.7 mW from a 1.8-V power supply. The chip area is 0.85 x 0.57 mm².     

High-performance V-band cascode HEMT mixer and downconverter module

A high-performance V-band cascode HEMT mixer is presented together with a compact downconverter module integrating the mixer with other receiver MMICs. The cascode mixer was optimized for conversion gain and/or linearity by employing the low-pass interstage networks and by optimizing the bias voltages. The low-pass interstage network effectively filters out the unwanted harmonics and spurious signals, and therefore, enhances the gain and the linearity of the cascode mixer. On a two-tone test, the cascode mixer showed a high conversion gain of 6.3 dB with an LO power of 2.6 dBm at 60 GHz. When the gate bias to the upper common-gate HEMT was tuned for the intermodulation distortion "sweet spot" theoretically predicted by the authors , the mixer showed a high third-order intercept point of 11.2 dBm with a decent gain of 4.1 dB under a small DC power consumption of 8 mW. To benchmark the performance of the cascode mixer of this work, a waveguide-based compact V-band downconverter module was built by integrating the mixer with an MMIC LNA, a VCO, and a LO driving amplifier. The downconverter module showed a conversion gain higher than 20 dB from 57.5 to 61.7 GHz. This paper shows the potential of the cascode FET mixer for high-performance compact downconverter applications at millimeter-wave frequencies.     

Continuous time common mode feedback technique for sub 1 V analogue circuits

A continuous time common mode feedback technique for sub 1 V analogue circuits using the bulk PMOS dynamic threshold (BP-DTMOS) technique is presented. The proposed method is used in a 0.8 V folded cascode amplifier in 0.18 /spl mu/m CMOS technology. The schematic and the post-layout simulation results show that this technique is effective in reducing common mode errors caused by process or environmental variations. It also improves the CMRR of the amplifier.