A 1.8-2.6 GHz CMOS VCO with switched capacitor array and switched inductor array

The design of a 1.76-2.56 GHz CMOS voltage-controlled oscillator(VCO)with switched capacitor array and switched inductor array is presented.Fabricated in 0.18μm 1P6M CMOS technology,the VCO achieves a 37% frequency tuning range.The measured phase noise varies between-118.5 dBc/Hz and-122.8 dBc/Hz at 1 MHz offset across the tuning range.Power consumption is about 14.4 mW with a 1.8 V supply.Based on a reconfigurable LC tank with switched capacitor array and switched inductor array,the mnmg range is analyzed and derived in terms of design parameters,yielding useful equations to guide the circuit design.     

1．3～2．2 GHz低噪声低功耗 CMOS LC VCO的设计

基于TSMC 0．18μm RFCMOS工艺,设计并实现了一个宽带低功耗低相位噪声的高性能压控振荡器（VCO）．为实现1．3～2．2 GHz调谐范围,VCO采用7‐bit（128根调谐曲线）固定电容阵列,同时也获得了超低的增益,降低了相位噪声．为弱化宽调谐范围带来的增益波动,VCO采用3‐bit可变电容阵列来提升低带曲线的斜率,以期与高带一致．为实现每根曲线的宽线性范围,可变电容采用分布式偏置电压技术．为降低相位噪声,还提出了一种输出零偏置架构以及电流源噪声滤除技术．测试结果表明,调谐电压的线性范围为0．2～1．6 V ;VCO输出频率范围为1．3～2．17 GHz ;高带调谐曲线叠合超过50％,低带超过80％;VCO增益仅为19 M Hz／V ;增益波动范围为13～25 M Hz／V ．当振荡频率为1312 M Hz ,1 M Hz 频偏处相位噪声为－116．53 dBc／Hz ;当振荡频率为2152 M Hz ,1 M Hz频偏处相噪为－112．78 dBc／Hz ．VCO功耗电流为1．2～3．2 mA ,电源电压为1．8 V ．提出的VCO既能提供51％的频率覆盖,又能实现低相位噪声,已经被成功应用于工业自动化无线传感网（WIA ）射频收发机芯片中．     

A 1.8-2.6 GHz CMOS VCO with switched capacitor array and switched inductor array

The design of a 1.76-2.56 GHz CMOS voltage-controlled oscillator(VCO) with switched capacitor array and switched inductor array is presented.Fabricated in 0.18μm 1P6M CMOS technology,the VCO achieves a 37% frequency tuning range.The measured phase noise varies between -118.5 dBc/Hz and -122.8 dBc/Hz at 1 MHz offset across the tuning range.Power consumption is about 14.4 mW with a 1.8 V supply.Based on a reconfigurable LC tank with switched capacitor array and switched inductor array,the tuning range is a...     

Differentially-Tuned VCO with Reduced Tuning Sensitivity and Flicker Noise Up-Conversion

Differential tuning in oscillators allows cancellation of common-mode bias noise and lower tuning sensitivity with respect to the most conventional single-ended tuning. However, the direct application of differential tuning increases the capacitor non-linearity and the flicker-induced phase noise. This paper analyzes quantitatively this phenomenon and proposes a novel configuration, which includes all the benefits of differential tuning with no penalty on phase noise. This circuit is fabricated in a 0.35-m CMOS technology together with a single-end-tuned oscillator and both cover the 2.0–2.4 GHz frequency range. The measured 1/f³ phase noise at 10 kHz offset is –71 dBc/Hz, which outperforms the companion single-end tuning oscillator by 10 dB.A.L. Lacaita is also with IFN-CNR Sezione Milano.Salvatore Levantino was born in 1973. He received the degree of Ingegnere in 1998 and the Ph.D. degree in electrical engineering in 2001 from the Politecnico di Milano, Italy. During his PhD program, he studied noise generation mechanisms in integrated oscillators and novel topologies for agile frequency synthesis. He also spent one year at Agere Systems (formerly Bell Laboratories), Murray Hill, NJ, working as consultant on IF-sampling receiver architectures. Since 2002, he is a post-doctoral researcher at the Politecnico di Milano. His research interests are mainly focused on fully integrated transceivers for wireless applications.Andrea Bonfanti was born in Besana B.za (Milan), Italy, in 1972. He received the Laurea Degree and the Ph.D. in electronics engineering from the Politecnico di Milano, Italy, in 1999 and in 2002, respectively. Since 2003, he is a post-doctoral researcher at the Politecnico di Milano. His activity is focused on the design of frequency synthesizers for wireless applications in CMOS. His research interests also include analog-to-digital converters.Luca Romanó was born in Milan, Italy, in 1976. He received the Laurea Degree in electronics engineering from the Politecnico di Milano, Milan, Italy, in 2001. He is currently working toward the Ph.D. degree in electronics and communications at the Politecnico di Milano. His research activity is oriented towards the development of frequency synthesizers for wireless broadband communications.Carlo Samori was born in 1966, in Perugia, Italy. He received the Laurea Degree in electronics engineering in 1992, and the Ph.D. in electronics and communications at the Politecnico di Milano, Italy, in 1995. In 2002, he was appointed Associate Professor of Electronics at the Politecnico di Milano. He worked on solid-state photo-detector and the associated front-end electronics. His current research interests include design and analysis of integrated circuits for communications in bipolar and CMOS technologies, noise analysis in oscillators, frequency synthesizer architectures. Since 1997, he is a Consultant of the Wireless Communication Circuit Research Department of Agere Systems, Murray Hill.Andrea L. Lacaita was born in 1962. He received the Laurea degree in nuclear engineering from the Politecnico di Milano, Italy, in 1985. In 1989–90, he was Visiting Scientist at the AT&T Bell Laboratories, Murray Hill, NJ, working on photo-refractive effects in superlattices for optical switching. In 1992, he became Associate Professor of Electronics at the Politecnico of Milano and since then, he has been teaching courses on electronics, electron devices, optoelectronics and solid-state physics. In 1999, he has been Academic Visitor at IBM T.J. Watson Research Center, Yorktown Heights, NY, where he contributed to the development of optical systems for IC testing. In 2000, he was appointed Full Professor of Electronics at the Politecnico di Milano and Head of the Microelectronics Lab. As researcher, he contributed to analog IC design with studies of phase noise in integrated LC-tuned oscillators and with the development of novel architectures of frequency synthesizers in RF front-ends. He has contributed to advances in microelectronics and optoelectronics, with particular emphasis on physics of single photon avalanche detectors, characterization and modeling of semiconductor devices. Within the field of ULSI microelectronics, he has studied carrier transport and quantum effect in scaled MOS transistors, technology and reliability of non-volatile memories. He is co-author of about 150 papers published in journals or presented in international conferences. He is also author of two books in Electronics.Prof. Lacaita received in 1993 the Award of the Italian Association of Electrical and Electronic Engineers (AEI) for his research on hot carrier effects. In 1998–2000, he served as Coordinator of the Committee on micro-and nano-electron devices of the Italian National Group of Electronics Engineers. Since 2000, he has been consultant for the European Commission in the evaluation on review of research projects in micro- and nano-electronics. Since 2001, he has been serving in the program committee of the IEEE International Electron Device Meeting (IEDM) and he is now European Chair.     

基于可变电容反馈技术的宽带VCO设计

该文提出了一种用于展宽Colpitts压控振荡器(VCO)调谐范围(T_R)的技术。为了实现宽调谐范围,采用一种可变电容反馈技术,该技术同时可得到优于传统Colpitts VCO的相位噪声。且该结构采用动态正向衬底自偏技术,以实现VCO较低功耗、易于起振的特性。基于90 nm CMOS工艺,设计了一款VCO,其相位噪声为-101.9 dBc/Hz@1 MHz,调谐范围为28.1%,考虑调谐范围的品质因数可达-192.2 dBc/Hz。芯片在1 V电压供电下,消耗了5.8 mW,芯片面积为0.45 mm~2。     

Design of 1.9 GHz RF CMOS VCO

A voltage controlled oscillator (VCO) module is designed, which can be used for the third generation mobile communication (3G) system. The circuit is simulated by spectre radio frequency (RF) by TSMC 0.25 μm CMOS process. During the simulation, the performance parameters of the designed VCO are as follows: tuning range 1.804 GHz-2.039 GHz, phase noise - 136.457 dBc/Hz @1 MHz, - 146.045 dBc/Hz@3 MHz, supply voltage 2.5 V, voltage output rate of 0.8 V-2.6 V, power consumption 25 mW. The layout of the related circuit is drawn by the Virtuoso Layout Editor.     

基于栅极电感反馈的CMOS差分Vacker VCO设计

提出了一种基于栅极电感反馈的Vacker压控振荡器(VCO),该结构能够改善电路的负阻抗,进而使得电路易于起振。对晶体管的负载效应和振幅稳定性的分析表明,该Vacker VCO相比较于Colpitts VCO,具有更好的振幅稳定性,进而改善了VCO的相位噪声。基于0.13-μm RF CMOS工艺,对该Vacker VCO进行了设计与芯片实现,测试结果表明：在消耗4.2 mW功耗的前提下,该VCO振荡频率为11 GHz～12.6 GHz,在11.8 GHz振荡频率处,相位噪声为-115.1 dBc/Hz@1 MHz,品质因数FOM指标达到-190.3 dBc/Hz。     

切换式调谐CMOS 压控振荡器

在现有的CMOS RF工艺条件下。利用“切换式调谐”设计思想完成了宽带调谐的压控振荡器(vco)的电路设计和版图设计。用Candence SpectreRF软件进行了模拟。结果表明。该VCO在保证其它性能指标的同时，实现了宽的频率覆盖。     

A low power tunable inductor based on active capacitor with negative resistance

A method to provide a low power tunable inductor is presented in which the inductance and its equivalent series resistance can be independently tuned. This equivalent series resistance can be also set to negative or zero value that is corresponding to inductor with ideal quality factor. In this method, a varactor is placed in parallel with a passive inductor and then, an active capacitor is placed in series with them. To this end, a low power Tunable Active Capacitor (TAC) is proposed which is capable of generating tunable capacitor and large negative resistance to compensate the loss of tunable inductor circuit. Also, the power consumption is low because of using a diode-connected transistor. A prototype of the proposed circuit is designed and simulated at 4 GHz. The electromagnetic simulation results show the inductance tuning range of 0.48–2.3nH with zero or even negative equivalent series resistance is obtained while the power dissipation is less than 3 mW. Moreover, noise analysis shows that higher inductance translates to lower noise while there is a weak correlation between noise and quality factor of the obtained inductances.     

60GHz宽调谐范围推—推压控振荡器设计

基于65nmCMOS工艺实现了60GHz推—推压控振荡器（VCO）设计。采用互补交叉耦合去尾电流源结构以降低相位噪声。压控振荡器输出包含两级缓冲放大器,第二级缓冲放大器偏置在截止区附近以增大二次谐波的输出功率。在1.2/0.8V电源电压下,压控振荡器核心和缓冲放大器分别消耗2.43mW和2.95mW。在偏离中心频率1MHz处相位噪声为-90.7dBc/Hz。输出功率为-2.92dBm。特别的,压控振荡器的调谐范围达到9.2GHz（15.3%）,与调谐范围相关的性能指标FOMT为-182.7dBc/Hz。该压控振荡器可应用于57GHz～64GHz开放频段超高速短距离无线通信。     

Floating active inductor based Class-C VCO with 8 digitally tuned sub-bands

A fully integrated floating active inductor based voltage-controlled oscillator (VCO) is presented. The active inductor employs voltage differencing transconductance amplifier (VDTA) as a building block. The designed VCO achieves frequency tuning by varying the bias current through the VDTA and utilizes a Class-C topology for improving the phase noise performance. The inductor-less VCO is designed and implemented in a 45-nm CMOS process and its performance is estimated using Virtuoso ADE of Cadence. Operating at a supply voltage of ±1 V, the proposed VCO consumes 0.44–1.1 mW corresponding to the oscillation frequency of 1.1–1.8 GHz thereby exhibiting a tuning range of 48.27%. The phase noise of the VCO lies in the range of −94.12 to −98.37 dBc/Hz at 1 MHz offset resulting in a FOM of −172.14 to −176.69 dBc/Hz.     

（英）W波段InP HBT 宽带高功率压控振荡器

本文介绍了一款具有较高输出功率和宽调谐频率范围的基波压控振荡器单片集成电路。其制作工艺为f_T =170GHz,f_max =250GHz的0.8um InP DHBT工艺。电路核心部分采用了平衡式考毕兹振荡器拓扑,并在后面添加了一级缓冲放大器来抑制负载牵引效应,并提升了输出功率。DHBT的反偏CB结作为变容二极管来实现频率调谐。芯片测量结果表明,VCO的频率调谐范围为81- 97.3GHz,相对带宽为18.3 %。在调谐频率范围内最大输出功率为10.5 dBm,输出功率起伏在3.5 dB以内。在该VCO的最大调谐频率97.3 GHz处相位噪声为-88 dBc/Hz @1MHz。在目前所报道的InP HBT基VCO MMIC中,本文在如此宽的频率调谐范围内实现了最高的输出功率。     

A low power and low phase-noise 91~96 GHz VCO in 90 nm CMOS

This paper reports a 94 GHz CMOS voltage-controlled oscillator (VCO) using both the negative capacitance (NC) technique and series-peaking output power and phase noise (PN) enhancement technique. NC is achieved by adding two variable LC networks to the source nodes of the active circuit of the VCO. NMOSFET varicaps are adopted as the required capacitors of the LC networks. In comparison with the conventional one, the proposed active circuit substantially decreases the input capacitance (C_in) to zero or even a negative value. This leads to operation (or oscillation) frequency (OF) increase and tuning range (TR) enhancement of the VCO. The VCO dissipates 8.3 mW at 1 V supply. The measured TR of the VCO is 91~96 GHz, close to the simulated (92.1~96.7 GHz) and the calculated one (92.2~98.2 GHz). In addition, at 1 MHz offset from 95.16 GHz, the VCO attains an excellent PN of – 98.3 dBc/Hz. This leads to a figure-of-merit (FOM) of ?188.5 dBc/Hz, a remarkable result for a V- or W-band CMOS VCO. The chip size of the VCO is 0.75 × 0.42 mm², i.e. 0.315 mm².     

一种Ku波段宽调谐范围高输出功率的InGaP/GaAs HBT VCO

本文介绍了一种采用InGaP/GaAs HBT工艺实现的全集成应用于Ku波段的压控振荡器(VCO)。该VCO采用Colpitts结构,以达到宽调谐范围,并且该VCO取得了较高的输出射频功率。测试结果表明：该VCO的振荡频率为12.82 GHz～14.97 GHz,调谐范围为15.47%,输出射频功率为0.31 dBm～6.46 dBm,在载频13.9 GHz处相位噪声为-94.9 dBc/Hz@1 MHz。在5 V单电源直流偏置下该VCO的功耗为52.75 mW,其芯片尺寸为0.81 mm×0.78 mm。最后,本文对VCO的品质因数FOM指标进行了讨论。     

低相位噪声毫米波单片压控振荡器的研制

采用0.18um GaAs PHEMT工艺,设计和研制了毫米波压控振荡器.该压控振荡器采用反射式结构,并针对了我国本地多点分配业务(LMDS)频段进行了优化设计,芯片采用OMM IC ED02AH工艺实现,芯片的尺寸为1.2mm×0.8mm.实测性能指标为:在28.46GHz,该压控振荡器的输出功率为7.3dBm,偏移1MHz处的相位噪声为-101dBc/Hz,调谐范围为27.5~30.4GHz.     

4.2GHz 1.8V CMOS LC压控振荡器

基于Hajimiri提出的VCO相位噪声模型,分析了差分LC VCO电路参数对于相位噪声的影响。根据前面的分析,详细介绍了LC VCO电路的设计方法:包括高Q值片上电感的设计、变容MOS管的设计以及尾电流的选取。采用SMIC 0.18μm 1P6 M、n阱、混合信号CMOS工艺设计了一款4.2GHz 1.8V LC VCO。测试结果表明:当输出频率为4.239GHz时,频偏1MHz处的相位噪声为-101dBc/Hz,频率调节范围为240MHz。     

采用有源电感的小面积宽可调范围VCO

为了实现电感-电容压控振荡器(LC VCO)的全集成和小面积,同时使其振荡频率具有较宽的可调范围和较低的相位噪声,采用差分有源电感和Q值增强共源共栅电路结构,对LC VCO进行设计。采用差分有源电感代替螺旋电感,减小了芯片面积,并利用有源电感的可调性,增大了振荡频率的可调范围。采用Q值增强共源共栅电路结构,增加了LC VCO的输出功率和Q值,进而减小了相位噪声。基于TSMC 0.18 μm RF CMOS工艺,采用Cadence仿真工具对LC VCO进行仿真验证。结果表明,LC VCO振荡频率的可调范围高达129%,在偏离最大振荡频率1 MHz处,最低相位噪声为-121.4 dBc/Hz,直流功耗为11 mW,优值FOMT(考虑到调谐范围)为-193.6 dBc/Hz。     

一款多模全球导航卫星系统接收机CMOS压控振荡器设计

本文介绍了一款应用在多模全球导航卫星系统中Σ-Δ小数频率合成器的压控振荡器的设计,压控振荡器采用双级积累模式可变电容器件。基于对调谐开关寄生电容的分析,压控振荡器优化了频率覆盖范围和调谐线性度,频率覆盖了GPS和北斗频段。压控振荡器采用了TSMC CMOS 0.18μm工艺,覆盖了GPS L1,BD B1/B2/B3频段的同时采用了线性化调谐技术,优化了相位噪声。恒定的VCO增益特性进一步提供了宽的电压调整范围,提高了环路的稳定性。     

高频宽调节范围压控振荡器设计研究

设计了一种基于0.18μm CMOS工艺模型的超高频宽调节范围的压控振荡器.系统采用3级环形压控振荡器结构,每级采用调节尾电流的方式,实现了2.5 GHz至5 GHz以上的高频宽调节范围.系统在输出频率为5 GHz时,在5 MHz频偏处的相位噪声为-89.26 dBc/Hz.此次设计的压控振荡器可广泛应用于各种嵌入式系统或ADC中,为其提供在大范围内可调节的时钟.