Low-power low-voltage reference using peaking current mirror circuit

A low-power low-voltage bandgap reference using the peaking current mirror circuit with MOSFETs operated in the subthreshold region is presented. A demonstrative chip was fabricated in 0.35 /spl mu/m CMOS technology, achieving the minimum supply voltage 1.4 V, the reference voltage around 580 mV, the temperature coefficient 62 ppm//spl deg/C, the supplied current 2.3 /spl mu/A, and the power supply noise rejection ratio of -84 dB at 1 kHz.     

A regulated body-driven CMOS current mirror for low-voltage applications

A CMOS current mirror (CM) based on the body-driven technique and active feedback scheme is presented. The proposed CM is immune to the threshold voltage limitation and offers much higher accuracy over wider current operating range than other body-driven CMs. The complete analysis of the input-output characteristics, system dc current transfer error, frequency, and noise performance is provided. By using a 1.5V/1V single power supply and 0.18-/spl mu/m n-well process, SPECTRE simulation results validate the analytical results and the overall good performance in terms of wider input-output voltage swing, lower input resistance, and larger output resistance compared with the conventional high-swing cascode CM.     

High-speed and high-precision current winner-take-all circuit

A CMOS high-performance current-mode winner-take-all circuit is presented. The circuit employs a novel technique for inhibitory and excitatory feedbacks based on input currents average computation, achieving both high speed and high precision. The circuit is designed for operation with a wide range of input current values, allowing its integration with circuits operating both in subthreshold and in strong inversion regions. Two circuits, each for a different range of input currents, have been implemented in a standard 0.35-/spl mu/m CMOS process available through MOSIS and are operated via a 3.3-V supply. Their operation is discussed, simulation results are reported and preliminary measurements from a test chip are presented.     

A high-speed, low-power bipolar digital circuit for Gb/s LSI's:current mirror control logic

A novel low-power bipolar circuit for Gb/s LSIs, current mirror control logic (CMCL), is described. To reduce supply voltage and currents, the current sources of emitter-coupled-logic (ECL) series gate circuits are removed and the lower differential pairs are controlled by current mirror circuits. This enables circuits with the same function as two-stacked ECL circuits to operate at supply voltage of -2.0 V and reduces the current drawn through the driving circuits for the differential pairs to 50% of the conventional level shift circuits (emitter followers) in ECL. This CMCL circuit achieves 3.1-Gb/s (D-FF) and 4.3-GHz (T-FF) operation with a power supply voltage of -2.0 V and power dissipation of only 1.8 mW/(FF)     

一种高精度双极性电流输出电路设计

电流电路由于其结构简单、抗干扰性强、安全性高和适合长距离传输等优点被广泛用于航空机载非电信号的机上传输,设计实现了一种双仪表放大器构造电流输出电路,支持-20～20mA的高精度恒流源输出,同时支持电压反馈及电流反馈两种实时监测,通过MutiSim仿真及实物测试,电流输出精度满足0.1%的设计要求,可用于机载设备的电流输出电路设计。     

designideas——改善双极电流吸收器的误差补偿方法

添加两个标准的1%公差电阻器,就可把电流吸收器的精度提高至少两个数量级。而且还可以补偿由电流增益较低的传输晶体管的基极电流引入的误差。为此,应测量晶体管的基极电流,并向源极参考电压添加一个成比例增减的误差项。在设计电流吸收器时,可使用MOSFET作为吸收器的传输晶体管,这是因为它的功率增益几乎无限,并且栅极电流很低。但是,高功率MOSFET带来很高的输入和输出电容,它们降低了吸收器的高频输出阻抗。作为替代品,电流增益较低的双极功率晶体管的输出电容比额定功率相当的MOSFET低得多。图1的设计是针对某种基于双极晶体管的…     

一种高精度时钟同步电路

本文提出了一种基于交错延迟单元和动态补偿电路的高精度时钟同步电路结构,HPSC,并 可用在对时钟要求较高的大规模分布网络中。此电路采用了基于SMD的粗调结构和动态补偿 电路的细调结构,可在两个时钟周期内完成粗调并在接下来三个时钟周期内完成细调,其误 差小于3.8 ps。本电路使用SMIC 0.13 μm 1P6M 工艺设计并实现,供电电压1.2 V。其输入 频率为200MHz-800MHz,占空比为20%-80%,有效面积 245μm×134μm,功耗为1.64 mW@500MHz     

A bitline leakage compensation scheme for low-voltage SRAMs

A bitline leakage current of an SRAM, induced by leakage current of the transmission transistors in the cells that are associated with the bitline, increases as the threshold voltage (V_TH) of the transistors is reduced for high performance at low power-supply voltage (V_DD). The increased bitline leakage causes slow or incorrect read/write operation of an SRAM because the leakage current acts as noise current for a sense amplifier. In this paper, the problem has been solved from a circuitry point of view, and the scheme which detects the bitline leakage current in a precharge cycle and compensates for it during a read/write cycle is proposed. Employing this scheme, the SRAM with 360-μA bitline leakage current can perform a read/write operation at the same speed as one that has no bitline leakage current. This enables a 0.1-V reduction in V_TH, and keeps the V_TH and delay scalability of a high-performance SRAM in technology progress. An experimental 8-Kb SRAM with 256 rows is fabricated in a 0.25-μm CMOS technology, which demonstrates the effectiveness of the scheme     

A high-precision VLSI winner-take-all circuit for self-organizingneural networks

The design and implementation of a high-precision VLSI winner-take-all (WTA) circuit that can be arranged to process 1024 inputs are presented. The cascade configuration can be used to significantly increase the competition resolution and maintain high-speed operation for a large-scale network. The total bias current increases in proportion to the number of circuit cells so that a nearly constant response time is achieved. A unique dynamic current steering method is used to ensure that only a single winner exits in the final output. Experimental results for a prototype chip fabricated in a 2-μm CMOS technology show that a cell can be a winner if its input is larger than those of the other cells by 15 mV. The measured response time is around 50 ns at a 1-pF load capacitance. This analog winner-take-all circuit is a key module in the competitive layer of self-organizing neural networks     

A resonant energy-recovery circuit for plasma display panel employing gas-discharge current compensation method

A resonant energy-recovery circuit for a plasma display panel (PDP) employing a gas-discharge current compensation method is proposed. Its main concept is to make the resonant circuit biased by V/sub s/ and 0V instead of V/sub s//2 in charging and discharging the PDP, respectively. This operation helps the PDP to be fully charged and discharged and all main switches turned on under zero-voltage switching. Moreover, since the inductor current can compensate the large gas-discharge current, the current stresses on main power switches can be considerably reduced and all main switches have the turn-on timing margin, which ensures the no voltage drop across the PDP. Therefore, all these features could favorably provide a high energy-recovery capability, more accumulated wall charge, reduced sustaining voltage, and low electromagnetic interference. Therefore, the proposed circuit is expected to be well suited for a hang-on-the-wall PDP TV.     

Implementation of low-voltage static RAM with enhanced data stability and circuit speed

This paper presents a novel SRAM circuit technique for simultaneously enhancing the cell operating margin and improving the circuit speed in low-voltage operation. During each access, the wordline and cell power node of selected SRAM cells are internally boosted into two different voltage levels. This technique with optimized boosting levels expands the read margin and the write margin to a sufficient amount without an increase of cell size. It also improves the SRAM circuit speed owing to an increase of the cell read-out current. A 256 Kbit SRAM test chip with the proposed technique has been fabricated in a 0.18 μm CMOS logic process. For 0.8 V supply voltage, the design scheme increases the cell read margin by 76%, the cell write margin by 54% and the cell read-out current by three times at the expense of 14.6% additional active power. Silicon measurement eventually confirms that the proposed SRAM achieves nearly 1.2 orders of magnitude reduction in a die bit-error count while operating with 26% faster speed compared with those of conventional SRAM.     

基于自偏置电流镜的CMOS红外焦平面读出电路

针对高精度红外焦平面阵列应用设计了一种具有高注入效率、大动态范围、稳定的探测器偏压、小面积和低功耗的自偏置电流镜注入CMOS读出电路.所设计的电路结构包括一种由自偏置的宽摆幅PMOS共源共栅电流镜和NMOS电流镜构成的反馈结构读出单元电路和相关双采样电路.对所设计电路采用Chartered 0.35 μm CMOS工艺进行了流片.测试结果显示:电路线性度达到了99%,探测器两端偏压小于1mV.电路输入阻抗近似为0,单元电路面积为10μm×15μm,功耗小于0.4μW.电量存储能力3108电子.测试结果表明:电路功能和性能都达到了设计要求.     

A high-precision current-mode WTA-MAX circuit with multichipcapability

This paper presents a circuit design technique suitable for the realization of winner-take-all (WTA), maximum (MAX), loser-take-all (LTA), and minimum (MIN) circuits. The technique presented is based on current replication and comparison. Traditional techniques rely on the matching of an N transistors array, where N is the number of system inputs. This implies that when N increases, as the size of the circuit and the distance between transistors will also increase, transistor matching degradation and loss of precision in the overall system performance will result. Furthermore, when multichip systems are required, the transistor matching is even worse and performance is drastically degraded. The technique presented in this paper does not rely on the proper matching of N transistors, but on the precise replication and comparison of currents. This can be performed by current mirrors with a limited number of outputs. Thus, N can increase without degrading the precision, even if the system is distributed among several chips. Also, the different chips constituting the system can be of different foundries without degrading the overall system precision. Experimental results that attest these facts are presented     

高精度标准镜支撑结构的研究与设计

为了保证高精度光学元件面形检测精度,必须对干涉仪标准镜自身的面形精度进行严格控制。在考虑标准镜自重的情况下,采用有限元方法研究了不同胶点数量及分布形式、不同的镜框支撑方式对参考面面形精度的影响。根据研究结果,针对球面标准镜面形精度要优于/40的要求,设计了口径150mm的标准镜的支撑方式,采用123点胶接、镜框底面六点的挠性支撑方式,经有限元分析得到:参考面面形的PV值为7.36nm,RMS值为1.52nm;并验证了温度变形较自重变形很小。结果表明,各项指标满足设计要求,证明了结构设计的合理性。     

一个低功耗低电压的二级运放压摆率增强电路

本文提出了一个新颖的二级运放压摆率增强电路。该电路采用AB类输入级,提高了电流效率。相对于运放,它完全开环工作,因此不会影响运放的稳定性。当运放处于压摆阶段时,电路检测运放输入差分电压,产生外部的动态电流并注入运放,从而使加快负载电容的充/放电过程。电路仿真结果显示：对于大的输入阶跃信号,该电路可以减少50%的建立时间;将电路运用于采样保持电路时,该电路提高了无杂散动态范围44.6dB,降低了总谐波失真43.9dB。本文提出的电路非常适用于低电压（1.2V或更低）工作,并且只消耗200μA的静态电流。     

A low-voltage micropower JFET/bipolar operational amplifier

A single cell supply (operable down to 1.2 V) micropower operational amplifier using compatible low pinchoff voltage JFET's (V/SUB p/=0.4 V) in conjunction with standard bipolar technology has been developed. The subvolt pinchoff JFET's have proved useful in the common-mode feedback-assisted biasing of a simple p-n-p input stage to permit single supply operation, the design of a low-voltage high-performance current mirror and a differential to single-ended converter. The amplifier exhibits excellent ac performance (unity gain slew rate=0.25 V//spl mu/s, unity gain bandwidth=850 kHz) with low power dissipation (245 /spl mu/W).     

Tunable current mirror and its application in LNA

A novel topology of current mirror (CM) with tunable output current is proposed. Two methods for output current tuning are presented. The first one utilizes an analog input voltage for linear current output, and the second one has an N-bit digital input signal for 2~N un-continuous current outputs. A linearization method for low noise amplifier (LNA) is proposed and realized with this tunable CM. As the provider of the bias current, the CM has brought the LNA a lower NF (noise figure) and a higher IIP3 (input-referred third-order intercept point) compared with a conventional one. The experimental results show that the LNA achieves 1.47 dB NF and + 19.83 dBm IIP3 at 860 MHz.     

可调节镜像电流源的研究及其在LNA中应用

A novel topology of current mirror （CM） with tunable output current is proposed. Two methods for output current tuning are presented. The first one utilizes an analog input voltage for linear current output, and the second one has an N-bit digital input signal for 2N un-continuous current outputs. A linearization method for low noise amplifier （LNA） is proposed and realized with this tunable CM. As the provider of the bias current, the CM has brought the LNA a lower NF （noise figure） and a higher IIP3 （input-referred third-order intercept point） compared with a conventional one. The experimental results show that the LNA achieves 1.47 dB NF and ＋ 19.83 dBm IIP3 at 860 MHz.