SoC based floating point implementation of differential evolution algorithm using FPGA

This paper presents floating point design and implementation of System on Chip (SoC) based Differential Evolution (DE) algorithm using Xilinx Virtex-5 Field Programmable Gate Array (FPGA). The hardware implementation is carried out to enhance the execution speed of the embedded applications. Intellectual Property (IP) of DE algorithm is developed and interfaced with the 32-bit PowerPC 440 processor using processor local bus (PLB) of Xilinx Virtex-5 FPGA. In the proposed architecture the algorithmic parameters of DE are scalable. The software and hardware implementation of the DE algorithm is carried out in PowerPC embedded processor and hardware IP respectively. The optimization of numerical benchmark functions and system identification in control systems are implemented to verify the proposed hardware SoC platform. The performance of the IP is measured in terms of acceleration gain of the DE algorithm. The optimization problems are solved by using floating point arithmetic in both embedded processor and hardware. The experimental result concludes that the hardware DE IP accelerates the execution speed approximately by 200 times compared to equivalent software implementation of DE algorithm on PowerPC 440 processor. Further, as a case study an Infinite Impulse Response (IIR) based system identification task on SoC using the developed hardware accelerator is implemented.     

Linux在Xilinx FPGA上的移植

Xilinx公司开发的Virtex-Ⅱ pro等FPGA结合可编程片上系统（SOPC）技术嵌入了PowerPC处理器硬核。本文结合Linux操作系统的优点及PowerPC嵌入式处理器硬核,在Virtex-Ⅱ Pro开发平台上,研究并实现了Linux操作系统在PowerPC405处理器中的移植,其中包括硬件平台的定制、交叉编译环境的建立、内核的配置及根文件系统的制作,最后通过具体的应用验证了系统的稳定性及可靠性。文中将处理器、操作系统与FPGA融合在一起完成既定的信号处理任务,既具有操作系统多任务、实时性等优点,又充分发挥了FPGA的优势,具有较好的应用前景。     

基于SOPC可重构的图像采集与处理系统设计

针对目前PC算法无法实现图像实时处理以及固定硬件平台很难实现算法修改或者升级的问题,设计一种基于SOPC可重构的图像采集与处理系统,实现了图像数据的片上实时处理以及在不改变硬件电路结构而完成算法修改或者升级的功能。此系统围绕两块Xilinx FPGA芯片进行设计,通过FPGA以及其Microblaze 32 bit软核处理器和相关接口模块实现硬件电路设计,结合FPGA开发环境ISE工具和EDK工具协作完成软件设计。由于采用SOPC技术和可重构技术,此设计具有设计灵活、处理速度快和算法可灵活升级等特点。     

基于FPGA片上PowerPC实现动态重构

文章介绍了FPGA动态部分重构的实现原理及实现方法,以FPGA内嵌PowerPC处理器内核为基础,通过ICAP内部配置访问通道,控制可重构模块进行在线局部重构,完成了系统动态重构的流程,充分利用了系统的硬件资源,实现了部分动态重构技术在SOPC中的应用。     

嵌入式PowerPC硬核环境下的操作系统移植

AFPGA芯片中嵌入处理器的硬核或软核,构成片上可壕程系统（SoPC）。对于专门的处理器体系结构,为了能够在源代码级别上对操作系统进行定制,以提供实时服务,一般采用将Linux内核进行剪裁并移植的方法。本文给出了在Xilinx Virtex4的PowerPC硬核环境下移植Linux内核的过程,并通过Vjrtex ML403开发板进行原型验证,以展示操作系统内按移植的整体思路以及各环节的关键步骤。     

System Architecture and Implementation of MIMO Sphere Decoders on FPGA

Multiple-input-multiple-output (MIMO) systems use multiple antennas in both transmitter and receiver ends for higher spectrum efficiency. The hardware implementation of MIMO detection becomes a challenging task as the computational complexity increases. This paper presents the architectures and implementations of two typical sphere decoding algorithms, including the Viterbo-Boutros (VB) algorithm and the Schnorr-Euchner (SE) algorithm. Hardware/software codesign technique is applied to partition the decoding algorithm on a single field-programmable gate array (FPGA) device. Three levels of parallelism are explored to improve the decoding rate: the concurrent execution of the channel matrix preprocessing on an embedded processor and the decoding functions on customized hardware modules, the parallel decoding of real/imaginary parts for complex constellation, and the concurrent execution of multiple steps during the closest lattice point search. The decoders for a 4times4 MIMO system with 16-QAM modulation are prototyped on a Xilinx XC2VP30 FPGA device with a MicroBlaze soft core processor. The hardware prototypes of the SE and VB algorithms show that they support up to 81.5 and 36.1 Mb/s data rates at 20 dB signal-to-noise ratio, which are about 22 and 97 times faster than their respective implementations in a digital signal processor.     

Unsupervised image thresholding: hardware architecture and its usage for FPGA-SoC platform

ABSTRACT

Otsu’s global automatic image thresholding operation is used in various image processing applications. It needs computation of normalized cumulative histogram, mean and cumulative moments that are compute-intensive operations. In this paper, a custom architecture is presented for an efficient computation of Otsu’s algorithm along with its utilization as an intellectual property (IP) core in a field programmable gate array (FPGA) based system-on-chip (SoC) environment for the application of connected component analysis (CCA). A self-normalization technique is employed, where single-cycle, read–modify–write operations are performed with block random access memories (BRAMs) and digital signal processing (DSP)slices. The architecture is designed for 640 × 480 size of images that are captured by a high-resolution analouge camera and buffered in a DDR2 SDRAM of Xilinx ML-507 platform at 25.175 MHz clock frequency. The embedded PowerPC processor core is used to control the frame acquisition process. Experimental results on Virtex-5 xc5vfx70t FPGA device show that the architecture utilizes 1.4% slices, 2.7% BRAMs and 3.9% DSP48E slices. The total power consumption of the design is 1440.59 mW. The proposed architecture as an IP core is able to work in real-time with standard VGA resolution video and requires low computational resources.     

基于CPCI总线的PowerPC主处理板设计

介绍了嵌入式系统中使用的基于CPCI总线的PowerPC主处理板的设计方法,以目前广泛应用的G4系列RISC微处理器MPC7410作为核心处理器,以PCI07作为控制器,PCI6150作为PCI-to-PCI桥,加上FPGA控制电路构成硬件平台,并移植VxWorks作为操作系统.提供多种标准接口,支持扩展功能,性能稳定...     

智能摄像系统视频采集模块的嵌入式结构

介绍的是实时视频采集模块的嵌入式结构,来实现智能的实时监控。嵌入式结构用赛灵思ML-507平台来进行开发。平台Virtex -5FXT FPGA设备中的FPGA结构中内嵌PowerPC440处理器,旋转变焦（PTZ）摄像机和VGA监视器与该平台连接。接口使用机载VGA输入视频编解码器和DVI发射器芯片。芯片的控制寄存器配置使用嵌入式PowerPC440处理器。应用软件用C语言编写。完成了视频的采集、传输、分辨率为640*480的显示。连接、处理能力高,FPGA消耗资源占18%,剩下的FPGA资源足够实现视频处理的应用。     

基于SOPC的嵌入式系统

利用SOPC Builder可以在短时间内把Nios Ⅱ CPU、Avalon总线、外围设备、片内调试模块等集成在一起生成系统需要的NiosⅡ处理器，然后用QuartusⅡ软件把NIOSⅡ处理器其它外部设备接口结合在一起编译下载到FPGA芯片中，即完成系统的硬件设计；软件设计通常采用C／C＋＋语言编写并用NoisⅡIDE编译后下载到FPGA中来实现一个SOPC系统。     

基于片上PowerPC的Vxworks处理平台的波束控制设计

片上嵌入式系统凭借其诸多方面的优势,如成本低、功耗低、尺寸小、处理速度快、可靠性高、实时性强、灵活性、产品上市时间以及设计开发周期短等优势,将嵌入式实时多任务操作系统VxWorks和基于FPGA的片上PowerPC平台相结合,使产品体积更小、环境适应性更强、运行更可靠、扩展和升级更灵活、生产成本更低。必将成为将来雷达产品上的主流技术。本文提出了在其内嵌PowerPC440处理器上构建Vxworks操作系统平台的雷达的波束控制设计。     

基于片上PowerPC的Vxworks处理平台设计

随着数字信息技术和网络技术的高速发展,嵌入式系统设计已经成为目前蓬勃发展的行业之一。由于FPGA嵌入式处理器具有体积小、功耗低、集成度高、能与FPGA内部逻辑紧密结合的优势,它必将引领嵌入式系统设计的新潮流。基于Xilinx公司Virtex-IV系列FPGA平台,在其内嵌PowerPC405处理器上构建Vxworks操作系统平台,通过与传统嵌入式处理平台的比较说明该平台的特点和优势。详细阐述了系统软硬件协同设计方法和平台构建过程。     

基于ARM+FPGA的影像交互与显示系统设计

为促进航空测绘信息获取的数字化、一体化、实时化,本文利用FPGA(Field-Programmable Gate Array,即现场可编程门阵列)并行处理的优势结合ARM处理器低功耗高性能的特点,基于ARM+FPGA的双核硬件架构实现了影像的交互与显示。该系统以Linux操作系统为软件开发平台,以ARM11嵌入式处理器为硬件核心、FPGA作为协处理器,采用FPGA片内FIFO(First Input First Output,即先进先出存储器)作为ARM处理器与FPGA之间的高速通信桥梁,针对Linux 2.6.36内核完成了对FPGA设备的驱动设计,并基于Qt图形用户界面实现了影像的实时显示。测试结果表明,ARM处理器与FPGA之间能够实现VGA(640×480)图像的高速交互,帧率可达26帧/s,最大传输带宽为182Mbps。该系统不仅体积小、功耗低、成本低,而且稳定性好、功能强,能够满足航空遥感摄影系统的实时性要求。     

用FPGA实现SOC技术宽间隔跳频发射系统的研究

使用VerilogHDL硬件描述语言在现场可编程门阵列(FPGA)上成功地实现基带与调制的片上系统(SOC)，该系统与MC145152频率合成器相连接，组成完整的跳频发射实验系统。对其进行了介绍，指明该系统经过测试，工作正常。     

Realization of a Motion Control IC for $X{-}Y$ Table Based on Novel FPGA Technology

The novel field-programmable-gate-array (FPGA) technology is able to combine an embedded processor and an application intellectual property to be a system-on-a-programmable-chip developing environment. Therefore, this paper presents a motion control IC for the X-Y table under this novel FPGA technology. The proposed motion control IC has two modules. One module performs the functions of the motion trajectory and two position/speed controllers for the X-Y table. The other module performs the functions of two current vector controllers of permanent-magnet synchronous motor drives. The former is implemented by software using a Nios II embedded processor due to the complicated control algorithm and low-sampling-frequency control (motion trajectory and position control: less than 1 kHz). The latter is implemented by hardware in the FPGA owing to the requirements of high-sampling-frequency control (current loop: 16 kHz; PWM circuit: 4-8 MHz) but simple computation. As a result, the hardware/software codesign technology can make the motion controller of the X-Y table more compact, flexible, perform better, and less costly.     

高分辨率SAR实时信号处理

介绍了高分辨率合成孔径雷达实时信号处理机硬件结构和实时信号处理算法及流程。该信号处理机的核心是G4模块，包含4个矢量处理芯片MPC7410，G4模块具有存储容量大和运算速度快的特点。算法上采用工程上较易实现的R-D算法及对比度最优自聚焦算法。利用机载SAR试飞数据验证，得到了高分辨率SAR图像，证明信号处理机稳定有效可靠。     

基于FPGA的航空总线协议接口设计

MIL-STD-1553B是一种应用广泛的航空总线协议,针对总线协议控制器基本依赖于进口专用器件现状,提出了以Xilinx公司Virtex-Ⅱ ProFPGA为核心实现航空总线协议接口的系统设计方案。采用SoPC技术,将PowerPC405硬核处理器与总线接口逻辑集成在一片FPGA上,从而使系统集成度高、扩展性强。通过测试表明,系统工作稳定可靠,满足1553B总线协议标准。     

基于FPGA多功能奶瓶的设计

为了设计一种能够迅速检测奶粉中三聚氰胺、控制水温、快速散热等智能化的婴幼儿奶瓶。该设计以FPGA作为核心处理器,设计出了硬件控制系统的电路,在QuartusⅡ和NiosⅡ开发环境下采用SOPC技术的C语言编写软核程序,VHDL编写了硬件模块,获得了预期的效果。     

Efficient Communication Between the Embedded Processor and the Reconfigurable Logic on an FPGA

Increasing device densities have prompted FPGA manufacturers, such as Xilinx and Altera, to incorporate larger embedded components, including multipliers, DSP blocks and even embedded processors. One of the recent architectural enhancements in the Xilinx Virtex family architecture is the introduction of the PowerPC405 hard-core embedded processor. In this paper we present a Software Defined Radio application that serves as a vehicle for investigating effective communication between the PowerPC405 processor and the surrounding FPGA fabric.