A High Linearity, Fast-Locking Pulsewidth Control Loop With Digitally Programmable Duty Cycle Correction for Wide Range Operation

A high linearity pulsewidth control loop (PWCL) is proposed in this paper. Using the linear control stage (CS) and digital-controlled charge pump (DCCP), the proposed PWCL can be operated within a wide-range of both input and output duty cycles over a wide frequency range. A simple detection circuit is utilized to control the DCCP in a complementary architecture such that the proposed PWCL can reduce the locking time ratio to 4.5. The test chip is fabricated using 0.18 mum CMOS process. The measurement results show that the frequency range of the input signal was 1 MHz to 1.3 GHz, the duty cycle range of the input signal is from 30% to 70% and the programmable duty cycle of the output signal is from 30% to 70% in steps of 5%. The measurement power dissipation and the peak-to-peak jitter are 4.8 mW and 13.2 ps, respectively, at an operating frequency of 1.3 GHz.     

A 500-MHz-1.25-GHz fast-locking pulsewidth control loop with presettable duty cycle

A 500-MHz-1.25-GHz fast-locking pulsewidth control loop (PWCL) with presettable duty cycle is realized in 0.35-/spl mu/m CMOS technology. The proposed voltage-difference-to-digital converter and switched charge pump circuits reduce the lock time of a conventional PWCL. Compared with the conventional PWCL, the proposed circuit can reduce the lock time by a factor of 2.58. A method to preset the duty cycle of the output clock is also described. Circuit measurements verify that the duty cycle of the output clock can be adjusted from 35% to 70% in steps of 5%.     

Design of high-frequency wide-range all digital phase locked loop in 90 nm CMOS

This paper presents a high-frequency wide tuning range all digital phase locked loop (ADPLL) designed using a 90 nm CMOS process with 1.2 V power supply. It operates in the frequency range of 1.9–7.8 GHz. The ADPLL uses a wide frequency range digital controlled oscillator (DCO) and a two stage acquisition process to obtain the fast lock time. The operation of the ADPLL includes both a frequency acquisition state and a phase acquisition state. A novel architecture is implemented which includes a coarse acquisition stage to obtain a monotonically increasing wide frequency range DCO for frequency acquisition and a fine control stage to achieve resolution of 18.75 kHz for phase tracking. Design considerations of the ADPLL circuit components and implementation using Cadence tools are presented. Spectre simulations demonstrate a peak-to-peak jitter value of <15 ps and a root mean square jitter value of 4 ps when locked at 5.12 GHz. The power consumption at 7.8 GHz is 8 mW and the frequency hopping time is 3.5 μs for a 3.2 GHz frequency change. Spectre simulations demonstrate ADPLL convergence to 5.12 GHz for the typical, fast, and slow process corners to support robust performance considering process variations.     

一种4路正交时钟校准电路的设计

采用TSMC 40 nm CMOS工艺,设计了一种正交时钟校准电路,它包含2个脉冲宽度调整环路和1个内嵌的延迟锁相环。与其他校准电路相比,本文校准电路无需50%占空比的参考时钟或者单端转差分(STC)电路,就能获得4路占空比为50%的时钟,还能调整时钟的相对相位以输出4路正交时钟。当工作频率为3.125 GHz时,该校准电路能将占空比为10%~90%的输入时钟自动调整至占空比为50%±0.2%的时钟,相位调整范围为58°~122°,电路功耗为2.2 mW,可应用于RapidIO物理层接收机电路中。     

All digital fast lock DLL-based frequency multiplier

One of the most important parameters in the design of synthesizers is lock time. A new fast lock delay locked loop (DLL) based frequency multiplier is proposed in this paper. Phase detector, charge pump and loop filter in conventional DLLs are replaced by a digital signal processor in the proposed structure. This leads to have better lock time, higher speed and smaller chip aria. The proposed structure can be implemented easily in a real system by means of a suitable powerful digital signal processor. Simulation has been done for 11 delay cells as a delay chain and input frequency equal with 300 MHz. The output frequency is multiplied by 11 (f_OUT = 3.3 GHz), and lock time is obtained about 13 ns which is equal to 4 clock cycles of reference clock.     

A 2.4-GHz frequency synthesizer based on process and temperature compensated ring ILFD

In this paper, a 2.4-GHz frequency synthesizer incorporating a ring-oscillator based process and temperature compensated injection-locked frequency divider (ILFD) is proposed. The synthesizer is implemented in a 0.18-μm standard complementary metal-oxide semiconductor process with a chip area of 3 mm × 3 mm plus the off-chip capacitors for loop filter. With an LC oscillator, the output frequency can be tuned from 2.057 to 2.652 GHz, while the settling time is around 36 μs with a loop bandwidth of 60 kHz. Measurements are performed across six different chips to study the circuit performance due to process variation. The worst-case total power consumption is measured to be 2.2 mW with a power supply of 1.8 V. The ILFD block is also tested separately and the test results show a wide locking range of 1.4 GHz over all the process corners and a temperature range from 0 to 80 °C.     

Frequency multiplier using pulse-width control loop

A frequency multiplier circuit based on a well-known pulse-width control loop is presented. The proposed circuit can be used to enhance the output frequency range of a phase-locked loop (PLL) by using multiple phases of the voltage-controlled oscillator. It can be used for enhancing the output frequency range of new as well as existing PLL designs with minimum impact on PLL loop dynamics. The circuit is generic in nature and can be used with any multi-phase oscillator type. The circuit is designed in 65 nm complimentary metal oxide semiconductor (CMOS) technology and has been simulated across process, voltage and temperature (PVT) corners with temperature variation from ?40°C to 125°C, analogue supply voltage variation from 1.62 V to 1.98 V, and digital supply voltage variation from 1.1 V to 1.3 V.     

A wide frequency range delay line for fast-locking and low power delay-locked-loops

A voltage controlled delay cell with wide frequency range is presented in this paper. The delay-line which is resulted by connecting five series of delay cells generating a wide range of delay from 1.9 to 13.24 ns. It can be used in an analog delay locked loop. The linear characteristic of the circuit with respect to the conventional delay line structures is improved, and a better performance of noise is obtained using differential structure. This circuit is designed by ADS software and TSMC CMOS 0.18 μm technology, with supply voltage 1.8 V. By changing control voltage from 0.335 to 1.8 V in delay line, a wide range of frequency from 75.52 to 917.43 MHz will be covered. Simulation results show that the proposed delay line has power consumption of maximum 3.77 mW at frequency of 75.52 MHz. It also shows that increasing of frequency will reduce power dissipation which is the one of the main characteristics of this novel circuit. Moreover, the delay locked loop which uses these delay cells has a very high lock speed so that the maximum lock time in just five clock cycles.     

A technique to improve the linearization of frequency–voltage characteristic of LC-VCO

This paper presents a very low-power linearization technique to improve the linearity of frequency-voltage characteristic of LC-VCO (voltage controlled oscillator) using MOS varactor. This reduces the VCO gain (K _VCO) variation and its required value over the tuning voltage range. Low K _VCO improves noise and reference spur performances at the output of phase lock loop/frequency synthesizer (FS). Low K _VCO variation reduces FS loop stability problem. Using this VCO circuit, a fully on-chip integer-N frequency synthesizer has been fabricated in 0.18 μm epi-digital CMOS technology for 2.45 GHz ZigBee application. The measured VCO phase noise is ?115.76 and ?125.23 dBc/Hz at 1 and 3 MHz offset frequencies, respectively from 2.445 GHz carrier and the reference spur of the frequency synthesizer is ?68.62 dBc. The used supply voltage is 1.5 V.     

All-digital delay-locked loop/pulsewidth-control loop with adjustable duty cycles

An all-digital delay-locked loop (DLL) and an all-digital pulsewidth-control loop (PWCL) with adjustable duty cycles are presented. For the DLL, by using the flash time-to-digital conversion, both the phase alignment and the duty cycle of the output clock are assured in 10 cycles. For the PWCL, the sequential time-to-digital conversion is adopted to reduce the required D-flip-flops and lock within 28 cycles. For both of the proposed circuits, the requirement of the input clock with 50% duty cycle is eliminated. The proposed circuits have been fabricated in a 0.35-/spl mu/m CMOS process. The proposed DLL generates the output clock with the duty cycle of 25%, 50% and 75%, and the operation frequency range is from 140 to 260 MHz. For the proposed PWCL, the duty cycle is adjusted from 30% to 70% in steps of 10%. The operation frequency range is from 400 to 600 MHz.     

A modified closed-loop auto frequency calibration technique for a 1.571-GHz integer-N PLL

In this paper, a modified closed-loop auto frequency calibration technique (MCL-AFC) is adopted in an integer-N phase-locked loop (PLL) for GPS-L1 application. The ignorance of circuit initial conditions setting in the closed-loop AFC may cause the start-up trap and long frequency calibration time. To solve these problems, the MCL-AFC technique is introduced. The process of MCL-AFC is listed below: first, initialisation process is only used for start-up of PLL; second, closed-loop voltage comparison process and open-loop switching process will take place alternately until optimum frequency control words are obtained. Tuning voltage searching range is reduced by half during the voltage comparison process since VCO’s tuning voltage is set to half of supply voltage through switching process. The MCL-AFC circuit is implemented in a 1-poly 6-metal 180 nm CMOS process and its chip area is 0.0167 mm². The measured locked output frequency of the PLL is 1.571 GHz and the out-band phase noise is ?131.9dBc/Hz at 1 MHz. The calibration time of PLL with MCL-AFC circuit is reduced to only 5µs while whole locking time is about 10.2µs.     

一种宽频率范围电荷泵锁相环快速锁定方法

以一种适用于现场可编程门阵列(FPGA)芯片的宽频率范围电荷泵锁相环(CPPLL)为例,介绍了一种通过添加简单辅助电路来减小锁相环(PLL)上电锁定时间的方法.该方法在传统电荷泵锁相环的基础上添加了预充电电路,可以大大减少压控振荡器控制电压(VCIRL)拉升的时间.除此之外还添加了频率比较电路,将较宽的频率范围分成若干...     

Pulsewidth control loop with a frequency detector for wide frequency range operation

A pulsewidth control loop (PWCL) with a frequency detector for wide frequency range operation is presented. The proposed PWCL is implemented with a duty cycle controlled circuit and frequency detector to correct the wide range frequency and duty cycle of the input clock. The duty cycle controlled circuit is able to modify the gain with different frequency and duty cycle ranges. The frequency and duty cycle of the input clock are detected by the frequency detector. The frequency detector is based on a ring oscillator and the input clock duty cycle and frequency are detected within two input clock cycles. The proposed circuit has been fabricated in a 0.35 μm CMOS technology. The proposed circuit generates the output clock of 50% duty cycle with the input range from 20% to 80% and frequency range 50–800 MHz. The measured duty cycle error is less than 1% within the frequency range from 50 MHz to 800 MHz.     

Design and implementation of differential pulsewidth control loop for GHz VLSI systems

A novel differential pulsewidth control loop (PWCL) is proposed, in which a balanced charge pump is employed so that the PWCL does not require a 50% duty cycle reference clock. A test chip is realised in a 0.35 /spl mu/m CMOS process, and the measured results show that the tuning range for the duty cycle of the input clock is from 27 to 71% at 1 GHz operating frequency.     

A New Transmission Gate Cascode Current Mirror Charge Pump for Fast Locking Low Noise PLL

Charge Pump in a phase locked loop (PLL) generates non-ideal effects such as current mismatches at the output node and switching errors at the pull up and pull down networks. This work presents a novel transmission gate cascode current mirror charge pump circuit. The switches incorporated in this work are Transmission Gates which help to reduce various switching errors, and only one supply independent reference current source is used to have a minimum current mismatch. The performance analysis carried out in the Cadence design environment, and it is observed that the loop locks in 25 ns which is 50 % faster than the conventional charge pump. The control voltage absolutely has no ripple in it after locking which reduces the reference spur further. It could be achieved because the current mismatch is only about 7 %. This PLL operates at 2.5 GHz having a wide lock range of 0.5–2.8 GHz where average power consumption is 1.74 mW. Due to the use of cascade current mirror circuits, the output voltage swing that can be obtained is 1.79 V.     

Wide tuning-range CMOS VCO based on a tunable active inductor

In this paper, a wide tuning-range CMOS voltage-controlled oscillator (VCO) with high output power using an active inductor circuit is presented. In this VCO design, the coarse frequency is achieved by tuning the integrated active inductor. The circuit has been simulated using a 0.18-µm CMOS fabrication process and presents output frequency range from 100 MHz to 2.5 GHz, resulting in a tuning range of 96%. The phase noise is –85 dBc/Hz at a 1 MHz frequency offset. The output power is from –3 dBm at 2.55 GHz to +14 dBm at 167 MHz. The active inductor power dissipation is 6.5 mW and the total power consumption is 16.27 mW when operating on a 1.8 V supply voltage. By comparing this active inductor architecture VCO with general VCO topology, the result shows that this topology, which employs the proposed active inductor, produces a better performance.     

一种低功耗时钟源IP的设计

基于SMIC 40 nm CMOS工艺,采用锁相环(PLL)设计了一种低功耗时钟源IP。提出的环路参数校准技术保证PLL在整个输出频率范围内稳定。采用电容倍乘技术减小环路滤波器占用的面积。采用可编程输出分频器拓宽了输出频率范围。后仿结果显示,该时钟源在0.125~3 GHz范围内可调,步长为0.125~1 MHz。环路参数校准后,PLL的带宽稳定在80 kHz,相位裕度稳定在48°。电路的供电电压为1.1 V,功耗小于3 mW,核心面积为0.096 mm²。     

A wide-range all digital DLL for multiphase clock generation

This paper presents a wide-range all digital delay-locked loop (DLL) for multiphase clock generation. Using the phase compensation circuit (PCC), the large phase difference is compensated in the initial step. Thus, the proposed solution can overcome the false-lock problem in conventional designs, and keeps the same benefits of conventional DLLs such as good jitter performance and multiphase clock generation. Furthermore, the proposed all digital multiphase clock generator has wide ranges and is not related to specific process. Thus, it can reduce the design time and design complexity in many different applications. The DLL is implemented in a 0.13 μm CMOS process. The experimental results show that the proposal has a wide frequency range. The peak-to-peak jitter is less than 7.7 ps over the operating frequency range of 200 MHz-1 GHz and the power consumption is 4.8 mW at 1 GHz. The maximum lock time is 20 clock cycles.     

Design of a W-band Frequency Tripler for Broadband Operation Based on a Modified Equivalent Circuit Model of GaAs Schottky Varistor Diode

This paper presents the design and experimental results of a W-band frequency tripler with commercially available planar Schottky varistor diodes DBES105a fabricated by UMS, Inc. The frequency tripler features the characteristics of tunerless, passive, low conversion loss, broadband and compact. Considering actual circuit structure, especially the effect of ambient channel around the diode at millimeter wavelength, a modified equivalent circuit model for the Schottky diode is developed. The accuracy of the magnitude and phase of S21 of the proposed equivalent circuit model is improved by this modification. Input and output embedding circuits are designed and optimized according to the corresponding embedding impedances of the modified circuit model of the diode. The circuit of the frequency tripler is fabricated on RT/Rogers 5880 substrate with thickness of 0.127 mm. Measured conversion loss of the frequency tripler is 14.5 dB with variation of ±1 dB across the 75?~?103 GHz band and 15.5?~?19 dB over the frequency range of 103?~?110 GHz when driven with an input power of 18 dBm. A recorded maximum output power of 6.8 dBm is achieved at 94 GHz at room temperature. The minimum harmonics suppression is greater than 12dBc over 75?~?110 GHz band.     

Low-voltage pulsewidth control loops for SOC applications

The proposed pulsewidth control loop (PWCL) adopts the same architecture as the conventional PWCL, but with a new duty-cycle detector and a new pulse generator. Using the new building block circuits, the clock frequency can be increased tremendously, and the output of the PWCL has fixed rising edge, which will not disturb the phase-locking result by a preceding phase-locked loop (PLL) or delay-locked loop (DLL). This means that the clock buffer can include a PLL/DLL and a PWCL to perform phase locking as well as pulsewidth adjustment simultaneously. All the building blocks used in the new PWCL have simple circuit structures that are suitable for low-voltage operation. A test chip is implemented in a 0.35-/spl mu/m CMOS process with only 1.8-V V/sub DD/ successfully generates a clock signal with a 0.6-ns pulsewidth for a heavily pipelined multiplier to operate at 400 MHz. The features of operating at low voltage, providing variable duty cycle, and being able to cooperate with PLL/DLL make the new PWCL suitable for system-on-chip (SOC) applications.