A time-domain full-wave extraction method of frequency-dependentequivalent circuit parameters of multiconductor interconnection lines

A time-domain full-wave method for the extraction of frequency-dependent equivalent circuit parameters of multiconductor interconnection lines is presented in this paper. The circuit parameters extracted by this method can be inserted into circuit simulation software to investigate time-domain responses of a high-speed IC system with multiconductor interconnects. Because the definitions of the voltage and the current are not unique in full-wave analysis, transformation among circuit parameters according to different definitions of the voltage and current is also presented. The method is based on the finite-difference time-domain (FDTD) method, and the reliability of this method is illustrated by its application to representative problems     

Statistical RTS model for digital circuits

In this work we study the variation in drain current of MOS transistors due to the capture and emission of electrons at interface states (traps), called random telegraph signal (RTS). Usually, RTS is studied in frequency domain. However, for digital circuits, it is more appropriate to use time-domain representations.The time-domain representation here proposed models the effect of RTS on I_ds as instantaneous Vt shifts. We introduce a statistical numerical approach for computing the total ΔVt of the transistor considering all the traps in the interface. The method analyses the effect of non-uniform charge densities along the channel. To show the applicability of the methodology to circuit analysis on the electrical level, the model is applied to characterize read and write instability failures caused by RTS on a 6T-SRAM cell.     

A novel mixed-mode OTA-C universal filter

A novel mixed-mode biquad circuit is presented. The circuit uses six single-output- and one dual-output-operational transconductance amplifiers, two grounded capacitors; and can realize lowpass, highpass, bandpass, notch, lowpass-notch, highpass-notch and allpass responses from the same topology. The circuit can be driven by voltage or current and its output can be voltage or current. The parameters ω_o and ω_o/Q _o enjoy independent electronic tunability. Simulation results are included.     

Ultra wideband filter using dumbbell-etched stepped impedance resonator

In this article, an ultra wideband bandpass filter using the dumbbell-etched stepped impedance resonator (SIR) is presented. The filter consists of a dumbbell-etched SIR with an impedance ratio K?>?1 and the enhanced coupled input/output lines. The SIR is folded into a dumbbell shape to achieve a smaller circuit size than the filter with conventional SIR. The bandwidth can be analysed using the image-parameter method to obtain the proper dimension of the coupled lines and verified using electromagnetic simulation. The measured 3?dB fractional bandwidth of 110% and insertion loss |S ₂₁| less than 3?dB over the entire passband are achieved.     

Novel current-mode biquadratic circuit using only plus type DO-DVCCs and grounded passive components

This paper introduces a novel current-mode biquadratic circuit using plus type differential voltage current conveyors (DVCCs) and grounded passive components. The circuit is constructed with two plus type dual current output DVCCs (DO-DVCCs), two grounded capacitors and two resistors. The circuit can realize multiple circuit transfer functions by choosing the appropriate input and output terminals. Additionally, the circuit parameters Q and ω ₀ can be set orthogonally by adjusting the passive components. The biquadratic circuit enjoys very low sensitivities to the circuit components. An example is given together with simulated results by PSPICE.     

A thermal module design for advanced packaging

A hybrid silicon wafer-scale multi-chip packaging design was chosen as the basis for a high performance, high power dissipation vehicle suitable for VLSI/ULSI applications. The package supports 25 chips (l x l cm), each capable of dissipating as much as 40 W. The heat generated by the chips is removed by water channels in the underlying structure. Deep- (about 1000 μm), and shallow- (about 100 μm. deep), channel designs, with a water flow rate of 499 cc/sec, and 39 cc/sec, respectively, have been analyzed. Both designs are capable of keeping circuit temperature rise small, while maintaining a uniform chip temperature. The temperature distribution of the thermal module was obtained by solving the 2-D heat conduction equation for isolated heat sources (the chips), and heat sinks (the water channels). Assuming that each of the 25 chips dissipates 40 W/cm², and heat is removed only via water flow, the maximum chip tempertaure(t _cc which occurs at the center of a chip) rise relative to inlet water temperature is 11.4° C, and 19.0° C for the deep, and shallow designs, respectively. The maximumt _cc variation between chips on the module (the same as the water temperature rise), for the cases analyzed, is 0.5° C for the deep-channel design, and 6° C for the shallow-channel design (calculated at 25° C inlet water temperature, and an optimum flow rate). For the extremely-uneven powered case (all chips except one at the inlet end are powered at 40 W/chip), the maximum temperature increases between inlet water temperature and chip temperature,t _cc , remain relatively the same, but the maximumt _cc variations between chips on the module increase to 11.4° C, and 19° C for the deep, and shallow designs, respectively, as might be expected. The temperature variation on a powered chip is less than 3° C for both the deep- and shallow-channel designs.     

Threshold-Volgage control schemes through substrate-bias for low-power high-speed CMOS LSI design

Lowering supply voltage,V _DD, is the most effective means to reduce power dissipation of CMOS LSI design. In lowV _DD, however, circuit delay increases and chip performance degrades. There are two means to maintain the chip performance: 1) to lower the threshold voltage,V _th, to recover circuit speed, or 2) to introduce parallel and/or pipeline architectures to make up for slow device speed. The first approach increases standby power dissipation due to lowV _th, while the second approach degrades worst case circuit speed caused byV _th fluctuation in lowV _DD. This paper presents two circuit techniques to solve these problems, in both of whichV _th is controlled through substrate bias. A Standby Power Reduction (SPR) scheme raisesV _th in a standby mode by applying substrate bias with a voltage-switch circuit. A Self-Adjusting Threshold-Voltage (SAT) scheme reducesV _th fluctuation in an active mode by adjusting substrate bias with a feed-back control circuit. Test chips are fabricated and effectiveness of the circuit techniques is examined. The SPR scheme reduces 50% of the active power dissipation while maintaining the speed and the standby power dissipation. The SAT scheme improves worst case circuit speed by a factor of 3 under a 1 VV _DD.     

A novel mixed-mode current-conveyor-based filter

A new mixed-mode biquad circuit is presented. The circuit uses six single-output plus-type second-generation current-conveyors (CCII+s), a single dual-output CCII+, two grounded capacitors, eight resistors, at least two of them permanently grounded, and can realize lowpass, highpass, bandpass, notch, lowpass notch, highpass notch and allpass responses from the same topology. The circuit can be driven by voltage or current and its output can be voltage or current. The parameters ω₀ and ω₀/Q ₀ enjoy independent electronic tunability. Simulation results are included.     

An efficient crosstalk parameter extraction method for high-speedinterconnection lines

A proposal is presented for an effective extraction method for crosstalk model parameters of high-speed interconnection lines. In the extraction procedure, mutual capacitance and mutual inductance of the coupled interconnection lines are extracted based on S-parameter measurement, time-domain-reflectometry (TDR) measurement and subsequent microwave network analysis. The extraction method is useful for characterizing homogeneous guiding structures, where the propagation of coupled transverse electromagnetic (TEM) modes is supported. In contrast to previous extraction methods, the suggested procedure requires fewer on-wafer probing steps and does not need matched terminations in the test device for high-frequency probing. The extracted models can be readily used with simulation program with integrated circuit emphasis (SPICE) circuit simulation. The procedure can also be used for modeling the crosstalk in packaging structures and multichip modules (MCMs). The proposed procedure has been successfully applied to the crosstalk model extraction of on-chip interconnection lines. Crosstalk model parameters were obtained for different line structures, spaces, and widths. Finally, the validity and reliability of the extracted models were examined by comparing a SPICE circuit simulation using the extracted crosstalk model parameters with high-speed time-domain crosstalk measurement. A close agreement was observed in the amplitude and pulse shape between the simulation and the measurement, showing the accuracy and usefulness of the proposed extraction method     

Versatile current-mode biquadratic circuit using only plus type CCCIIs and grounded capacitors

This paper introduces a versatile current-mode biquadratic circuit using second generation current-controlled current conveyors (CCCIIs). The circuit is constructed with two plus type multiple current output CCCIIs (MO-CCCIIs) and two grounded capacitors. The circuit can realize low-pass, band-pass, high-pass, band-stop and all-pass transfer functions by choosing appropriate input and output terminals without any component matching conditions. Additionally, the circuit parameters Q and ω₀ can be set orthogonally by adjusting the bias currents of the MO-CCCIIs and grounded capacitors. The biquadratic circuit enjoys very low sensitivities to the circuit components.

Some examples are given together with simulated results by PSPICE.     

Determination of the parameters of deep levels from the relaxational delay of breakdown of a p-n junction

A technique for determining the deep-center parameters from the relaxational delay of avalanche breakdown of a p-n junction is investigated. The method implemented does not impose any restrictions on the relation between the concentration of the deep centers and that of the dopant impurities and can be used in those cases when the current-voltage characteristic of the sample is poorly monitored or the equivalent circuit of the p-n junction is complex. This may be a consequence of strongly compensated base regions, the presence of high-resistance layers, or imperfect ohmic contacts. Possibilities of the method are illustrated by the example of determining the parameters of the gold acceptor level in p ⁺-n-n ⁺ structures with high gold content (N _Au =0.9N _d ). Fiz. Tekh. Poluprovodn. 33, 494–498 (April 1999)     

A simplified synthesis of transmission lines with a tree structure

The limiting factor for high-performance systems is being set by interconnection delay rather than transistor switching speed. The advances in circuits speed and density are placing increasing demands on the performance of interconnections, for example chip-to-chip interconnection on multichip modules. To address this extremely important and timely research area, we analyze in this paper the circuit property of a generic distributedRLC tree which models interconnections in high-speed IC chips. The presented result can be used to calculate the waveform and delay in anRLC tree. The result on theRLC tree is then extended to the case of a tree consisting of transmission lines. Based on an analytical approach a two-pole circuit approximation is presented to provide a closed form solution. The approximation reveals the relationship between circuit performance and the design parameters which is essential to IC layout designs. A simplified formula is derived to evaluate the performance of VLSI layout.     

Realization of Tunable Pole-Q Current-Mode OTA-C Universal Filter

A realization of a current-mode operational transconductance amplifier-capacitor (OTA-C) universal filter with tunable pole-Q is proposed. A biquadratic band-reject function is used as the initial synthesis function based on three integrator blocks. Consequently, the proposed filter uses a total of three multiple-output OTAs and three grounded capacitors. Five types of transfer functions, namely, low-pass, high-pass, band-pass, band-reject, and all-pass responses, can be obtained without changing the circuit topology. The pole-Q (Q ₀) and the pole-frequency (ω ₀) parameters are independently tuned. The Q ₀ and ω ₀ parameters are electronically tuned by adjusting the transconductance gains of the OTAs. Furthermore, Q ₀ can be tuned by varying the capacitor manually without affecting ω ₀. SPICE simulation results of the proposed filter are presented.     

Efficient sensitivity analysis of transmission-line networks usingmodel-reduction techniques

An efficient algorithm, based on congruent transformation and model reduction, is proposed for evaluation of frequency- and time-domain sensitivity of large linear networks containing lossy coupled transmission lines. The sensitivity of the voltage and current waveforms can be calculated with respect to lumped components and parameters of transmission lines. The algorithm is based on projecting the adjoint network equations on a reduced-order subspace that preserves the circuit moments. The proposed algorithm provides a significant decrease in the computational expense for sensitivity analysis     

Accurate closed-form formulas for the electromagnetic parameters of squared coaxial lines

This article presents a set of accurate closed-form formulas for the electromagnetic parameters (inductance (L), capacitance (C) and characteristic impedance (Z_c)) for squared coaxial lines with circular and square inner conductor. The analytical expressions, deduced from rigorous analysis by the finite element method (FEM), method of moments (MoM) and curves fitting techniques, can be easily implemented in CAD simulation tools, to design components for wireless communication. This study presents accurate and suitable general expressions for all squared coaxial lines with a wide range of outer to inner conductors ratio between 1.2 and 10. As an application, we present the design of 60 GHz branch line couplers.     

An analysis method for high-speed circuit systems

A new method for analyzing high-speed circuit systems is presented. The method adds transmission line end currents to the circuit variables of the classical modified nodal approach. Then the matrix equation describing high-speed circuit system can be formulated directly and analyzed conveniently for its normative form. A time-domain analysis method for transmission lines is also introduced. The two methods are combined together to efficiently analyze high-speed circuit systems having general transmission lines. Numerical experiment is presented and the results are compared with that calculated by Hspice.     

Adaptive neuro-fuzzy inference system for gap discontinuities in coplanar waveguides

A new approach based on an adaptive neuro-fuzzy inference system (ANFIS) is presented for gap discontinuities in coplanar waveguides (CPWs). The proposed ANFIS model combines the neural network adaptive capabilities and the fuzzy qualitative approach. The ANFIS is presented so as to produce a good approximation to the nonlinear relationship between the geometrical parameters and the frequency-dependent equivalent circuit parameter (the S ₂₁ parameter of the gap). The ANFIS results for the S ₂₁ parameters are compared with the results available in the literature obtained by using the conformal-mapping technique (CMT), and the results confirm that the proposed ANFIS model can provide an accurate computation of the S ₂₁ parameters of the gaps in CPWs.     

Transient power supply current monitoring—A new test method for CMOS VLSI circuits

We present a new method for testing digital CMOS integrated circuits. The new method is based on the following premise: monitor the switching behavior of a circuit as opposed to the output logic state. We use the transient power supply current as a window of observability into the circuit switching behavior. A method for isolating normal switching transients from those which result from defects is introduced. The feasibility of this new testing approach is investigated by conducting several experiments involving the design of integrated circuits with built-in defects, fabrication, and physical testing. The results of these experiments show this new test method to be a promising one for detecting defects that can escape stuck-at testing andI _DDQ testing.     

Self‐Limited Switching in Ta2O5/TaOx Memristors Exhibiting Uniform Multilevel Changes in Resistance

To facilitate the development of memristive devices, it is essential to resolve the problem of non‐uniformity in switching, which is caused by the random nature of the filamentary switching mechanism in many resistance switching memories based on transition metal oxide. In addition, device parameters such as low‐ and high‐state resistance should be regulated as desired. These issues can be overcome if memristive devices have switching limits for both the low‐ and high‐resistance states and if their resistance values are highly controllable. In this study, a method termed self‐limited switching for uniformly regulating the values of both the low‐ and high‐resistance states is suggested, and the circuit configuration required for the self‐limited switching is established in a Ta₂O₅/TaO_x memristive structure. A method of improving the uniformity of multi‐level resistance states in this memristive system is also proposed.