SPICE compatible modelling of on-chip coupled interconnects

On-chip coupled interconnect lines are modelled using measured S-parameters. The physical consistency between single and coupled line model parameters are maintained in the proposed methodology. The SPICE compatible model is validated in both the frequency and the time domain using copper and ultra low-kappa coupled interconnects.     

Efficient timing modelling of coupled inductance dominant RLC interconnects

An efficient timing modelling scheme for coupled inductance dominant resistance inductance capacitance (RLC) interconnects is presented. The transfer function in the Laplace domain is expanded in a series of rational, polynomial and exponential products, the time-domain responses of which can be computed analytically. The resulting time-domain response has fast convergence yet maintains high fidelity of non-monotonic characteristics of RLC transmission line circuits. By using an analytical decoupling technique, an efficient analytical timing model for coupled inductance dominant RLC interconnects is constructed.     

Bus encoder design for reduced crosstalk,power and area in coupled VLSI interconnects

This research work presents a novel circuit for simultaneous reduction of power, crosstalk and area using bus encoding technique in RC modeled VLSI interconnect. Bus-invert method is used to reduce inter-wire coupling, which is actually responsible for crosstalk, delay and power dissipation in coupled interconnects. The proposed method focuses on simplified and improved encoder circuit for 4, 8 and 16 coupled lines. In past, the researchers developed encoders that usually focused on minimizing power dissipation and/or crosstalk, thereby paying heavy penalty in terms of chip area. However, the proposed encoder and decoder while significantly reducing crosstalk demonstrates an overall reduction of power dissipation by 68.76% through drastically limiting switching activity. Furthermore, while reducing the complexity, chip area and transistor count of the circuit is reduced by more than 57%.     

S-parameter-measurement-based high-speed signal transientcharacterization of VLSI interconnects on SiO2-Si substrate

A new S-parameter-based signal transient characterization method for very large scale integrated (VLSI) interconnects is presented. The technique can provide very accurate signal integrity verification of an integrated circuit (IC) interconnect line since its S-parameters are composed of all the frequency-variant transmission line characteristics over a broad frequency band. In order to demonstrate the technique, test patterns are designed and fabricated by using a 0.35 μm complementary metal-oxide-semiconductor (CMOS) process. The time-domain signal transient characteristics for the test patterns are then examined by using the S-parameters over a 50 MHz to 20 GHz frequency range. The signal delay and the waveform distortion presented in the interconnect lines based on the proposed method are compared with the existing interconnect models. Using the experimental characterizations of the test patterns, it is shown that the silicon substrate effect and frequency-variant transmission line characteristics of IC interconnects can be very crucial     

Simulation of high-speed interconnects

With the rapid developments in very large-scale integration (VLSI) technology, design and computer-aided design (CAD) techniques, at both the chip and package level, the operating frequencies are fast reaching the vicinity of gigahertz and switching times are getting to the subnanosecond levels. The ever increasing quest for high-speed applications is placing higher demands on interconnect performance and highlighted the previously negligible effects of interconnects such as ringing, signal delay, distortion, reflections, and crosstalk. In this review paper various high-speed interconnect effects are briefly discussed. In addition, recent advances in transmission line macromodeling techniques are presented. Also, simulation of high-speed interconnects using model-reduction-based algorithms is discussed in detail     

蝶形微带天线的全波分析与宽带设计

介绍了蝶形微带贴片天线的一种全波分析方法－矩量法,与多端网络法相比,其适应范围更广。然后介绍了展宽天线频带的一种设计方法。通过不对称馈电方式,激励起两个相近频率的模式,从而使微带天线驻波比带宽获得明显展宽。测试结果与计算结果相当吻合,证实了数值分析与设计方法的有效性。     

Isolation effects in single- and dual-plane VLSI interconnects

The issue of interline coupling in high-speed VLSI interconnects is addressed. A full-wave-based technique is used to numerically solve for the modes and hence the line voltages and currents for multiconductor microstrip. The accuracy of these results is compared with time-domain experimental data. Isolation lines placed between signal lines and grounded at both ends are considered as a means of significantly reducing crosstalk. It is shown that the performance of such lines depends on several factors such as relative mode velocities, signal rise and fall times, and line length. These points are illuminated by considering the effects of isolation lines in two geometries of interest in high-speed integrated circuits. On the basis of these results one can determine the usefulness of isolation lines for a given geometry     

Shape effect on electromigration in VLSI interconnects

The influence of the shape of VLSI interconnects on the lifetime due to electromigration is investigated. Simulations and experiments indicate that, in some cases, the right angle corners of the metal lines, widely interconnections layout of VLSI circuits, reduce the lifetime of such interconnects. Substitutions by more gradual, smaller angled corners improve electromigration lifetimes.     

The analytical model for crosstalk noise of current-mode signaling in coupled RLC interconnects of VLSI circuits

With the continuous advancement of semiconductor technology,the interconnects crosstalk has had a great influence on the performances of VLSI circuits.To date,most of the research about the interconnects of VLSI circuits focus on the voltage-mode signaling (VMS) scheme while the current-mode signaling (CMS) scheme is rarely analyzed.First of all,an equivalent circuit model of two-line coupled interconnects is presented in this paper, which is applicable to both the CMS and VMS schemes.The coupling capacitive and mutual inductive are taken into account in the equivalent circuit model.Secondly,the output noise of CMS and VMS schemes are investigated in the paper according to the decoupling technique andABCD parameter matrix approach at local level,intermediate level and global level,respectively.Moreover,the experimental results show that the CMS interconnects have lesser noise peak,noise width and noise amplitude than the VMS interconnects in the same cases,and the CMS scheme is especially suitable for the global interconnects communication of VLSI circuits.It is found that the results obtained by ABCD parameter matrix approach are in good accordance with the simulation results of the advanced design system.     

High-speed and low-power repeater for VLSI interconnects

This paper proposes a repeater for boosting the speed of interconnects with low power dissipation. We have designed and implemented at 45 and 32 nm technology nodes. Delay and power dissipation performances are analyzed for various voltage levels at these technology nodes using Spice simulations. A significant reduction in delay and power dissipation are observed compared to a conventional repeater. The results show that the proposed high-speed low-power repeater has a reduced delay for higher load capacitance. The proposed repeater is also compared with LPTG CMOS repeater, and the results shows that the proposed repeater has reduced delay. The proposed repeater can be suitable for high-speed global interconnects and has the capacity to drive large loads.     

Analysis of conductor losses in high-speed interconnects

This paper describes the influence of conductor losses on the crosstalk between coupled interconnecting lines using an integral equation method. The method combines a full-wave space domain Green's function in the dielectric regions with a quasi-static Green's function in the conductors. Following this procedure, propagation characteristics are derived in the frequency and time domain and presented for various geometries     

Rapidly annealed Mo-Polycide For VLSI gates and interconnects

In this paper, the results of an investigation on the formation of Mo-polycide by sputtering from a composite target followed by rapid thermal annealing (RTA) is presented. The influences of target stoichiometry and other deposition parameters including cathode power, Ar-pressure, dc bias and substrate temperature were investigated before and after an RTA cycle. The deposition at high substrate temperature resulted in high oxygen content and high film stress. On the other hand, dc bias and Ar pressure have been found to have insignificant effect on film properties. A final MoSi₂ film resistivity of 72 μΩ cm was achieved by sputtering from a MoSi_2.1 target at ambient temperature followed by RTA at 1100° C for 10 s. This RTA cycle was compatible with that required for implant activation and glass reflow. NMOS FETs having Mo-polycide gates were fabricated using RTA to simultaneously activate implanted dopants and to reflow PSG. Excellent I-V characteristics of these devices indicate that no damage to gate oxide was induced by using rapidly annealed Mo-polycide.     

Optimization and scaling of CMOS-bipolar drivers for VLSI interconnects

In this paper, rules are presented for the optimized design of CMOS-bipolar drivers for large capacitive loads typical of VLSI interconnects. Simulations and closed-form solutions show that the n-p-n bipolar transistors have to be operated in the high-level injection mode, and that their sizes have to be tailored to the two-thirds power of the load, and it scales with the two-thirds power of the base width of the n-p-n transistor and with the one-third power of the channel length of the MOS transistor. For comparison, the CMOS cascade with a tailored second stage is shown to have competitive potential at the expense of an area being approximately 2.5 times larger than that of a CMOS-bipolar stage.     

Optimization of throughput performance for low-power VLSI interconnects

The technique of optimal voltage scaling and repeater insertion is analyzed in this paper to reduce power dissipation on global interconnects. An analytical model for the maximum bit-rate of a very large scale integration interconnect with repeaters has been derived and results are compared with HSPICE simulations. The analytical model is also used to study the effects of interconnect length and scaling on throughput. The throughput-per-bit-energy is analyzed to determine an optimum combination of supply voltage and repeaters for a low-power global interconnect with 250 nm /spl times/ 250 nm cross-sectional dimensions implemented with the 180 nm micro-optical silicon system technology node. It is shown that the optimal supply voltage is approximately equal to twice the threshold voltage. A case study illustrates that a combination of 1 V supply along with one repeater per millimeter increases the throughput-per-bit-energy to over three times that of a latency-centric interconnect of 2 V, which results in a 70% reduction in power dissipation without any loss of throughput performance.     

Crosstalk and transient analyses of high-speed interconnects andpackages

A multiconductor interconnect is modeled using resistors and linear-dependent current and voltage sources. The analysis of a high-speed circuit including lossy interconnection buses is then reduced to simulation of the circuit together with the equivalent circuits of the interconnects. The authors present a new method for the crosstalk and transient analysis of lossy interconnects with arbitrary termination circuits. In order to analyze an interconnect containing N signal conductors, they derive closed-form formulas to determine its transfer functions, and they apply the inverse Fourier transform to obtain its time-domain pulse response functions. Two types of equivalent circuit models can be formulated once the pulse response functions of the interconnect are found. The circuit schematics of the models depend on the number of the signal conductors, irrespective of the physical parameters of the interconnect. These models are compatible with standard circuit simulation tools since they consist of linear resistive networks and linear-dependent sources only. Two example circuits are studied to examine the accuracy and efficiency of the method     

Fast and accurate quasi-three-dimensional capacitance determinationof multilayer VLSI interconnects

A new fast and accurate capacitance determination methodology for intricate multilayer VLSI interconnects is presented. Since a multilayer interconnect structure is too complicated to be directly tractable, it is simplified by investigating charge distributions within the system. The quasi-three-dimensional (3-D) capacitances of the structure are then determined by combining a set of solid-ground-based two-dimensional (2-D) capacitances and shielding effects that can be independently calculated from the simplified structure. The shielding effects due to the neighboring lines of a line can be analytically determined from the given layout dimensions. The solid-ground-based 2-D capacitances can also be quickly computed from the simplified structure. Thus, the proposed capacitance determination methodology is much more cost-efficient than conventional 3-D-based methods. It is shown that the calculated quasi-3-D capacitances have excellent agreement with 3-D field-solver-based results within 5% error     

Full-wave modelling of coaxial cables by FDTD technique

Coaxial cables are commonly used in microwave systems but are difficult to model rigorously in the finite-difference time-domain (FDTD) method, particularly with coarse meshes. Various techniques are investigated and the optimum method identified. In addition, attention is paid to strategies for the computation of the characteristic impedance.     

Electromagnetic analysis of multiconductor losses and dispersion in high-speed interconnects

A self-consistent electromagnetic analysis of multiconductor transmission lines is presented for high-speed, high-density MMIC's and VLSI interconnects. In contrast to classical approach, this analysis handles the multiconductor as normal dielectric with high conductivity in electromagnetic simulation. Therefore, dispersion and loss effects can exactly be described in this model. Examples of interconnect circuits with up to four conductors are analyzed for dispersion and frequency-dependent losses. Propagation characteristics of multimode along symmetrical and asymmetrical multiconductor are obtained. Some inherent influences of losses on high-density interconnects and physical dependence of these effects are also discussed.     

A coupled efficient and systematic full-wave time-domain macromodeling and circuit Simulation method for signal integrity analysis of high-speed interconnects

This paper presents an accurate and systematic approach for analysis of the signal integrity of the high-speed interconnects, which couples the full-wave finite difference time domain (FDTD) method with scattering (S) parameter based macromodeling by using rational function approximation and the circuit simulator. Firstly, the full-wave FDTD method is applied to characterize the interconnect subsystems, which is dedicated to extract the S parameters of the subnetwork consisting of interconnects with fairly complex geometry. Once the frequency-domain discrete data of the S parameters of the interconnect subnetwork is constructed, the rational function approximation is carried out to establish the macromodel of the interconnect subnetwork by employing the vector fitting method, which provides a more robust and accurate solution for the overall problem. Finally, the analysis of the signal integrity of the hybrid circuit can be fulfilled by using the S parameters based macromodel synthesis and simulation program with integrated circuits emphasis (SPICE) circuit simulator. Numerical experiments demonstrate that the proposed approach is accurate and efficient to address the hybrid electromagnetic (interconnect part) and circuit problems, in which the electromagnetic field effects are fully considered and the strength of SPICE circuit simulator is also exploited.