An analytical approach to dynamic crosstalk in coupled interconnects

This paper deals with waveform analysis, crosstalk peak and delay estimation of CMOS gate driven capacitively and inductively coupled interconnects. Simultaneously switching inputs for the coupled interconnects are considered. A transmission line-based coupled model of interconnect is used for analysis. Alpha-power Law model of MOS transistor is used to represent the transistors in CMOS driver. Peaks and delays at far-end of victim line are estimated for conditions when the inputs to the two coupled interconnects are switching in-phase and out-of-phase. The comparison of analytically obtained results with SPICE simulations show that the proposed model captures noise peak and their timing; 90% propagation delay; transition time delay and waveform shape with good accuracy, such as not more than 5% error in crosstalk peak estimation.     

FDTD based transition time dependent crosstalk analysis for coupled RLC interconnects

The performance of high density chips operating in the GHz range is mostly affected by on-chip interconnects. The interconnect delay depends on many factors, a few of them are inputs toggling patterns, line ＆ coupling parasitics, input rise/fall time and source/load characteristics. The transition time of the input is of prime importance in high speed circuits. This paper addresses the FDTD based analysis of transition time effects on functional and dynamic crosstalk. The analysis is carried out for equal and unequal transition times of coupled inputs. The analysis of the effects of unequal rise time is equally important because practically, it is quite common to have mismatching in the rise time of the signals transmitting through different length wires. To demonstrate the effects, two distributed RLC lines coupled inductively and capacitively are taken into consideration. The FDTD technique is used because it gives accurate results and carries time domain analysis of coupled lines. The number of lumps in SPICE simulations is considered the same as those of spatial segments. To validate the FDTD computed results, SPICE simulations are run and results are compared. A good agreement of the computed results has been observed with respect to SPICE simulated results. An average error of less than 3.2% is observed in the computation of the performance parameters using the proposed method.     

One- and Two-Dimensional Coherently Coupled Implant-Defined Vertical-Cavity Laser Arrays

Loss between elements of coherently coupled vertical-cavity surface-emitting laser (VCSEL) arrays typically causes out-of-phase operation with on-axis intensity nulls in the far-field. We show that in-phase evanescently coupled VCSEL arrays may be defined by proton implantation. An advantage for implanted in-phase coherently coupled VCSEL arrays is that this approach employs a simple and reliable fabrication process where the absence of loss between elements leads to in-phase coupling. We present data for 2, 3, and 4 element in-phase implant-defined coherently coupled VCSEL arrays.     

SWAN: high-level simulation methodology for digital substrate noise generation

Substrate noise generated by the switching digital circuits degrades the performance of analog circuits embedded on the same substrate. It is therefore important to know the amount of noise at a certain point on the substrate. Existing transistor-level simulation approaches based on a substrate model extracted from layout information are not feasible for digital circuits of practical size. This paper presents a complete high-level methodology, which simulates a large digital standard cell-based design using a network of substrate macromodels, with one macromodel for each standard cell. Such macromodels can be constructed for both EPI-type and bulk-type substrates. Comparison of our substrate waveform analysis (SWAN) to several measurements and to several full SPICE simulations indicates that the substrate noise is simulated with our methodology within 10%-20% error in the time domain and within 2 dB relative error at the major resonance in the frequency domain. However, it is several orders of magnitude faster in CPU time than a full SPICE simulation.     

An accurate analytical propagation delay model for high-speed CMLbipolar circuits

A new analytical delay model for high-speed CML circuits is presented. It is applicable to high-speed/low-voltage-swing silicon and HBT CML circuits operating at medium or high current densities. The model is based on bipolar SPICE parameters file, and can be used to estimate the propagation delay time of CML circuits under different operating conditions. The detailed transient analysis accounts for delay components due to each element in the complete SPICE bipolar transistor model. The comparison to SPICE circuit simulation results show excellent agreement for a wide range of state-of-the-art technologies and circuit parameters. The new model predicts the delay time with less than 5% error in most cases. The influence of the finite slopes (slewing rate) of the input signal and the device dimensions is also investigated. The delay model determined the optimum current i₀ (or load resistor R_L) for a transistor of a certain emitter area when driven by a source of a voltage swing (ΔV) and slew time (t_r ). At a specified power dissipation, the delay model is used to optimally size the transistor emitter area for maximum switching speed. The model provides circuit and device guidelines to minimize the propagation delay time and improve the performance of high-speed CML circuits     

Analytical model for switching transitions of submicron CMOS logics

We propose a new analytical model for the switching characteristics of CMOS logics. Our new model, named the Switching Response of CMOS logic by Convolution approach (SRC), can successfully produce the output waveforms under any switching conditions with simple analytical expressions. SRC modeling is a process of transforming CMOS logic into a linear system. This model provides procedures to determine the transfer function and the driving function (input of linear system) of the linear system from given CMOS logic, and then an output waveform, expressed as a third-order equation, is obtained by the convolution of two functions. All parameters in this model are determined in a straightforward manner from given device characteristics and layout geometry without empirical or fitting processes and presimulations. In addition, a delay equation is developed based upon the SRC model. With this delay equation, the delay can be predicted within a few percent differences compared to SPICE simulation results for the wide range of input transition time and output loading capacitance     

Subthreshold analysis of an MOS analog switch

Charge injection error in the presence of subthreshold effects has been analyzed. It is confirmed that the subthreshold effect is significant at low voltage falling rates. A simplified model is derived using an appropriate approximation. Predictions are compared to the results of a SPICE simulation, a nonquasi-static (NQS) model simulation and experimental results. Excellent agreement between the modified and NQS model and recently published experimental results was obtained. This analytical model is computationally efficient compared to the SPICE and NQS models and provides physical insight into the switching errors     

Crosstalk analysis for a CMOS gate driven inductively and capacitively coupled interconnects

This paper deals with crosstalk analysis of a CMOS driven capacitively and inductively coupled interconnect. The Alpha Power Law model of MOS transistor is used to represent a CMOS driver. This is combined with a transmission line-based coupled RLC model of interconnect to develop a composite model for analytical purpose. On this basis a transient analysis of crosstalk noise is carried out. Comparison of the analytical results with SPICE extracted results shows that the error involved is nominal.     

基于槽线的太赫兹同相和反相功分器设计

根据接地共面波导(GCPW)和槽线的结构特点,首先设计并仿真验证了一种由接地共面波导到槽线的功分器;然后根据槽线横截面的电场分布特性,设计了一种GCPW-槽线-GCPW结构的同相功分器和反相功分器。仿真结果表明,同相功分器在175~225 GHz范围内的插入损耗优于4 dB,回波损耗优于9.6 dB;反相功分器在185~215 GHz范围内的插入损耗优于4 dB,回波损耗优于10.5 dB,幅度不平衡度小于0.24 dB,相位不平衡度小于1.3°。相比其他太赫兹功分器,本文设计的功分器在插入损耗和回波损耗相当的情况下,具有更简单、紧凑和易于集成的结构。     

On the quadrature accuracy of in-phase coupled quadrature LC oscillator

In this article, closed-form equations are proposed for phase and amplitude errors of an in-phase coupled quadrature LC oscillator. First of all, the injected current from coupling network to switching one is analytically calculated in a novel approach. Then, fundamental equations are obtained to derive phase and amplitude errors which are results of mismatches of the tank's inductors, capacitors and resistors. The analysis shows that the LC tank's phase of this oscillator has a negligible deviation from zero that is desirable and causes low phase noise. Also, the study indicates that in-phase coupling of this structure generates an injection current that reduces the output current magnitude. In the following, a mechanism is proposed to compensate the phase error, using intentional mismatch in tail currents. Moreover, In contrast to previous works, there is not a considerable trade-off between phase error and phase noise; meaning phase noise is almost stable while phase error dramatically decreases. Next, Many simulations have been done in TSMC 0.18 μm to evaluate the proposed analytical equations and efficiency of the presented approach. Finally, all of these tests confirm the high accuracy of equations and capability of the mentioned technique.     

Design for velocity saturated, short-channel CMOS drivers withsimultaneous switching noise and switching time considerations

Design guidelines for velocity-saturated, short-channel CMOS drivers are presented in this paper based on approximating the package inductance by an effective, lumped, power-supply bus parasitic inductance. A worst-case maximum simultaneous switching noise V_GM and gate propagation delay time t_D,1/2 are treated as performance constraints for which driver design tradeoffs between driver geometry, the maximum number of simultaneously switched drivers, and the effective inductance are obtained. For typical loading conditions, design examples based on the proposed guidelines are shown by SPICE simulations using the MOS3 model to agree with both design goals within 10%     

Waveform analysis and delay prediction for a CMOS gate driving RLC interconnect load

This paper deals with the problem of estimating the performance of a CMOS gate driving RLC interconnect load. The widely accepted model for CMOS gate and interconnect line is used for the representation. The CMOS gate is modeled by an Alpha Power law model, whereas the distributed RLC interconnect is represented by an equivalent π-model. The output waveform and the propagation delay of the inverter are analytically calculated and compared with SPICE simulations. The analytical driver-interconnect load model gives sufficiently close results to SPICE simulations for two different cases of slow and fast input ramps. For each case of stimulation, the model gives an insight to four regions of operation of the CMOS gate. The voltage waveform at the end of an interconnect line is obtained for each region of operation. The SPICE and analytical results for the output voltage waveform and propagation delay match very closely.     

Broadband Millimeter-Wave In-Phase and Out-of-Phase Waveguide Dividers with High Isolation

In this paper, two novel broadband in-phase and out-of-phase waveguide power dividers with high isolation are presented. Based on the substrate-integrated waveguide (SIW) divider and SIW-to-waveguide transition circuit, two kinds of E-plane waveguide dividers have been implemented. Due to the features of in-phase and out-of-phase performances, the proposed waveguide dividers can provide much more flexibilities than that of conventional E-plane waveguide T-junction. A broadband phase and amplitude performances are achieved across the whole Ka-band owing to the wideband characteristic of the SIW divider and transition circuits. To minimize the size and loss of the divider, a compact and low-loss SIW-to-waveguide transition circuit has been developed using the antisymmetric tapered probes. Two prototypes of the Ka-band waveguide dividers, including the in-phase and out-of-phase types, have been fabricated and measured. Measured results show that the isolation, input return loss, output return loss, amplitude imbalance, and phase imbalance of the in-phase divider are better than 15.5, 13.1, 10.8, 0.4 dB, and 3.5⁰, while those of the out-of-phase divider are better than 15.0, 13.4, 10.4, 0.5 dB, and 3.6⁰, respectively, over the frequency range from 26.5 to 40 GHz. The measured results agree well with the simulated ones. Considering their wide bandwidth, high isolation, good port matching performance, and compact configuration, the two types of waveguide dividers can be good candidates for broadband applications in millimeter-wave waveguide systems.     

Effects of simultaneous switching noise on the tapered bufferdesign

Complementary metal-oxide-semiconductor (CMOS) output buffers, comprised of a series of tapered inverters, are used to drive large off-chip capacitances. The ratio of the size of transistors between two consecutive stages is the buffer taper factor. With higher frequency of operation and simultaneous switching of the output drivers, the parasitic inductance present at the pin-pad-package interface results in significant switching noise on the power lines. A comprehensive analysis and estimate of simultaneous switching noise (SSN) including the velocity saturation effects seen in the submicron transistors during the switching of output drivers is presented. The effect of SSN on the overall buffer propagation delay and transition time is discussed. The presence of SSN results in an increase in the optimum taper factor between inverter stages for a given capacitive load. Beyond a critical value, the output transition time of a tapered buffer increases with reducing taper factor due to SSN. SSN can be reduced by skewing the switching of output buffers, SPICE simulation results show that skewing buffer switching with additional inverter stages reduces SSN and increases buffer propagation delay     

The Effect of Signal Activity on Propagation Delay of CMOS Logic Gates Driving Coupled On-Chip Interconnections

The effect of interconnect coupling capacitances on neighboring CMOS logic gates driving coupled interconnections strongly depends upon signal activity. A transient analysis of two capacitively coupled CMOS logic gates is presented in this paper for different combinations of signal activity. The uncertainty of the effective load capacitance and propagation delay due to signal activity is addressed. Analytical expressions characterizing the output voltage and propagation delay are also presented for different signal activity conditions. The propagation delay based on these analytical expressions is within 3% as compared to SPICE, while the estimated delay neglecting the difference between the load capacitances can exceed 45%. The logic gates should be properly sized to balance the load capacitances in order to minimize any uncertainty in the delay and load. The peak noise voltage on a quiet interconnection determined from the analytical expressions is within 4% of SPICE. The peak noise voltage on a quiet interconnection can be minimized if the effective output conductance of the quiet logic gate driving the interconnect is increased.     

CMOS delay time model based on weighted peak current

The authors propose a new CMOS delay time model with the configuration ratio, the input slope and the load condition taken into account. This model is based on the optimally weighted switching peak current. The delay equations are computationally effective and the error is typically within 10% of SPICE results     

Input mapping algorithm for modelling of CMOS circuits

An algorithm for mapping every possible input pattern of a complementary metal oxide semiconductor (CMOS) gate to an equivalent set of normalised inputs (inputs which have the same starting point and transition time) is presented. Such an algorithm is required in order to perform analytical modelling of CMOS gates, and the results obtained are very accurate compared to SPICE simulations     

Design of CMOS tapered buffer for minimum power-delay product

The tapered buffer is analyzed from the viewpoint of power dissipation. Both uniform and nonuniform tapered buffers are considered. It is found that there is an optimum value of tapering factor for a minimum power-delay product. In case of uniform tapering, we can obtain an analytical solution of the optimum tapering factor for a minimum power-delay product, which is about 1.5~2 times larger than that for a minimum propagation delay. It is also found that there exists a nonuniform tapering factor which gives a global optimum condition for a minimum power-delay product, which, however, results in a larger short-circuit current. Compared with a uniform buffer, a nonuniform tapered buffer shows about 8% improvement in dynamic switching energy, and 3~5% improvement in total switching energy. We confirm this by simulating tapered buffers with SPICE     

Prediction of 2-level PWM inverter efficiency using MATLAB/Simulink

This article proposes a direct approach for the prediction of inverter efficiency using MATLAB/Simulink, instead of an indirect loss calculation approach based on analytical models. In analytical approach, efficiency is obtained by calculating individual losses separately, such as switching losses, conduction losses and harmonic losses using analytical models. However, this approach requires accurate analytical models and complicated calculations, due to the variation in the switching frequency, switching transient and modulation techniques. In the proposed approach, the actual waveform of the inverter system is directly generated using MATLAB/Simulink. The instantaneous voltage and current waveform including switching transients are generated. Thus, the proposed approach is very simple and convenient for efficiency prediction. The proposed approach also works for any system parameters or control methods, such as various pulse-width modulation (PWM) techniques, different switching frequencies, switching devices and load types. The proposed approach can be adopted for the efficiency prediction of any switching strategies and any types of inverters such as neutral-point-clamped (NPC) inverters, H bridge inverters and H5 topology, since the topologies are modelled as circuits in the MATLAB/Simulink program and no analytical model is required for the proposed approach. Furthermore, the proposed approach can provide operation techniques and conditions such as PWM techniques and switching frequency that offer high efficiency. In this article, inverter performance is evaluated for various PWM techniques and switching frequencies. The PWM technique and switching frequency that offer high efficiency is obtained. Finally, the proposed approach is verified by experimental results.