低压工作的轨到轨输入／输出缓冲级放大器

本文提出了一种低压工作的轨到轨输入／输出缓冲级放大器。利用电阻产生的输入共模电平移动,该放大器可以在低于传统轨到轨输入级所限制的最小电压下工作,并在整个输入共模电压范围内获得恒定的输入跨导;它的输出级由电流镜驱动,实现了轨到轨电压输出,具有较强的负载驱动能力。该放大器在CSMCO．6-μmCMOS数模混合工艺下进行了HSPICE仿真和流片测试,结果表明：当供电电压为5V,偏置电流为60uA,负载电容为10pF时,开环增益为87．7dB,功耗为579uw,单位增益带宽为3．3MHz;当该放大器作为缓冲级时,输入3VPP10kHz正弦信号,总谐波失真THD为53．2dB。     

恒跨导高摆率轨对轨运算放大器的设计

本文在分析MOS管恒跨导输入级和AB类输出级运算放大器的基础上设计了一个高摆率、恒跨导的轨对轨运算放大器。在输入级中采用了齐纳二极管的稳压原理,保证Rail-to-Rail运算放大器的输入跨导恒定。为了实现高转换率,本文采用了一种新型的压摆率提高电路。另外,为了提高系统的稳定性,采用了控制零点的米勒补偿进行频率补偿。采...     

基于最小电流选择的运算放大器设计

设计了一种工作电压为3V恒跨导满幅CMOS运算放大器,针对轨对轨输入级中存在的跨导不恒定和简单AB类输出级性能偏差这2个问题,提出了利用最小电流选择电路来稳定输入级的总跨导;浮动电流源控制的无截止前馈AB类输出级实现了运放的满幅输出,同时减小了交越失真。该电路通过HSpice进行仿真验证,在0～3V输入共模范围内,输入级跨导的变化小于3.3%,开环增益为93dB,单位增益带宽为8MHz,相位裕量为66°。     

A 75 μW rail-to-rail class AB CMOS operational amplifier

A new class AB CMOS operational amplifier featuring rail-to-rail output swing is presented. The proposed circuit operates with an output voltage supply of 1 V only, while the overall power consumption is lower than 75 μW. The output stage shows a quiescent current of 15 μA, while it guarantees a peak current of 220 μA. The slew rate is 1.5 V μs⁻¹ (C₁ = 150 pF) and the THD is −63 dB, when a 0.98 V_pp−10.4 kHz sinewave is applied, as measured on an experimental prototype realised with a standard 0.8 μm CMOS process. The circuit presented is suitable for use in portable hand-set systems or in medical aids.     

一种基于恒定电流技术的具有低功耗和低失真的轨导轨输入输出放大器

本文提出了一种应用于音频信号处理的具有恒定的跨导Rail-to-Rail放大器,并且恒定跨导是通过一种恒定电流技术来实现。此技术是基于差分输入对工作在弱反型区。对于工作在弱反型区的MOSFET具有低失调和低功耗的优势。采用标准的0.35微米的CMOS工艺对电路进行流片,此芯片占有面积75×183 μm2。测试结果表明：在3.3V电源电压下,电路最大功耗为85.37mW;在2kHz时总谐波失真为1.2%。     

A low power and low distortion rail-to-rail input/output amplifier using constant current technique

A rail-to-rail amplifier with constant transconductance,intended for audio processing,is presented.The constant transconductance is obtained by a constant current technique based on the input differential pairs operating in the weak inversion region.MOSFETs working in the weak inversion region have the advantages of low power and low distortion.The proposed rail-to-rail amplifier,fabricated in a standard 0.35μm CMOS process,occupies a core die area of 75×183μm~2.Measured results show that the maximum power consumption is 85.37μW with a supply voltage of 3.3 V and the total harmonic distortion level is 1.2%at 2 kHz.     

CMOS高频电流差分缓冲放大器

本文提出了一种利用修改的差分电流传输器(MDCC)与电压跟随器实现的全新高频CMOS差分电流缓冲放大器电路(CDBA).PSPICE仿真结果表明,在0～100MHz的频率范围内,提出的电路能很好地满足CDBA的端口特性.作为应用,实现了二阶电流模式多功能滤波器,并对他们进行了仿真.     

A low noise compact class AB buffer amplifier with accurate quiescent current control

The authors present a new low-noise class AB buffer amplifier. The proposed buffer amplifier achieves a low noise with fast settling time and low power consumption. The buffer amplifier circuit attains an input referred noise voltage of 12.8 \( {{\text{nV}} /{\sqrt {\text{Hz}}}} \), a DC gain of 108 dB, a unit-gain frequency of 8 MHz, and rising slew rate of 36 V/μs, as the load capacitance equals 150 pF. The circuit is power efficient when driving large capacitive loads and is well suited for low noise low power analog video buffer applications.     

电流型运算放大器在应用电路中的特性研究

文中简要介绍了电流型运放的特性,着重对电流型运放的应用电路进行测试,研究电流型运放的应用特性。实验中,选择典型电流型运放及电压型运放构建负阻变换器、电压跟随器和同相比例放大器,通过对此3类应用电路的测试,分析、总结运放参数对特殊应用电路的影响,为电路设计者在具体电路的设计中恰当选择适合的放大器提供参考。     

Design procedure for two-stage CMOS opamp with optimum balancing of speed,power and noise

This article presents a basic two-stage CMOS opamp design procedure that provides the circuit designer with a means to establish optimised balancing between speed, power and noise for a given load condition. The proposed design steps allow opamp designers to optimise the power consumption for the given constraints of settling time, accuracy, noise and load. The key factor is to establish the optimum combination of ratios of transconductance of second stage to first stage and load capacitor to compensation capacitor. So, required accuracy and settling time can be established with minimum power consumption. Unlike the earlier reported design procedures, in this article a systematic method is presented to set the quiescent voltages at the transistors of the first and second stages of the opamp. This work will be helpful to select appropriate method of implementation of Miller compensation for given constraints. To verify the viability of the proposed design steps, SPICE simulation results for the proposed procedure are given. Best simulation results obtained on Tanner tool show settling time and power dissipation equal to 320 ns and 188.5 μW, respectively, for 5 pf capacitive load.     

High slew rate current mode transconductance error amplifier for low quiescent current output-capacitorless CMOS LDO regulator

This paper presents a CMOS low quiescent current output-capacitorless low-dropout regulator (LDO) based on a high slew rate current mode transconductance amplifier (CTA) as error amplifier. Using local common-mode feedback (LCMFB) in the proposed CTA, the order of transfer characteristic of the circuit is increased. Therefore, the slew rate at the gate of pass transistor is enhanced. This improves the LDO load transient characteristic even at low quiescent current. The proposed LDO topology has been designed and post simulated in HSPICE in a 0.18 µm CMOS process to supply the load current between 0 and 100 mA. The dropout voltage of the LDO is set to 200 mV for 1.2–2 V input voltage. Post-layout simulation results reveal that the proposed LDO is stable without any internal compensation strategy and with on-chip output capacitor or lumped parasitic capacitances at the output node between 10 and 100 pF. The total quiescent current of the LDO including the current consumed by the reference buffer circuit is only 3.7 µA. A final benchmark comparison considering all relevant performance metrics is presented.     

A new CMOS wideband low noise amplifier with gain control

In this paper, a new CMOS wideband low noise amplifier (LNA) is proposed that is operated within a range of 470 MHz-3 GHz with current reuse, mirror bias and a source inductive degeneration technique. A two-stage topology is adopted to implement the LNA based on the TSMC 0.18-μm RF CMOS process. Traditional wideband LNAs suffer from a fundamental trade-off in noise figure (NF), gain and source impedance matching. Therefore, we propose a new LNA which obtains good NF and gain flatness performance by integrating two kinds of wideband matching techniques and a two-stage topology. The new LNA can also achieve a tunable gain at different power consumption conditions. The measurement results at the maximum power consumption mode show that the gain is between 11.3 and 13.6 dB, the NF is less than 2.5 dB, and the third-order intercept point (IIP3) is about −3.5 dBm. The LNA consumes maximum power at about 27 mW with a 1.8 V power supply. The core area is 0.55×0.95 mm².     

A CMOS low noise amplifier with integrated front-side micromachined inductor

The paper presents the design and characterization of a low noise amplifier (LNA) in a 0.18 μm CMOS process with a novel micromachined integrated stacked inductor. The inductor is released from the silicon substrate by a low-cost CMOS compatible dry front-side micromachining process that enables higher inductor quality factor and self-resonance frequency. The post-processed micromachined inductor is used in the matching network of a single stage cascode 4 GHz LNA to improve its RF performance. This study compares performance of the fabricated LNA prior to and after post-processing of the inductor. The measurement results show a 0.5 dB improvement in the minimum noise figure and a 1 dB increase in gain, while good input matching is maintained. These results show that the novel low-cost CMOS compatible front-side dry micromachining process reported here significantly improves performance and is very promising for System-On-Chip (SOC) applications.     

Design of 3.1–10.6 GHz ultra-wideband CMOS low noise amplifier with current reuse technique

A new low complexity ultra-wideband 3.1–10.6 GHz low noise amplifier (LNA), designed in a chartered 0.18 μm RFCMOS technology, is presented in this paper. The ultra-wideband LNA only consists of two simple amplifiers with an inter-stage inductor connected. The first stage utilizing a resistive current reuse and dual inductive degeneration techniques is used to attain a wideband input matching and low noise figure. A common source amplifier with inductive peaking technique as the second stage achieves high flat gain and wide the −3 dB bandwidth of the overall amplifier simultaneously. The implemented ultra-wideband LNA presents a maximum power gain of 15.6 dB, a high reverse isolation of −45 dB and a good input/output return losses are better than −10 dB in the frequency range of 3.1–10.6 GHz. An excellent noise figure (NF) of 2.8–4.7 dB was obtained in the required band with a power dissipation of 14.1 mW under a supply voltage of 1.5 V. An input-referred third-order intercept point (IIP3) is −7.1 dBm at 6 GHz. The chip area including testing pads is only 0.8 mm × 0.9 mm.     

一个低功耗的带片上参考电压缓冲器的12位30兆采样率的CMOS流水线模数转换器

介绍了一个在0.13µm 1P8M CMOS工艺下实现的12位30兆采样率流水线模数转换器。提出了一种消除前端采样保持电路的低功耗设计方法。除了第一级之外,带双输入的两级cascode补偿的运算放大器在相邻级间共享以进一步地减小功耗。该模数转换器在5MHz的模拟输入和30.7MHz的采样速率下达到了65.3dB的SNR,75.8dB的SFDR和64.6dB的SNDR。该芯片在1.2V电源电压下消耗33.6mW。FOM达到了0.79pJ/conv step。     

A low power 12-bit 30 MSPS CMOS pipeline ADC with on-chip voltage reference buffer

A 12-bit 30 MSPS pipeline analog-to-digital converter(ADC) implemented in 0.13-μm 1P8M CMOS technology is presented.Low power design with the front-end sample-and-hold amplifier removed is proposed.Except for the first stage,two-stage cascode-compensated operational amplifiers with dual inputs are shared between successive stages to further reduce power consumption.The ADC presents 65.3 dB SNR,75.8 dB SFDR and 64.6 dB SNDR at 5 MHz analog input with 30.7 MHz sampling rate.The chip dissipates 33.6 mW from 1.2 V power supply.FOM is 0.79 pJ/conv step.     

A resistorless CMOS bandgap reference with low temperature coefficient and high PSRR

A novel bandgap reference (BGR) with low temperature and supply voltage sensitivity without any resistor, which is compatible with standard CMOS process, is presented in this article. The proposed BGR utilises a differential amplifier with an offset voltage proportional to absolute temperature to compensate the temperature drift of emitter–base voltage. Besides, a self-biased current source with feedback is used to provide the bias current of the BGR core for reducing current mirror errors dependent on supply voltage and temperature further. Verification results of the proposed BGR implemented with 0.35?µm CMOS process demonstrate that a temperature coefficient of 10.2?ppm/°C is realised with temperature ranging from ?40°C to 140°C, and a power supply rejection ratio of 58?dB is achieved with a maximum supply current of 27?µA. The active area of the presented BGR is 160?×?140?µm².     

一种应用于直接变频WLAN接收机带数字辅助直流失调消除功能的可变增益放大器

本文提出了一种包含数字辅助直流失调消除(DCOC)功能,应用于直接变频无线局域网接收机的可变增益放大器(PGA)电路。该PGA采用0.13微米标准CMOS工艺实现,芯片面积0.39平方毫米,在1.2伏电源电压下的功耗为6.5毫瓦。通过采用单环路单数模转换器(DAC)混合信号直流失调消除结构,直流失调消除的最小建立时间减小至1.6微秒,同时可变增益放大器的增益能够在-8分贝到54分贝间以2分贝的步长变化。该直流失调消除环路采用了一种分段式数模转换器以在不牺牲精度的前提下降低设计复杂度,并采用了特定的数字控制算法使得环路的直流失调消除响应时间能够在快慢两种模式间动态切换,以使可变增益放大器符合无线局域网应用的要求。