Design of a 24–40 GHz balanced low noise amplifier using Lange couplers

A wide band （24–40 GHz） fully integrated balanced low noise amplifier （LNA） using Lange couplers was designed and fabricated with a 0.15 μm pseudomorphic HEMT （pHEMT） technology. A new method to design a low-loss and high-coupling Lange coupler for wide band application in microwave frequency was also presented. This Lange coupler has a minimum loss of 0.09 dB and a maximum loss of 0.2 dB over the bandwidth from 20 to 45 GHz. The measured results show that the realized four-stage balanced LNA using this Lange coupler exhibites a noise figure （NF） of less than 2.7 dB and the maximum gain of 30 dB; moreover, a noticeably improved reflection performance is achieved. The input VSWR and the output VSWR are respectively less than 1.45 and 1.35 dB across the 24–40 GHz frequency range.     

High linearity technique for ultra-wideband low noise amplifier in 0.18 μm CMOS technology

A linearization technique for ultra-wideband low noise amplifier (UWB LNA) has been designed and fabricated in standard 0.18 μm CMOS technology. The proposed technique exploits the complementary characteristics of NMOS and PMOS to improve the linearity performance. A two-stage UWB LNA is optimized to achieve high linearity over the 3.1-10.6 GHz range. The first stage adopts inverter topology with resistive feedback to provide high linearity and wideband input matching, whereas the second stage is a cascode amplifier with series and shunt inductive peaking techniques to extend the bandwidth and achieve high gain simultaneously. The proposed UWB LNA exhibits a measured flat gain of 15 dB within the entire band, a minimum noise figure of 3.5 dB, and an IIP3 of 6.4 dBm while consuming 8 mA from a 1.8 V power supply. The total chip area is 0.39 mm², including all pads. The measured input return loss is kept below −11 dB, and the output return loss is −8 dB, from 3.1 to 10.6 GHz.     

A 2 GHz variable gain low noise amplifier in 0.18-μm CMOS

This paper describes a 2 GHz active variable gain low noise amplifier (VGLNA) in a 0.18-μm CMOS process. The VGLNA provides a 50-Ω input impedance and utilizes a tuned load to provide high selectivity. The VGLNA achieves a maximum small signal gain of 16.8 dB and a minimum gain of 4.6 dB with good input return loss. In the high gain and the low gain modes, the NFs are 0.83 dB and 2.8 dB, respectively. The VGLNA’s IIP3 in the high gain mode is 2.13 dBm. The LNA consumes approximately 4 mA of current from a 1.8-V power supply.     

A 0.18μm CMOS dual-band low power low noise amplifier for a global navigation satellite system

This paper presents a dual-band low noise amplifier for the receiver of a global navigation satellite system. The differences between single band and multi-band design methods are discussed.The relevant parameter analysis and the details of circuit design are presented.The test chip was implemented in a TSMC 0.18μm 1P4M RF CMOS process.The LNA achieves a gain of 16.8 dB/18.9 dB on 1.27 GHz/1.575 GHz.The measured noise figure is around 1.5-1.7 dB on both bands.The LNA consumes less than 4.3 mA of current ...     

Design of a wideband low-power continuous-time ΣΔ modulator in 90 nm CMOS technology

The design of a wideband low-power continuous-time (CT) sigma-delta modulator (ΣΔM) is presented. At system level, an improved direct design method is used which allows direct design of the modulator in continuous-time domain. The modulator employs a low-latency flash quantizer to minimize excess loop delay. Digital-to-analog (DAC) trimming technique is used to correct the quantizer offset error, which permits minimum-sized transistors to be used for fast and low-power operation. The modulator is designed in 90 nm CMOS process with single 1.0-V power supply. It achieves a dynamic range (DR) of 75 dB and a signal-to-noise-and-distortion-ratio (SNDR) of 70 dB in a 25 MHz signal bandwidth with 16.4 mW power dissipation.     

A 0.18μm CMOS low noise amplifier using a current reuse technique for 3.1-10.6 GHz UWB receivers

A new,low complexity,ultra-wideband 3.1-10.6 GHz low noise amplifier(LNA),designed in a chartered 0.18μm RFCMOS technology,is presented.The ultra-wideband LNA consists of only two simple amplifiers with an inter-stage inductor connected.The first stage utilizing a resistive current reuse and dual inductive degeneration technique is used to attain a wideband input matching and low noise figure.A common source amplifier with an inductive peaking technique as the second stage achieves high flat gain and wide -3 dB bandwidth of the overall amplifier simultaneously.The implemented ultra-wideband LNA presents a maximum power gain of 15.6 dB,and a high reverse isolation of—45 dB,and good input/output return losses are better than -10 dB in the frequency range of 3.1-10.6 GHz.An excellent noise figure(NF) of 2.8-4.7 dB was obtained in the required band with a power dissipation of 14.1 mW under a supply voltage of 1.5 V.An input-referred third-order intercept point(IIP3) is -7.1 dBm at 6 GHz.The chip area,including testing pads,is only 0.8×0.9 mm2.     

Design of a 65?nm CMOS 8?GHz wideband: track-and-hold, for radio astronomy and cosmology applications

In modern millimeter and sub-millimeter communication systems, particle physics, neutrino astronomy, and for passive applications in radio astronomy or remote atmospheric sensing, the trend is to eliminate analog functional blocks, such as mixers and filters, by converting the signal into the digital domain as early as possible in the processing chain. Therefore, fast analog-to-digital converters (ADC) are needed. Track-and-hold (TAH) circuits can reduce time constraints by holding the analog input value while comparators are sampled, in order to minimize the aperture time errors. This article describes the design of a TAH using the 65?nm CMOS technology from STMicroelectronics. A fully differential architecture has been adopted. The circuit exhibits a ?3?dB input bandwidth wider than 8?GHz. At 8?GHz, the maximum sampling frequency, the measured overall power consumption and gain are 178?mW and ?2?dB, respectively. The TAH core dissipates around 40?mW. The measured total harmonic distortion (THD) at Nyquist sampling conditions is about ?37?dB. The circuit die area is 1.1?mm2.     

Design of an ultra small passive balun in CMOS 65?nm technology for 60?GHz applications

In this paper a new procedure for the spiral Marchand balun design is shown and demonstrated. The size reduction for this component is fundamental to obtain a high level of integration for the radio frequency analog circuits. This work shows a micro-structure that, working as a balun, achieves good performance in phase and amplitude balance, while maintaining minimum size. These results were achieved by performing an accurate theoretical analysis followed by an electromagnetic simulation of the structure. A set of equations are proposed to describe the component behavior and the measurements show a strong agreement with the simulations confirming the quality of the design flow. The balun shows a maximum of 1.5 dB of insertion loss, with 0.1 dB of amplitude imbalance. The phase imbalance reach as a maximum of 7° at 65?GHz. The total occupied area of the balun remain below to 0.01?mm².     

Design of variable gain low noise amplifier using feedback circuit with memory circuits for 5.2 GHz band

This paper presents a novel adaptive gain control method for Low Noise Amplifiers (LNAs) at the 5.2 GHz band using a feedback circuit, and operating in the baseband signal frequency. A uniform step variable gain can be implemented using a two-stage LNA based on the cascade topology. The feedback circuit consists of seven functional blocks, each of which has been designed for minimum power consumption. The storage circuit in the feedback circuit is used to store the previous signal magnitude, thus avoiding unnecessary power consumption in the LNA. We simulated the performances of LNA in terms of the gain, IIP3, Noise Figure (NF), stability, and power consumption. The adaptive front-end LNA with the feedback circuit can achieve a variable gain from 11.39 dB to 22.74 dB with excellent noise performance even at a high gain mode. The DC power of the proposed variable gain LNA consumes 5.68–6.75 mW under a 1.8 V supply voltage.     

A 0.18μm CMOS 3-5 GHz broadband flat gain low noise amplifier

A 3-5 GHz broadband flat gain differential low noise amplifier (LNA) is designed for the impulse radio uitra-wideband (IR-UWB) system. The gain-flatten technique is adopted in this UWB LNA. Serial and shunt peaking techniques are used to achieve broadband input matching and large gain-bandwidth product (GBW). Feedback networks are introduced to further extend the bandwidth and diminish the gain fluctuations. The prototype is fabricated in the SMIC 0.18 μm RF CMOS process. Measurement results show a 3-dB gain bandwidth of 2.4-5.5 GHz with a maximum power gain of 13.2 dB. The excellent gain flatness is achieved with ±0.45 dB gain fluctuations across 3-5 GHz and the minimum noise figure (NF) is 3.2 dB over 2.5-5 GHz. This circuit also shows an excellent input matching characteristic with the measured S11 below-13 dB over 2.9-5.4 GHz. The input-referred 1-dB compression point (IPldB) is -11.7 dBm at 5 GHz. The differential circuit consumes 9.6 mA current from a supply of 1.8 V.     

A 0.18 μm CMOS 3-5 GHz broadband flat gain low noise amplifier

A 3-5 GHz broadband flat gain differential low noise amplifier(LNA) is designed for the impulse radio ultra-wideband(IR-UWB) system.The gain-flatten technique is adopted in this UWB LNA.Serial and shunt peaking techniques are used to achieve broadband input matching and large gain-bandwidth product(GBW).Feedback networks are introduced to further extend the bandwidth and diminish the gain fluctuations.The prototype is fabricated in the SMIC 0.18μm RF CMOS process.Measurement results show a 3-dB gain band...     

Design of an L1 band low noise single-chip GPS receiver in 0.18 μm CMOS technology

This article presents an L1 band low noise integrated global positioning system(GPS)receiver chip using 0.18 μm CMOS technology.Dual-conversion with a low-IF architecture was used for this GPS receiver.The receiver is composed of low noise amplifier(LNA),down-conversion mixers,band pass filter,received signal strength indicator,variable gain amplifier,programmable gain amplifier,ADC,PLL frequency synthesizer and other key blocks.The receiver achieves a maximum gain of 105 dB and noise figure less than 6 dB.The variable gain amplifier(VGA)and programmable gain amplifier(PGA)provide gain control dynamic range over 50 dB.The receiver consumes less than 160 mW from a 1.8 V supply while occupying a 2.9 mm2chip area including the ESD I/O pads.     

5.8GHz WLAN CMOS双平衡混频器的设计

介绍了基于0．18μm CMOS工艺的802．11a无线局域网（WLAN）有源双平衡混频器的设计方法。该混频器射频（RF），本振（LO）和中频（IF）信号频率分别为5．8GHz，4.6GHz和1．2GHz。仿真结果显示：在1．8V电压下；变频增益为4．27dB，单边带噪声系数为10．73dB，1dB压缩点为-13．18dB，三阶输入截点为-3．04dB，功耗为32．4mW，芯片面积为1．8mm×1mm。     

Design of a low noise distributed amplifier with adjustable gain control in 0.15μm GaAs PHEMT

正A low noise distributed amplifier consisting of 9 gain cells is presented.The chip is fabricated with 0.15-μm GaAs pseudomorphic high electron mobility transistor(PHEMT) technology from Win Semiconductor of Taiwan.A special optional gate bias technique is introduced to allow an adjustable gain control range of 10 dB.A novel cascode structure is adopted to extend the output voltage and bandwidth.The measurement results show that the amplifier gives an average gain of 15 dB with a gain flatness of±1 dB in the 2-20 GHz band.The noise figure is between 2 and 4.1 dB during the band from 2 to 20 GHz.The amplifier also provides 13.8 dBm of output power at a 1 dB gain compression point and 10.5 dBm of input third order intercept point(IIP3),which demonstrates the excellent performance of linearity.The power consumption is 300 mW with a supply of 5 V,and the chip area is 2.36×1.01 mm~2.     

A transformer-loaded receiver front end for 2.4 GHz WLAN in 0.13μm CMOS technology

A 2.4 GHz radio frequency receiver front end with an on-chip transformer compliant with IEEE 802.11b/g standards is presented.Based on zero-IF receiver architecture,the front end comprises a variable gain common-source low noise amplifier with an on-chip transformer as its load and a high linear quadrature folded Gilbert mixer.As the load of the LNA,the on-chip transformer is optimized for lowest resistive loss and highest power gain.The whole front end draws 21 mA from 1.2 V supply,and the measured results show a double side band noise figure of 3.75 dB,-31 dBm IIP3 with 44 dB conversion gain at maximum gain setting.Implemented in 0.13μm CMOS technology,it occupies a 0.612 mm~2 die size.     

2 to 23 GHz BiFET low noise amplifier design flow and implementations in 0.25 μm SiGe BiCMOS technology

Two BiFET LNAs are here reported, implemented in a 0.25 μm BiCMOS technology from ST Microelectronics. First of them, dedicated to WCDMA standard, depicts a 15.5 and 2.85 dB, S₂₁ and noise figure (NF), respectively, under 2 mA current consumption. The second realization operates at 23 GHz for Mini-Link application. It provides a 14 dB gain and 7 dB at 22 GHz NF for an 8.2 mA current consumption under 2.5 V. Both circuits were designed according to a design flow, here depicted, based on input matching, NF and gain optimisation. A large part of the article also deals with high frequency layout considerations. Indeed useful techniques dedicated to integrated microstrip waveguides and RF inter-connections are proposed based on 3D electromagnetic field simulations.