Noise-aware interconnect power optimization in domino logic synthesis

Realization of high-performance domino logic depends strongly on energy-efficient and noise-tolerant interconnect design in ultradeep submicrometer processes. We characterize the cycle-averaged power model for interconnects accounting for switching statistics and dynamic behaviors. For the sake of signal integrity, cross-coupling effects are also characterized, which reflect logical correlation between adjacent wires. Based on the new models for interconnect power and capacitive crosstalk, we optimize the coupling power consumed by interconnects with crosstalk constraints. Experimental results show that optimized designs save the power consumption about 14% on average.     

Two-pole approximation for interconnect design and optimization

Firstly, an approach to find two approximate poles for capturing the system behaviour of interconnect network is presented. Secondly, two parameters, the damping ratio and natural undamped frequency, are expressed as functions of the two poles. These two parameters are used to define an objective function and constraints, which form a constrained multivariable nonlinear optimization problem. The optimization problem is solved using a gradient projection method. One major advantage of our approach is the ability to explicitly control the maximum overshoots at the observation points.     

Multi-objective optimization of interconnect geometry

The rapid increase in the number of wiring layers due to improved planarization and metallization techniques permits spatial resources to be traded for improved performance. Yield, power dissipation and propagation delay are all sensitive to the selection of the pitch and width of wires in each layer. As in many other engineering design problems, however, there exists no unique solution which simultaneously optimizes all aspects of system performance. The best that can be achieved is the identification of the optimal surface within the multi-objective performance space. A single design can be chosen from this list a posteriori using additional selection criteria which may depend, for example, on the specific details of the product application. This paper investigates the use of Pareto genetic algorithms to explore the extent of multi-objective optimal surfaces. The tradeoffs between yield, power-dissipation and cycle time for a benchmark netlist are examined as a function of in-plane geometry for a seven-layer interconnect.     

Cell-based interconnect migration by hierarchical optimization

Fueled by Moore's Law, VLSI market competition and economic considerations dictates the introduction of new processor's microarchitecture in a two-year cycle called “Tick-Tock” marketing strategy. A new processor is first manufactured in the most advanced stable process technology, followed in a one-year delay by introducing chips comprising same microarchitecture but manufactured in a newer scaled process technology, thus allowing higher production volumes, better performance and lower cost. Tick-Tock is enabled by the automation of chip's layout conversion from an older into a newer manufacturing process technology. This is a very challenging computational task, involving billions of polygons. We describe an algorithm of a hierarchy-driven optimization method for cell-based layout conversion used at Intel for already several product generations. It transforms the full conversion problem into successive problems of significantly smaller size, having feasible solutions if and only if the full-chip problem does. The proposed algorithm preserves the design intent, its uniformity and maintainability, a key for the success of large-scale projects.     

High speed interconnect through device optimization for subthreshold FPGA

Field programmable gate array (FPGA) consumes a significant amount of static and dynamic power due to the presence of additional logic for providing more flexibility as compared to application specific integrated circuits (ASICs). The fabrication cost of ASICs is rising exponentially in deep submicron and hence it is important to investigate different techniques for reducing FPGA power consumption so that they can also be employed in place of ASICs in portable energy constrained applications. It is also important to investigate the possibility of extending the use of FPGA even to subthreshold region for ultra low power (ULP) applications. Interconnect resources of an FPGA consumes most of the chip power, area and also determines the overall circuit delay. Subthreshold circuits show orders of magnitude power saving over superthreshold circuits. Improving the performance of subthreshold circuits is a main design challenge at the circuit and device levels to spread their application area. This paper proposes to improve the performance of subthreshold FPGA in terms of delay and switching energy by optimizing and operating interconnect drivers in the near threshold operating region. The possibility of inserting repeaters and the suitability of CNT as an interconnect in the subthreshold region are also explored. The simulation of FPGA interconnect resources using the proposed technique shows 67%, 73.33% and 61.8% increase in speed and 35.72%, 39% and 35.44% reduction in switching energy for Double, Hex and Long interconnect segments, respectively, over the conventional one.     

A statistical yield optimization framework for interconnect in double patterning lithography

In double patterning lithography, within-layer overlay error results in critical dimensions variability. Overlay error has been considered as a systematic source of variation; however, it is segueing into a random error for technology nodes smaller than 45-nm. Therefore, statistical design techniques should be applied to estimate and optimize the yield loss due to overlay error. In this paper, we study the impacts of overlay error on functional and parametric yields of interconnects in 32- and 22-nm technologies. A yield optimization method is applied to derive optimal width and spacing of interconnects for mentioned technologies. Experimental results show that parametric yield loss becomes more problematic in 22-nm technology node compared with the functional yield loss. Moreover, we show that DFM techniques such as wire spreading are necessary to realize the desirable parametric constraints in 22-nm node. Our analysis reveals that overlay electrical impact increases considerably in DPL in the presence of congestion.     

POMR: a power-aware interconnect optimization methodology

As VLSI technologies scale down, the average die size is expected to remain constant or to slightly increase with each generation. This results in an average increase in the global interconnect lengths. To mitigate their impact, buffer insertion has become the most widely used technique. However, unconstrained buffering is expected to require several hundreds of thousands of global interconnect buffers. This increased number of buffers is destined to adversely impact the chip power consumption. In this paper, an optimal power maze routing and buffer insertion/sizing problem for a two-pin net is formulated, as a shortest paths ranking problem. The pseudopolynomial time bound of the new formulation fits well within the context of the increased number of buffers. In fact, power savings as high as 25% for the 130-nm technology with a 10% sacrifice in delay is achieved. Furthermore, with the advent of dual threshold technologies, power sensitive applications can substantially benefit from adopting dual threshold buffers. Accordingly, the proposed problem formulation is extended to incorporate the selection of the buffer threshold voltage, where a twofold increase in power savings is observed. During the assessment of the impact of technology scaling using a set of MCNC Benchmarks, an average power saving as high as 35% with a 10% sacrifice in delay is observed. In addition, there is a 10% variation in the power savings when accounting for the process variations.     

Loop-based interconnect modeling and optimization approach for multigigahertz clock network design

A highly efficient loop-based interconnect modeling methodology is proposed for multigigahertz clock network design and optimization. Closed-form loop resistance and inductance models are proposed for fully shielded global clock interconnect structures, which capture high-frequency effects including inductance and proximity effects. The models are validated through comparisons with electromagnetic simulations and measured data taken from a Power4 chip. This modeling methodology greatly improves the clock interconnect simulation efficiency and enables fast physical design exploration. Examples of interconnect performance optimization are demonstrated and design guidelines are proposed.     

快速片上互连缓冲器插入时序优化分析

互连线延时已成为制约大规模集成电路性能的瓶颈,而缓冲器插入能很好解决互连线延时。Van GinnekenfvGl算法是缓冲器插入互连时序优化的经典算法,针对此算法的3个主要操作过程进行改进,利用红黑树数据结构存储路由拓扑数据结构,缩短数据结构的更新访问时间;利用快速冗余判别和排序方法减小解方案数量和求解最优的复杂度。通过标准测试电路集ISCAS89中的电路对本文方法进行测试,测试结果表明,虽然随着电路规模增加,改进方法和传统方法运行时间都相应增加,但改进方法的优势更加明显;且随着缓冲器库规模的增加,其优势也越发明显,如只有一种缓冲器的缓冲器库,改进算法耗时为VG算法的73．28％,当有8种和20种缓冲器的缓冲器库时,耗时分别为VG算法的67．34％和63．05％。采用本文中的快速缓冲器插入算法,能有效缩短基于缓冲器插入的大规模互连时序优化时间。     

Raphael-深亚微米集成互连参数仿真优化系统

针对超深亚微米层次下的金属互连设计,使用Raphael(集成布线互连)仿真系统完成了互连寄生效应参数的提取。介绍了Raphael仿真系统的主要功能及基本应用,并分析了常规集成布线互连参数模型。采用二层跨越式互连结构,对寄生电阻、电容参数进行了仿真,并得到电流密度的分布结果。这些参数的提取及验证对电路的布局设计是十分重要的。     

超深亚微米层次互连特性及其布局布线优化(英文)

随着集成电路特征尺寸进入超深亚微米层次,互连线开始成为制约系统功能和可靠性的决定性因素。本文介绍了布局布线中的几种优化步骤:拥挤驱动布局、局部布局和搜索提炼、轨道分配和搜索修补。并结合Synopsys公司的超深亚微米布局布线系统APOLLO-Ⅱ有效地解决了互连线的串扰噪声和破坏问题。     

Global interconnect width and spacing optimization for latency, bandwidth and power dissipation

This paper addresses a novel methodology optimizing global interconnect width and spacing for International Technology Roadmap for Semiconductors technology nodes. Global interconnects with and without buffer insertion are considered. The effects of the width and spacing of global interconnects on performance, such as delay, bandwidth, total repeater area and energy dissipation, are analyzed. The product of delay and bandwidth is used as the figure of merit for simultaneous short latency and large bandwidth and the proposed methodology can optimize global interconnects for the maximal figure of merit. It is demonstrated that buffers should not be inserted in global interconnects if interconnect length is shorter than a critical length, which is a constant for a given technology. For global interconnects with buffer insertion, the optimal width and spacing have analytical expressions and are constants for a given technology. For global interconnects without buffer insertion, the optimal width and spacing are dependent on both the technology parameters and interconnect length and can be computed numerically.     

Effects of temperature in deep-submicron global interconnect optimization in future technology nodes

The resistance of on-chip interconnects and the current drive of transistors are strongly temperature-dependent. As a result, the interconnect performance in Deep-Submicron technologies is affected by temperature in a substantial proportion. In this paper we evaluate thermal effects in global RLC interconnects and quantify their impact in a standard optimization procedure based on repeaters insertion. By evaluating the difference between a simple RC and an accurate RLC model, we show how the temperature induced increase of resistance may reduce the impact of inductance. We also project the evolution of such effects in future CMOS technologies, according to the semiconductor roadmap.     

一种多用户MIMO系统干扰对齐优化算法

干扰对齐技术可以获得干扰信道自由度的最佳值,从而有效改善系统的性能。在实际系统中干扰对齐技术通常采用迭代的方法进行预编码矩阵与干扰抑制矩阵的设计,而迭代方法都需要对发送预编码矩阵进行初始化处理。然而,目前大多数已有的研究所采用的初始化处理方法都忽略了干扰的影响。因此,在此基础上提出了一种基于新的初始化方法的优化算法,该方法在初始化预编码矩阵中既考虑了干扰信号也考虑了有用信号。首先,选取均方误差和最小化作为优化目标,然后利用正交三角（QR）分解将信道空间分为有用信号空间与干扰信号空间来进行预编码矩阵的初始化设计,经过反复迭代得到发送预编码矩阵与干扰抑制矩阵的最优解。理论分析和仿真结果表明,所提算法在收敛性、均方误差、和速率等方面都优于其他算法。     

Modeling the electrical effects of metal dishing due to CMP for on-chip interconnect optimization

A dishing model is developed to investigate the electrical effects of metal dishing in the damascene process, based on experimental data and physical analysis. A metric for dishing, the dishing radius, has been defined. A study utilizing this model shows that the impact of dishing on performance can be mitigated at both the process and design stages. More specifically, process improvement is most effective when the dishing radius is less than 50 /spl mu/m. During design, dishing effects can be suppressed by uniformly splitting a wide line into several narrower lines; the most beneficial number of line-splitting is between two and four from both efficiency and performance considerations.     

电力通信综合数据网市县互联优化方案

针对某市综合数据网市县互联链路现状,文章分析了目前市县互联链路存在的问题,阐述了优化原则,重点探讨并制定了市县骨干综合数据网互联优化方案。在实际应用中证明了这一方案的可行性。     

Design optimization of one-turn helix: a novel compliant off-chip interconnect

As the rapid advances in integrated circuit (IC) design and fabrication continue to challenge and push the electronic packaging technology, in terms of fine pitch, high performance, low cost, and good reliability, compliant interconnects show great potential for next-generation packaging. One-turn helix (OTH) interconnect, a compliant chip-to-next level substrate or off-chip interconnect, is proposed in this work, and this interconnect can facilitate wafer-level probing as well as wafer-level packaging without the need for an underfill. The interconnect has high mechanical compliance in the three orthogonal directions, and can accommodate the differential displacement induced by the coefficient of thermal expansion (CTE) mismatch between the silicon die and an organic substrate. The fabrication of the helix interconnect is similar to the standard IC fabrication, and the wafer-level packaging makes it cost effective. In this paper, we report the fabrication of an area array of helix interconnects on a silicon wafer. Also, we have studied the effect of interconnect geometry parameters on its mechanical compliance and electrical parasitics. Thinner and narrower arcuate beams with larger radius and taller post are found to have better mechanical compliance. However, it is found that structures with excellent mechanical compliance cannot have good electrical performance. Therefore, a trade off is needed for the design of OTH interconnect. An optimization technique using response surface methodology has been applied to select the optimal structure parameters. The optimal compliant OTH interconnect will have a total standoff height of about 100 /spl mu/m, a radius of about 35 /spl mu/m and a cross section area of about 430 /spl mu/m/sup 2/.     

Development of robust interconnect model based on design ofexperiments and multiobjective optimization

When designing an integrated circuit, it is important to take into consideration random variations arising from process variability. Traditional optimization studies on VLSI interconnect attempt to find the deterministic optimum of a cost function but do not take into account the effect of these random variations on the objective. We have developed an effective methodology based on TCAD simulation and design of experiments to optimize interconnect including the effects of process variations. The aim of the study is to search for optimum designs that both meet the performance specification and are robust with respect to process variations. A multiobjective optimization technique known as Normal Boundary Intersection is used to find evenly-spaced tradeoff points on the Pareto curve. Designers can then select designs from the curve without using arbitrary weighting parameters. The proposed methodology was applied to a 0.12 μm CMOS technology; optimization results are discussed and verified using Monte Carlo simulation     

Power-aware hold optimization for ASIC physical synthesis

Hold timing closure is an important milestone at the physical design phase of every Application Specific Integrated Circuit (ASIC). Many approaches have been proposed by different researchers and commercial Electronic Design Automation (EDA) providers to fix hold timing violations, but there has been no effort to study the impact of each technique on power consumption. Nowadays, the rise of low power applications demand keeps pushing for the invention of new power reduction techniques. In this paper, we presented a novel approach for power consumption reduction by reducing the power increase seen during the hold timing optimization. A sample of 100 industrial post-CTS designs from different applications and fabrication process technologies (from 180 nm to 28 nm) was used to measure the ratios of Δpower/Δhold_timing and Δarea/Δhold_timing of each technique. The ratios were calculated after legalization and global routing to include not only the power/area added directly by the hold optimization, but also the power/area increases induced indirectly by the additional timing fixes needed after placement legalization and routing repair. By considering the impact on power consumption and area increase of each technique while optimizing the design we have reduced substantially the power increase and the area overhead caused by the hold fixing. Experimental results show a power reduction of 7%, and an area reduction of 1% on average, with a beneficial impact on hold timing and a neutral impact on setup timing.