A 15/30-GHz Dual-Band Multiphase Voltage-Controlled Oscillator in 0.18- μm CMOS

A multiphase oscillator suitable for 15/30-GHz dual-band applications is presented. In the circuit implementation, the 15-GHz half-quadrature voltage-controlled oscillator (VCO) is realized by a rotary traveling-wave oscillator, while frequency doublers are adopted to generate the quadrature output signals at the 30-GHz frequency band. The proposed circuit is fabricated in a standard 0.18-mum CMOS process with a chip area of 1.1times1.0 mm². Operated at a 2-V supply voltage, the VCO core consumes a dc power of 52 mW. With a frequency tuning range of 250 MHz, the 15-GHz half-quadrature VCO exhibits an output power of -8 dBm and a phase noise of -112 dBc/Hz at 1-MHz offset frequency. The measured power level and phase noise of the 30-GHz quadrature outputs are -16 dBm and -104 dBc/Hz, respectively     

Dual-band ultra-wide tuning range CMOS voltage-controlled oscillator

A dual-band wide-tuning range LC CMOS voltage controlled oscillator (VCO) topology is proposed. Dual-band operation is realised by employing a double-tuned double-driven transformer as a resonator. The proposed approach eliminates MOS switches, which are typically used in multi-standard oscillators, and thus improves phase noise and tuning range characteristics. The concept is demonstrated through the design of an LC VCO in a standard 0.18 mum CMOS process. Two frequency bands are realised (2.4 and 6 GHz) with 740 MHz tuning range in the first band and 1.56 GHz tuning range in the second band. Operating from a 1.8 V supply, the VCO has a simulated phase noise of -119 dBc/Hz in the 2.4 GHz band and -110 dBc/Hz in the 6 GHz band at 600 KHz offset from the carrier     

A 1.8-V 2.4/5.15-GHz dual-band LCVCO in 0.18-/spl mu/m CMOS technology

A dual band, fully integrated, low phase-noise and low-power LC voltage-controlled oscillator (VCO) operating at the 2.4-GHz industrial scientific and medical band and 5.15-GHz unlicensed national information infrastructure band has been demonstrated in an 0.18-/spl mu/m CMOS process. At 1.8-V power supply voltage, the power dissipation is only 5.4mW for a 2.4-GHz band and 8mW for a 5.15-GHz band. The proposed VCO features phase-noise of -135dBc/Hz at 3-MHz offset frequency away from the carrier frequency of 2.74GHz and -126dBc/Hz at 3-MHz offset frequency away from 5.49GHz. The oscillator is tuned from 2.2 to 2.85GHz in the low band (2.4-GHz band) and from 4.4 to 5.7GHz in the high band (5.15-GHz band).     

Novel 53/106 GHz Dual-Band MMW LC Oscillator Implemented in SiGe BiCMOS Technology

In this Paper, we present a fully integrated millimeter wave LC voltage-controlled oscillator (VCO), which employs a novel topology, operating at dual-band frequency of 53.22 GHz-band and 106.44 GHz-band. The low-phase noise performance of ?107.3 dBc/Hz and ?106.1 dBc/Hz at the offset frequency of 600 kHz, ?111.8 dBc/Hz and ?110.6 dBc/Hz at the offset frequency of 1 MHz around 53.22 GHz and 106.44 GHz are achieved using IBM BiCMOS-6HP technology, respectively. Two tuning ranges, of 52.7 - 53.8 GHz and 105.4 - 107.6 GHz for the proposed LC VCO are obtained. The output voltage swing of this VCO is around 1.8 V_p-p at the operation frequency of 53.22 GHz and 0.45 V_p-p at 106.44 GHz; the total power consumption is about 16.5 mW. To our knowledge, this is the first oscillator which operates at dual-band frequency above 50 GHz with the best preformance.     

A fully integrated multi-band ED-mode pHEMT VCO using variable transformer and switched resonator

A systematic approach to the design of a reconfigurable LC-coupled voltage-controlled oscillator (VCO) is proposed in this article. The focus is on the choice of the reactive elements of the resonance tank which are most suitable to switch to the desired oscillation frequencies. The optimum Q of the tank will be determined by the selected component. We report a 0.5-µm enhancement–depletion (ED) mode pHEMT (HEMT, high-electron mobility transistor) multiple-frequency VCO, and the generation of multiple frequencies are achieved using switched resonator topology. LC-tank circuit is built by square transformers. By careful selection of the reactive elements, evenly distributed results showed at each designed band. The multi-band ED-mode pHEMT VCO showed the output power of ?4.7?dBm for 2?GHz band, ?6.67?dBm for 3.86?GHz band and ?5.9?dBm for 4.5?GHz band, respectively. The phase noises at 1?MHz offset frequency from carrier were ?112.8?dBc/Hz for 2?GHz, ?105?dBc/Hz for 3.86?GHz and ?103.3?dBc/Hz for 4.5?GHz, respectively. The total chip size is only 1.17?×?0.83?mm².     

A 5.9-GHz voltage-controlled ring oscillator in 0.18-/spl mu/m CMOS

This paper presents the design of three- and nine-stage voltage-controlled ring oscillators that were fabricated in TSMC 0.18-/spl mu/m CMOS technology with oscillation frequencies up to 5.9 GHz. The circuits use a multiple-pass loop architecture and delay stages with cross-coupled FETs to aid in the switching speed and to improve the noise parameters. Measurements show that the oscillators have linear frequency-voltage characteristics over a wide tuning range, with the three- and nine-stage rings resulting in frequency ranges of 5.16-5.93 GHz and 1.1-1.86 GHz, respectively. The measured phase noise of the nine-stage ring oscillator was -105.5 dBc/Hz at a 1-MHz offset from a 1.81-GHz center frequency, whereas the value for the three-stage ring oscillator was simulated to be -99.5 dBc/Hz at a 1-MHz offset from a 5.79-GHz center frequency.     

4GHz级频率综合器下单片低相位噪声CMOS电感电容压控振荡器的设计

基于0.18μm RF CMOS工艺,采用双端调谐结构实现了一种可应用于WLAN的二次变频收发机的压控振荡器.其输出频率范围可以覆盖收发机所需4.1～4.3GHz的频段,其最大调谐范围为500MHz.在距中心频率4.189GHz为4MHz处的相位噪声为-117dBc/Hz,500kHz处为-107dBc/Hz.输出信号抖动的均方根值为4.423ps,输出功率为-8.68dBm.     

A fully integrated 5.8 GHz U-NII band 0.18-/spl mu/m CMOS VCO

A fully integrated 5.8 GHz CMOS L-C tank voltage-controlled oscillator (VCO) using a 0.18-/spl mu/m 1P6M standard CMOS process for 5 GHz U-NII band WLAN application is presented. The VCO core circuit uses only PMOS to pursue a better phase noise performance since it has less 1/f noise than NMOS. The measurement is performed by using a FR-4 PCB test fixture. The output frequency of the VCO is from 5860 to 6026 MHz with a 166 MHz tuning range and the phase noise is -96.9 dBc/Hz at 300 kHz (or -110 dBc/Hz at 1 MHz) with V ctrl = 0 V. The power consumption of the VCO excluding buffer amplifiers is 8.1 mW at V/sub DD/ = 1.8 V and the output power is -4 dBm.     

基于开关电容阵列的5.8GHz全集成LC压控振荡器设计

采用TSMC 0.18μm 1P6M RF CMOS工艺,完成了一种基于开关电容阵列的全集成LC压控振荡器的设计.版图后仿真结果表明,在1.8V电源电压下,电路核心功耗约为7.2mW,中心振荡频率为5.8GHz,在偏离中心频率1MHz处,该VCO的相位噪声为-121.8dBc/Hz,调谐范围为10.2%,满足交通专用短程通信系统的频段要求.     

A novel complementary Colpitts differential CMOS VCO with low phase noise performance

A low phase noise Ka-band CMOS voltage-controlled oscillator is proposed in this paper. A new complementary Colpitts structure was adopted in a 0.18-μm CMOS process to achieve differential-ended outputs, low phase-noise performance, and low-power consumption. The designed VCO oscillates from 29.8 to 30 GHz with 200 MHz tuning range. The measured phase noise at 1-MHz offset is −109 dBc/Hz at 30 GHz and −105.5 dBc/Hz at 29.8 GHz. The power consumption of VCO is only 27 mW. In addition, compared with the published papers, the proposed CMOS VCO achieves the best figure of merit (FOM) of −185 dB at 29.95-GHz band.     

一种宽带正交振荡器中子频带的精确设计方法

设计了一个应用于3.5 GHz频段锁相环的低电压宽带正交压控振荡器。通过对开关电容阵列进行功能划分和优化设计,从而精确地将锁相环的频道点逐一映射到了振荡器的子频带中,进而消除了频道切换时子频带的选择过程时间。该芯片采用0.18μm CMOS工艺实现,测试结果表明:振荡器的频率覆盖范围从3.04~3.58 GHz,并且所有的子频带均一一准确地覆盖了目标频道点;调谐增益从86 MHz/V变化至132 MHz/V,其平均值仅比设计值高6%;最高子频带的中心频率为3.538 GHz,其偏离载波1 MHz处的相位噪声为-121.6 dBc/Hz;在1.2 V电源电压下,振荡器核心的功耗约为14 mW。     

一种用于双波段GPS接收机的低功耗宽带CMOS频率合成器

提出了一种用于双波段GPS接收机的宽带CMOS频率合成器.该GPS接收机芯片已经在标准O.18μm射频CMOS工艺线上流片成功,并通过整体功能测试.其中压控振荡器可调振荡频率的覆盖范围设计为2～3.6GHz,覆盖了L1,L2波段的两倍频的频率点.并留有足够的裕量以确保在工艺角和温度变化较大时能覆盖所需频率.芯片测试结果显示,该频率综合器在L1波段正常工作时的功耗仅为5.6mW,此时的带内相位噪声小于-82dBc/Hz,带外相位噪声在距离3.142G载波1M频偏处约为-112dBc/Hz,这些指标很好地满足了GPS接收芯片的性能要求.     

Bottom-series coupled quadrature VCO using the inductive gate voltage boosting technique

This article presents a new low-voltage bottom-series coupled quadrature voltage-controlled oscillator (QVCO), which consists of two n-core cross-coupled VCOs with the bottom-series coupling transistors. The low-voltage operation is obtained via an inductive gate voltage boosting technique. The proposed CMOS QVCO has been implemented with the TSMC 0.18?µm CMOS technology and the die area is 0.897?×?0.767?mm². At the supply voltage of 0.7?V, the total power consumption is 1.5?mW. The free-running frequency of the QVCO is tuneable from 3.77 to 4.12?GHz as the tuning voltage is varied from 0.0 to 0.7?V. The measured phase noise at 1?MHz frequency offset is ?123.35?dBc/Hz at the oscillation frequency of 4.12?GHz and the figure of merit of the proposed QVCO is ?193.5?dBc/Hz.     

A Dual-Band CMOS Voltage-Controlled Oscillator Implemented With Dual-Resonance LC Tank

A new fully integrated, dual-band CMOS voltage controlled oscillator (VCO) is presented. The VCO is composed of n-core cross-coupled Colpitts VCOs and was implemented in 0.18 $mu$m CMOS technology with 0.8 V supply voltage. The circuit allows the VCO to operate at two resonant frequencies with a common LC tank. The VCO has two control inputs, one for continuous control of the output frequency and one for band switching. This VCO is configured with 5 GHz and 12 GHz frequency bands with differential outputs. The dual-band VCO operates in 4.78–5.19 GHz and 12.19–12.61 GHz. The phase noises of the VCO operating at 5.11 and 12.2 GHz are ${-}117.16$ dBc/Hz and ${-}112.15$ dBc/Hz at 1 MHz offset, respectively, while the VCO draws 3.2/2.72 mA and 2.56/2.18 mW consumption at low/high frequency band from a 0.8 V supply.      

8.64-11.62 GHz CMOS VCO and divider in a zero-IF 802.11a/b/g WLAN and Bluetooth application

A fully integrated VCO and divider implemented in SMIC 0.13-μm RFCMOS 1P8M technology with a 1.2 V supply voltage is presented.The frequency of the VCO is tuning from 8.64 to 11.62 GHz while the quadrature LO signals for 802.11a WLAN in 5.8 GHz band or for 802.11b/g WLAN and Bluetooth in 2.4 GHz band can be obtained by a frequency division by 2 or 4,respectively.A 6 bit switched capacitor array is applied for precise tuning of all necessary frequency bands.The testing results show that the VCO has a phas...     

Wide tuning-range CMOS VCO based on a tunable active inductor

In this paper, a wide tuning-range CMOS voltage-controlled oscillator (VCO) with high output power using an active inductor circuit is presented. In this VCO design, the coarse frequency is achieved by tuning the integrated active inductor. The circuit has been simulated using a 0.18-µm CMOS fabrication process and presents output frequency range from 100 MHz to 2.5 GHz, resulting in a tuning range of 96%. The phase noise is –85 dBc/Hz at a 1 MHz frequency offset. The output power is from –3 dBm at 2.55 GHz to +14 dBm at 167 MHz. The active inductor power dissipation is 6.5 mW and the total power consumption is 16.27 mW when operating on a 1.8 V supply voltage. By comparing this active inductor architecture VCO with general VCO topology, the result shows that this topology, which employs the proposed active inductor, produces a better performance.     

Rotary traveling-wave oscillator design using 0.18 μm CMOS

A rotary traveling-wave oscillator (RTWO) targeted at 5.8 GHz band operation is designed and fabricated using standard 0.18 μm CMOS technology. Both simulation and measurement results are presented. The chip size including pads is 1.5 × 1.5 mm2. The measured output power at a frequency of 5.285 GHz is 6.68 dBm, with a phase noise of-102 dBc/Hz at 1 MHz offset from the carrier.     

A 5-GHz low phase noise differential colpitts CMOS VCO

A low noise 5-GHz differential Colpitts CMOS voltage-controlled oscillator (VCO) is proposed in this letter. The Colpitts VCO core adopts only PMOS in a 0.18-/spl mu/m CMOS technology to achieve a better phase noise performance since PMOS has lower 1/f noise than NMOS. The VCO operates from 4.61 to 5 GHz with 8.3% tuning range. The measured phase noise at 1-MHz offset is -120.42 dBc/Hz at 5 GHz and -120.99 dBc/Hz at 4.61 GHz. The power consumption of the VCO core is only 3 mW. To the authors' knowledge, this differential Colpitts CMOS VCO achieves the best figure of merit (FOM) of 189.6 dB at 5-GHz band.     

A spur-reduction technique for a 5-GHz frequency synthesizer

A spur-reduction technique is presented to achieve low reference spurs for a 5-GHz frequency synthesizer. A dual-path control scheme incorporated with a pair of the proposed smoothed varactors reduces the gain of voltage-controlled oscillator to less than 15 MHz/V, attenuates the spurious tones, and shortens the simulated settling time by 56%. In, addition, a digital frequency-calibration circuit is used to enlarge the tuning range to overcome process variations. A 5-GHz frequency synthesizer has been fabricated for verification in a 0.18-/spl mu/m CMOS process. It exhibits phase noise of -79 and -113 dBc/Hz at 10-kHz and 1-MHz offset, respectively. The reference spur level of -74 dBc is achieved by using a second-order loop filter. The overall tuning range is 16.3% and power consumption is 36 mW from a 1.8-V supply. The total switching time including digital frequency calibration takes no more than 110 /spl mu/s.     

A 1.78–3.05?GHz fractional-N frequency synthesizer with power reduced multi-modulus divider

Nowadays, multi-band frequency synthesizers are very popular for their compatibility, which lowers the chip cost. In this article, a low power 2.4?GHz broadband fractional-N frequency synthesizer based on ???C?? modulation is presented. A novel power reduced multi-modulus divider based on 2/3 divider cells is presented. The ??mod?? signals are employed to dynamically control the current of the end-of-cycle logic blocks in 2/3 divider cells. When the end-of-cycle logic blocks have no contribution to the divider operation, they are turned off to save power. The saved power is more than 30% in the desired division ratio range. A dual-band voltage controlled oscillator with switched capacitor arrays is designed to cover a wide tuning range. Other circuits such as phase frequency detector, charge pump and loop filter are also integrated on the chip. The whole frequency synthesizer has been fabricated in Chartered 0.18???m RF CMOS process. Tested results show it covers the tuning range from 1.78 to 3.05?GHz, with phase noise smaller than ?85 dBc/Hz at 100?kHz offset, and smaller than ?115 dBc/Hz at 3?MHz offset. Its power consumption is only 9.2?mW under 1.8?V supply voltage, and the chip occupies an area of 1.2?mm?×?1.3?mm.