SiGe HBT功率放大器基极偏置电阻的优化

模拟了基极偏置电阻对功率放大器参数的影响.在兼顾效率、S参数、电压驻波比、功率增益及稳定性等特性的同时,得到了三阶交调信号幅度为最小值时的优化基极偏置电阻.模拟结果表明,一个优化的基极偏置电阻,不仅能使功率放大器的直流偏置点不受影响,三阶交调信号幅度最小,功率增益平坦度得到改善,而且S参数也能满足功放的要求.     

基于输入分解输出匹配的多态自检电路进化设计

针对进化方法在多态自检电路设计方面存在的扩展性问题,该文提出了一种基于输入分解输出匹配的多态自检电路进化设计方法。该方法将原始电路分解为可进化生成部分和固定部分,由此减少待进化设计电路的输入个数以及适应度评价时真值表输入输出组合数量,从而降低电路进化复杂度;在适应度评价阶段,当电路输出位与理想输出匹配度小于1/2时,通过添加非门的形式提高候选电路适应度和种群多样性,防止最优结构的丢失。进化设计实验将多态门和普通门相结合,进行了两种多态自检加法器的设计。结果表明,与传统多态自检电路进化设计方法相比所提方法进化代数分别减少了47.9%和89.1%,单个测试参量下故障覆盖率分别提高了75.7%和79.7%,具有收敛速度快、扩展性好、故障覆盖率高的优点。     

一种学习放大电路和反馈基本原理的新方法

在“模拟电子技术基础”课程中,对放大电路和反馈基本原理的理解是难点。常规的授课思路是分析的学习方法,给定一个放大电路和反馈,然后分析各元件的作用和反馈的类型。本文介绍一种新的学习方法,从三极管开始逐个增加元件,直至一个满足要求的电路,这种基于设计的新方法有利于学生的理解。     

低功耗CMOS射频低噪声放大器的设计

介绍了一个针对无线通讯应用的2.1 GHz低噪声放大器(LNA)的设计.该电路采用Chartered 0.25 μm CMOS工艺,电源电压为2.5 V,设计中使用了多个电感,详述了设计过程并给出了优化仿真结果. 模拟结果显示,该电路能提供21.63 dB的正向增益(S21),功耗为12.5 mW,噪声系数为2.1 dB,1 dB压缩点为-19.054 1 dBm.芯片面积为0.8 mm×0.6 mm.测试结果达到了设计指标,一致性良好.     

差模电压放大倍数的四种分析方法

差分放大电路的主要作用是抑制共模电平和放大差模信号,因而具有良好的温度和噪声特性,是集成运放的重要基础。为了更好地对差模放大倍数进行分析,文章总结出三种新的解法,即直接求解法、GmRout方法和戴维宁求解,可合计得到四种分析方法。便于学生有机地把电路理论的知识运用到模拟电路分析中,加深对差分放大电路的理解。     

一种输出匹配可调的、高线性度宽带功率放大器

采用自适应偏置技术和有源电感实现了一款输出匹配可调的、高线性度宽带功率放大器(PA)。自适应偏置技术抑制了功放管直流工作点的漂移,提高了PA的线性度。有源电感参与输出匹配,实现了输出匹配可调谐,该策略可调整因工艺偏差、封装寄生造成的输出匹配退化。利用软件ADS对电路进行验证,结果表明,在4 GHz频率下,输入1dB压缩点(Pin 1dB)为-7dBm,输出1dB压缩点(Pout 1dB)为11dBm,功率附加效率(PAE)为8.7%。在3.1GHz~4.8 GHz频段内,增益为(20.3±1.1)d B,输入、输出的回波损耗均小于-10dB。     

A novel structure of the fully differential CMOS amplifier with symmetric active load

In this article, we propose a novel general structure of a linear symmetric fully differential voltage amplifier with a symmetric output. It is applicable to all sets of complementary component pairs such as BJT, JFET and MOSFET. We demonstrate the superiority of the proposed circuit in comparison with the state-of-the-art solutions. The characteristics are illustrated in both frequency and time domains, and a comparison is given between the proposed amplifier and the traditional differential amplifier with a current mirror as an active load for the same set of complementary components in CMOS equally sized W/L = 150/3 technology. The static voltage transfer characteristic of the proposed amplifier has an extremely small linearity error. The deviation from the linear characteristics is less than 0.018 mV for the amplitude of the output differential voltage of 1 Vpp. The common-mode gain by symmetric output is negligible because the proposed structure is fully symmetric. The simulation results demonstrate the efficiency of the proposed amplifier.     

A multi-channel analog IC for in vitro neural recording

Recent work in the field of neurophysiology has demonstrated that, by observing the firing characteristic of action potentials (AP) and the exchange pattern of signals between neurons, it is possible to reveal the nature of "memory" and "thinking" and help humans to understand how the brain works. To address these needs, we developed a prototype fully integrated circuit (IC) with micro-electrode array (MEA) for neural recording. In this scheme, the microelectrode array is composed by 64 detection electrodes and 2 reference electrodes. The proposed IC consists of 8 recording channels with an area of 5 × 5 mm². Each channel can operate independently to process the neural signal by amplifying, filtering, etc. The chip is fabricated in 0.5-μ m CMOS technology. The simulated and measured results show the system provides an effective device for recording feeble signal such as neural signals.     

高效率基站Doherty功放的研究

随着无线通信系统的发展,人们对数据和信息的需求在不断的增加。功率放大器作为通信系统中最重要的模块之一,功放的性能对整个系统性能的影响至关重要。面对高速增长的移动数据业务和频谱资源短缺的威胁,高峰均比（PAR）的调制方式不断出现,如OFDM调制方式,这就对功放的线性度提出了较高的要求。为了保证信号的线性度,一般采用功率回退的方法来实现。以NXP公司的140W晶体管为模型,在ADS仿真软件中设计对称Doherty仿真电路。设计完成的功放电路能够在6dB功率范围内保持高效率工作。     

A low power dual-band multi-mode RF front-end for GNSS applications

A CMOS dual-band multi-mode RF front-end for the global navigation satellite system receivers of all GPS,Bei-Dou,Galileo and Glonass systems is presented.It consists of a reconfigurable low noise amplifier(LNA),a broadband active balun,a high linearity mixer and a bandgap reference(BGR) circuit.The effect of the input parasitic capacitance on the input impedance of the inductively degenerated common source LNA is analyzed in detail.By using two different LC networks at the input port and the switched cap...     

A Low Complexity Reconfigurable DCT Architecture to Trade off Image Quality for Power Consumption

In this paper we present a low complexity discrete cosine transform (DCT) architecture based on computation re-use in vector-scalar product. 1-D DCT operation is expressed as additions of vector-scalar products and basic common computations are identified and shared to reduce computational complexity in 1-D DCT operation. Compared to general distributed arithmetic based DCT architecture, the proposed DCT shows 38% of area and 18% of power savings with little performance degradation. We also propose an efficient method to trade off image quality for computational complexity. The approach is based on the modification of DCT bases in bit-wise manner and different computational complexity/image quality trade-off levels are suggested. Finally, based on the above approaches, we propose a low complexity DCT architecture, which can dynamically reconfigure from one trade-off level to another. The reconfigurable DCT architecture can achieve power savings ranging from 28% to 56% for 3 different trade-off levels.

The Concept of Operational Rank Extractor

An operational rank extractor (ORE) is introduced in this paper as an operational amplifier having rank extractors at its inputs. This versatile building block can implement a variety of nonlinear transfer functions such as a dead-zone amplifier, a limiter, a full-wave rectifier, and a tri-state comparator (including hysteretic behavior). A 6-input circuit has been implemented in a 2 m CMOS process. The total silicon area is 460 × 100m², and the circuit dissipates 0.7 mW from a single 5 V supply. Various circuit configurations are analyzed theoretically, and experimental results are also provided.     

驱动功率放大器微分叠加技术的分析与实现

本文提出了一种新的统一表达式,用于分析微分叠加技术在大信号和小信号时的效果。根据该表达式,微分叠加技术在大信号和小信号时有不同的优化方法。在0.13μm工艺下实现了一种用于可配置射频发射机的使用大信号微分叠加技术的驱动功率放大器。该驱动放大器兼容900 MHz频段的GSM信号和1.95 GHz频段的WCDMA信号,其增益范围可达44 dB,增益步长为2 dB。测试结果表明,该发射机的总体OIP3可达19 dBm,其输出1 dB压缩点可达7.5 dBm。     

900MHz 低噪声功率放大器的仿真设计

低噪声放大器的特点是噪声系数小而输出功率较小,功率放大器的特点是输出功率较大而噪声系数较大。为了实现噪声系数小而输出功率较大的放大器,本文结合低噪放和功率放大器的设计方法,设计了一种用于谐波雷达发射机的低噪声功率放大器,该放大器由两级放大器组成,前级主要实现低噪声功能,后级主要实现功率增益。通过优化仿真设计,该放大器达到了比较理想的结果,具有良好的线性度和二次谐波抑制能力。     

一种71dB动态范围的低功耗可编程增益放大器

本文实现了一款应用于电力线通信的可编程增益放大器(PGA)。采用闭环直接耦合方式,动态范围为71dB,调节精度为1dB。为了优化功耗和面积,本文提出了一种新的电阻阵列。该设计在SMIC0.18μm工艺下仿真,结果表明:在35dB增益下输入参考噪声为20nV/姨Hz;输出电压峰峰值为1V时,THD达到-68dB;最大增益误差为0.11dB;在1.8V的供电电压下,功耗为1mA。     

An electronically tunable current-mode quadrature oscillator using PCAs

This article presents a new realisation of active RC sinusoidal oscillator with electronically tunable condition and frequency of oscillation (FO). As compared to the class of three resistors, two capacitors (3R-2C)-based canonic oscillators, the circuit proposed here uses only two resistors and two capacitors as the passive components and still provides non-interactive tuning laws for the condition of oscillation and the FO. The proposed circuit employs new bipolar programmable current amplifier as the active building block and is capable of simultaneously providing two explicit quadrature current outputs. SPICE simulation results have been included to verify the workability of the circuit as an oscillator and the tuning range of the FO.     

1.6GHz高线性高效率驱动放大器设计

在0.35μm射频CMOS工艺下,设计了一种可应用于发射终端的1.6 GHz驱动放大器.该放大器采用两级结构,第一级采用共源共栅结构,其中共源输入由两个分别工作在AB类和B类状态的并联放大管构成,提高了放大器的线性度和效率.第二级采用工作在B类状态的共源放大结构,进一步提高了驱动放大器的性能.仿真结果显示,放大器的最大输出三阶交调点为17.3 dBm,功率增加效率为57%,输出饱和功率为18.5 dBm,功率增益为26 dB,在3.3 V电压下总的电流消耗为5.4 mA.     

一种高压电晕检测系统的设计

在当今电晕放电现象检测研究领域中,多数检测方法对检测环境有严苛要求且检测过程中易产生较大误差。针对这一问题,设计了一种高压电晕检测系统,该系统通过对电晕放电产生的电磁波进行检测,由观测波形来判断电晕放电是否发生。重点设计了低噪声放大器和差分放大器等前端硬件部分,另外简单介绍了系统中信号采集和数字信号处理等后端部分,最后检测平台经现场测试具有误差小且能够实现200 m以内电晕放电检测的目标。     

Voltage difference transresistance amplifier and its application: floating FDNR simulator circuit

In this article, a new active building component with electronically tunable transresistive block, voltage difference transresistance amplifier, and its floating frequency dependent negative resistor simulator circuit application is presented. The simulator circuit is shown to operate using single active building block with two grounded passive components, to be electronically tunable over its value which is controlled by an independent current source, not to require any conditions of component matching and to have good sensitivity performance with respect to tracking errors. To examine functionality of the design, a CRD band-pass filter example is given.

Numerous simulation program with integrated circuit emphasis (SPICE) simulations are performed and depicted through the article to verify validity of the study. Taiwan semiconductor manufacturing company (TSMC) 0.18 µm complementary metal oxide semiconductor technology parameters are used through simulations.