Dynamic sleep transistor and body bias for active leakage power control of microprocessors

In order to manage the active power consumption of high-performance digital designs, active leakage control techniques are required to provide significant leakage power savings coupled with fast time constants for entering and exiting idle mode. In this paper, dynamic sleep transistors and body bias are used in conjunction with clock gating to control active leakage for a 32-bit integer execution core in 130-nm CMOS technology. Measurements on pMOS sleep transistor reveal that lowest-leakage state is reached in less than 1 /spl mu/s, resulting in 37/spl times/ reduction in leakage power, while reactivation of block is achieved in less than two clock cycles. PMOS body bias reduces leakage power by 2/spl times/ with no performance penalty, and similar reactivation time. Power measurements at 4 GHz, 1.3 V, 75/spl deg/C demonstrate 8% total power reduction using dynamic body bias and 15% power reduction using a pMOS sleep transistor, for a typical activity profile.     

High-performance low-power CMOS memories using silicon-on-sapphire technology

Complementary MOS silicon-on-sapphire inverters fabricated using silicon-gate technology and 5-/spl mu/m channel-length devices has achieved nanosecond propagation delays and picojoule dynamic power-x delay products. In addition to high switching speed and low dynamic power, inverters with low leakage currents and therefore low quiescent power have been obtained. Two complex CMOS/SOS memories that realize the performance attributes of the individual inverters have been fabricated. An aluminium-gate 256-bit fully decoded static random-access memory features a typical access time of 50 ns at 10 V with a power dissipation of 0.4 /spl mu/W/bit (quiescent) and 10 /spl mu/W/bit (dynamic). The access time at 5 V is typically 95 ns. A silicon-gate 256-bit dynamic shift register features operation at clock signals of 200 MHz at 10 V and 75 MHz at 5 V. The dynamic power dissipation at 50 MHz and 5 V is typically 90 /spl mu/W/bit.     

Design and simulation of an ultra-low power high performance CMOS logic: DMTGDI

An ultra-low power, high speed dual mode CMOS logic family called DMTGDI is introduced. This logic family takes over and improves main characteristics of Gate Diffusion Input (GDI) and Dual Mode Logic (DML). Simulations have been performed in 90 nm CMOS on a single bit full adder. DMTGDI shows 60% performance improvement over conventional DML, and significant reduction of power-delay product (PDP), of about 95% in static mode, and 75% in dynamic mode. Monte Carlo simulations reveal that DMTGDI is more robust under process variation comparing to conventional DML. Post layout simulation demonstrates negligible effect of parasitic elements on performance of the single bit adder.     

一种静态电路兼容的4GHz 64位动态加法器设计

设计了一个与静态电路兼容的64位动态加法器,采用嵌入逻辑的动态触发器,以及多相位时钟技术,实现了与上、下级静态电路的接口.在加法器内部采用稀疏先行进位策略平衡逻辑路径长度以降低内部负载,提高性能.在STMicro90nmCMOS工艺下,该加法器可工作在4GHz时钟下,功耗45.9mW.     

nMOS reversible energy recovery logic for ultra-low-energyapplications

We propose a new fully reversible adiabatic logic, nMOS reversible energy recovery logic (nRERL), which uses nMOS transistors only and a simpler 6-phase clocked power. Its area overhead and energy consumption are smaller, compared with the other fully adiabatic logics. We employed bootstrapped nMOS switches to simplify the nRERL circuits. With the simulation results for a full adder, we confirmed that the nRERL circuit consumed substantially less energy than the other adiabatic logic circuits at low-speed operation. We evaluated a test chip implemented with 0.8-μm CMOS technology, which included a chain of nRERL inverters integrated with a clocked power generator. The nRERL inverter chain of 2400 stages consumed the minimum energy at V_dd=3.5 V at 55 kHz, where the adiabatic and leakage losses are about equal, which is only 4.50% of the dissipated energy of its corresponding CMOS circuit at V_dd=0.9 V. In conclusion, nRERL is more suitable than the other adiabatic logic circuits for the applications that do not require high performance but low energy consumption     

A 0.5 V 320 MHz 8 bit×8 bit pipelined multiplier in 130 nm CMOS process

This paper presents an 8×8 bit pipelined multiplier operating at 320 MHz under 0.5 V supply voltage. Using PMOS forward body bias technique, the modified full adder and the new D flip-flop with synchronous output are combined and implemented in the proposed pipelined multiplier to achieve high operation speed at supply voltages as low as 0.5 V. The proposed pipelined multiplier is fabricated in 130 nm CMOS process. It operates up to 320 MHz and the power consumption is only 1.48 mW at 0.5 V. Moreover, the power consumption of the proposed pipelined multiplier at 0.5 V is reduced over 5.7 times than that of the traditional architecture at 1.2 V. Thus, the proposed 8×8 bit pipelined multiplier is suitable for SoC and dynamic voltage frequency scaling applications.     

Design and analysis of low power high-speed 1-bit full adder cells for VLSI applications

This paper presents a low power and high speed two hybrid 1-bit full adder cells employing both pass transistor and transmission gate logics. These designs aim to minimise power dissipation and reduce transistor count while at the same time reducing the propagation delay. The proposed full adder circuits utilise 16 and 14 transistors to achieve a compact circuit design. For 1.2 V supply voltage at 0.18-μm CMOS technology, the power consumption is 4.266 μW was found to be extremely low with lower propagation delay 214.65 ps and power-delay product (PDP) of 0.9156 fJ by the deliberate use of CMOS inverters and strong transmission gates. The results of the simulation illustrate the superiority of the newly designed 1-bit adder circuits against the reported conservative adder structures in terms of power, delay, power delay product (PDP) and a transistor count. The implementation of 8-bit ripple carry adder in view of proposed full adders are finally verified and was observed to be working efficiently with only 1.411 ns delay. The performance of the proposed circuits was examined using Mentor Graphics Schematic Composer at 1.2 V single ended supply voltage and the model parameters of a TSMC 0.18-μm CMOS.     

Delay and power monitoring schemes for minimizing power consumption by means of supply and threshold voltage control in active and standby modes

This paper describes newly developed delay and power monitoring schemes for minimizing power consumption by means of the dynamic control of supply voltage V/sub DD/ and threshold voltage V/sub TH/ in active and standby modes. In the active mode, on the basis of delay monitoring results, either VDD control or VTH control is selected to avoid any oscillation problem between them. In V/sub DD/ control, on the basis of delay monitoring results, VDD is adjusted so as to be maintained at the minimum value at which the chip is able to operate for a given clock frequency. In V/sub TH/ control, on the basis of power monitoring results, VTH is adjusted so as to maintain a certain switching current I/sub SW//leakage current I/sub LEAK/ ratio known to indicate minimum power consumption. In the standby mode, the precision of power monitoring (which detects optimum body bias by comparing subthreshold current I/sub SUBTH/ to substrate current I/sub SUB/) is improved by taking into consideration both the effects of lowering V/sub DD/ and the effects of the presence of gate-oxide leakage current. Experimental results with a 90-nm CMOS device indicate that use of the proposed power monitoring results in the successful minimizing of power consumption. It does so by making it possible to: 1) maintain the I/sub SW//ILEAK ratio in the active mode and 2) detect optimum body bias conditions (I/sub SUBTH/=ISUB) within an error of less than 20% with respect to actual minimum leakage current values in the standby mode.     

Carry-select adder using single ripple-carry adder

Instead of using dual carry-ripple adders, a carry select adder scheme using an add-one circuit to replace one carry-ripple adder requires 29.2% fewer transistors with a speed penalty of 5.9% for bit length n=64. If speed is crucial for this 64 bit adder, then two of the original carry-select adder blocks can be substituted by the proposed scheme with a 6.3% area saving and the same speed     

A novel approach to high-level switching activity modeling withapplications to low-power DSP system synthesis

We address high-level synthesis of low-power digital signal processing (DSP) systems by using efficient switching activity models. We present a technology-independent hierarchical scheme that can be easily integrated into current communications/DSP CAD tools for comparing the relative power/performance of two competing DSP designs without specific knowledge of transistor-level details. The basic building blocks considered for such systems are a full adder, a half adder, and a one-bit delay. Estimates of the switching activity at the output of these primitives are used to model the activity in more complex building blocks of DSP systems. The presented hierarchical method is very fast and simple. The accuracy of estimates obtained using the proposed approach is shown to be within 4% of the results obtained using extensive bit-level simulations. Our approach shows that the choice of multiplier/multiplicand is important when using array multipliers in a datapath. If the input signal with smaller mean square value is chosen as the multiplicand, almost 20% savings in switching activity can be achieved. This observation is verified by an analog simulation using a 16 × 16 bit array multiplier implemented in a 0.6-μ process with 3.3 V supply voltage     

A versatile function generator chip implemented in an I/SUP 2/L gate array

A mask-programmable I/SUP 2/L gate array is used to implement a versatile function generator chip which employs a 9 bit input data set to generate a 9 bit digital ramp. The chip utilizes a novel ripple adder design that uses only eight I/SUP 2/L inverters per full adder and requires only on I/SUP 2/L gate delay for carry propagation per bit. The ramp can wobbulate between an initial and a final frequency or have a constant frequency. The initial and final frequencies, the wobbulation rate, the ramp amplitude and frequency, and the wobbulation mode are all controlled from the input data. The output may also be selected as a rectangular wave with variable duty cycle. Typical input data setup and hold times of about 75 ns each were obtained for this design. A gate utilization factor ~95 percent has been achieved in programming the gate array.     

A novel yield optimization technique for digital CMOS circuits design by means of process parameters run-time estimation and body bias active control

This work presents a novel approach to optimize digital integrated circuits yield referring to speed, dynamic power and leakage power constraints. The method is based on process parameter estimation circuits and active control of body bias performed by an on-chip digital controller. The associated design flow allows us to quantitatively predict the impact of the method on the expected yield in a specific design. We present the architecture scheme, the theoretical foundation, the estimation circuits used, and two application case studies, referring to an industrial 0.13-/spl mu/m CMOS process data. The approach results to be remarkably effective at high operating temperature. In the presented case study, initial yields below 14% are improved to 86% by using a single controller and a single set of estimation circuits per die.     

A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology With Integrated Power Management

This paper introduces a high-performance voltage-scalable SRAM design in a 32 nm strain-enhanced high-k + metal-gate logic CMOS technology. The 291 Mb SRAM design features a 0.171 ?m² six-transistor bitcell that supports a broad range of operating voltages for low-power and high-frequency embedded applications. The tileable 128 kb SRAM subarray achieves 72% array efficiency with 4.2 Mb/mm² bit density, and consumes 5 mW of leakage power at the supply voltage of 1 V. The design provides 4 GHz and 2 GHz of operating frequencies at the supply voltages of 1.0 V and 0.8 V, respectively. The integrated power management scheme features close-loop memory array leakage control, floating bitline, and wordline driver sleep transistor, resulting in a 58% reduction in subarray leakage power consumption.     

基于多数决定逻辑非门的低功耗全加器设计

全加器是算术运算的基本单元,提高一位全加器的性能是提高运算器性能的重要途径之一。首先提出多数决定逻辑非门的概念和电路设计,然后提出一种基于多数决定逻辑非门的全加器电路设计。该全加器仅由输入电容和CMOS反向器组成,较少的管子、工作于极低电源电压、短路电流的消除是该全加器的三个主要特征。对这种新的全加器,用PSpice进行了晶体管级模拟。结果显示,这种新的全加器能正确完成加法器的逻辑功能。     

Application of source biasing technique for energy efficient DECODER circuit design: memory array application

Researchers have proposed many circuit techniques to reduce leakage power dissipation in memory cells.If we want to reduce the overall power in the memory system,we have to work on the input circuitry of memory architecture i.e.row and column decoder.In this research work,low leakage power with a high speed row and column decoder for memory array application is designed and four new techniques are proposed.In this work,the comparison of cluster DECODER,body bias DECODER,source bias DECODER,and source coupling DECODER are designed and analyzed for memory array application.Simulation is performed for the comparative analysis of different DECODER design parameters at 180 nm GPDK technology file using the CADENCE tool.Simulation results show that the proposed source bias DECODER circuit technique decreases the leakage current by 99.92％ and static energy by 99.92％ at a supply voltage of 1.2 V.The proposed circuit also improves dynamic power dissipation by 5.69％,dynamic PDP/EDP 65.03％ and delay 57.25％ at 1.2 V supply voltage.     

一种适用于通信系统的异步加-选择-比较器

介绍了一种适用于Viterbi解码器的异步ACS(加法器-比较器-选择器)的设计.它采用异步握手信号取代了同步电路中的整体时钟.给出了一种异步实现结构的异步加法单元、异步比较单元和异步选择单元电路.采用全定制设计方法设计了一个异步4-bit ACS,并通过0.6μm CMOS工艺进行投片验证.经过测试,芯片在工作电压5V,工作频率20MHz时的功耗为75.5mW.由于采用异步控制,芯片在"睡眠"状态待机时不消耗动态功耗.芯片的平均响应时间为19.18ns,仅为最差响应时间23.37ns的82%.通过与相同工艺下的同步4-bit ACS在功耗和性能方面仿真结果的比较,可见异步ACS较同步ACS具有优势.     

Statistical leakage current reduction in high-leakage environments using locality of block activation in time domain

This paper describes a new leakage current reduction methodology that can give a statistical leakage current reduction even if the chip is in active mode, as well as in sleep mode. The proposed scheme utilizes a time locality of activation probability of a given circuit block like cache memory characteristics. The leakage cut-off switch is operated by a self-timed sleep timer, which puts the block into sleep mode. By waiting for a certain number of cycles before entering sleep mode, power overhead associated with the sleep and wake-up process is optimized, and its conditional probability is also analyzed. The effectiveness of the proposed scheme is verified by an 8-bit RISC microprocessor using Verilog HDL with real firmware, and demonstrated by a 64-bit carry-look-ahead adder with the self-cut-off switch fabricated with dual-threshold voltage SOI technology. The criterion of the effectiveness of the proposed scheme is also discussed.     

Stability and leakage characteristics of novel conducting PMOS based 8T SRAM cell

The stability and leakage power of SRAMs have become an important issue with scaling of CMOS technology. This article reports a novel 8-transistor (8T) SRAM cell improving the read and write stability of data storage elements and reducing the leakage current in idle mode. In read operation, the bit-cell keeps the noise-vulnerable data ‘low’ node voltage close to the ground level and thus producing near-ideal voltage transfer characteristics essential for robust read functionality. In write operation, a negative bias on the cell facilitates to change contents of the bit. Unlike the conventional 6T cell, there is no conflicting read and write requirement on sizing the transistors. In standby mode, the built-in stacked device in the 8T cell reduces the leakage current significantly. The 8T SRAM cell implemented in a 130 nm CMOS technology demonstrates 2× higher read stability while bearing 20% better write-ability at 1.2 V typical condition and a reduction by 45% in leakage power consumption compared to the standard 6T cell. Results of the bit-cell architecture were also compared to the dual-port 8T SRAM cell. The stability enhancement and leakage power reduction provided with the proposed cell are confirmed under process, voltage and temperature variations.     

A Low Distortion and Low Dissipation Power Amplifier with Gate Bias Control Circuit for Digital/Analog Dual-Mode Cellular Phones

A power amplifier operating at 3.3 V. has been developed for CDMA/AMPS dual-mode cellular phones. It consists of linear GaAs power MESFET's, a new gate bias control circuit, and an output matching circuit which prevents the drain terminal of the second MESFET from generating the harmonics. The relationship between the intermodulation distortion and the spectral regrowth of the power amplifier has been investigated with gate bias by using the two-tone test method and the adjacent channel leakage power ratio (ACPR) method of CDMA signals. The dissipation power of the power amplifier with a gate bias control circuit is minimized to below 1000 mW in the range of the low power levels while satisfying the ACPR of less than ?26 dBc for CDMA mode. The ACPR of the power amplifier is measured to be ?33 dBc at a high output power of 26 dBm.     

Effectiveness of adaptive supply voltage and body bias for reducing impact of parameter variations in low power and high performance microprocessors

Adaptive supply voltage as well as adaptive body bias may be used to control the frequency and leakage distribution of fabricated microprocessor dies. Test chip measurements show that adaptive V/sub CC/ is effective in reducing the impact of parameter variations on frequency, active power, and leakage power of microprocessors when 20 mV V/sub CC/ resolution is used. Using adaptive V/sub CC/ together with adaptive V/sub BS/ or within-die body bias is much more effective than using any of them individually.