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随着集成电路工艺的不断提高，CMOS电路规模不断增大，功耗成为集成电路设计主要指标之一。文章首先以多位比较器为例，阐述了存在于部分多位电路功能块中的冒险共振现象；然后给出其在VLSI电路最大功耗估计中的应用。ISCAS85电路集实验结果证实了文章思路的有效性。 相似文献
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The feasibility of implementing analog CMOS VLSI weighted median filters for image and signal processing is discussed. The proposed weighted median filter uses a transconductance comparator as a basic cell, where the output saturation current is used as the weight parameter in the median filter. Experimental results of the proposed analog weighted median filter for an ON Semiconductor 0.5 μm technology through MOSIS fabricated prototype are shown. 相似文献
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提出了一种新的准静态单相能量回收逻辑,其不同于以往的能量回收逻辑,真正实现了单相功率时钟,且不需要任何额外的辅助控制时钟,不但降低了能耗,更大大简化了时钟树的设计.该逻辑还可以达到两相能量回收逻辑所具有的速度.设计了一个8位对数超前进位加法器,并分别用传统的静态CMOS逻辑、钟控CMOS绝热逻辑(典型的单相能量回收逻辑)和准静态单相能量回收逻辑实现.采用128组随机产生的输入测试向量的仿真结果表明:输入频率为10MHz时,准静态能量回收逻辑的能耗仅仅是传统静态CMOS逻辑的45%;当输入频率大于2MHz时,可以获得比时钟控CMOS绝热逻辑更低的能耗. 相似文献
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低功耗CMOS逻辑电路设计综述 总被引：9，自引：1，他引：9
分析了ＣＭＯＳ逻辑电路的功耗来源从降低电源电压、减 上负载电容和逻辑电路开关活动几率等方面论述了降国耗的途径。讨论了深亚微米器件中亚同值电流对功耗的影响以及减小亚阈值电流的措施,最后分析了高层次设计对降低功耗的关键作用,说明低功耗设计必须从设计的各个层次加在考虑,实现整体优化设计。 相似文献
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提出了一种新的准静态单相能量回收逻辑,其不同于以往的能量回收逻辑,真正实现了单相功率时钟,且不需要任何额外的辅助控制时钟,不但降低了能耗,更大大简化了时钟树的设计.该逻辑还可以达到两相能量回收逻辑所具有的速度.设计了一个8位对数超前进位加法器,并分别用传统的静态CMOS逻辑、钟控CMOS绝热逻辑(典型的单相能量回收逻辑)和准静态单相能量回收逻辑实现.采用128组随机产生的输入测试向量的仿真结果表明:输入频率为10MHz时,准静态能量回收逻辑的能耗仅仅是传统静态CMOS逻辑的45%;当输入频率大于2MHz时,可以获得比时钟控CMOS绝热逻辑更低的能耗. 相似文献
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Advances in VLSI technology have enabled the implementation of complex digital circuits in a single chip, reducing system size and power consumption. In deep submicron low power CMOS VLSI design, the main cause of energy dissipation is charging and discharging of internal node capacitances due to transition activity. Transition activity is one of the major factors that also affect the dynamic power dissipation. This paper proposes power reduction analyzed through algorithm and logic circuit levels. In algorithm level the key aspect of reducing power dissipation is by minimizing transition activity and is achieved by introducing a data coding technique. So a novel multi coding technique is introduced to improve the efficiency of transition activity up to 52.3% on the bus lines, which will automatically reduce the dynamic power dissipation. In addition, 1 bit full adders are introduced in the Hamming distance estimator block, which reduces the device count. This coding method is implemented using Verilog HDL. The overall performance is analyzed by using Modelsim and Xilinx Tools. In total 38.2% power saving capability is achieved compared to other existing methods. 相似文献
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提出了一种单端自适应偏置电路,该电路能够根据输入信号功率,动态地调整输出直流电压,以提升射频功率放大器(PA)的线性度及功率回退区域的效率。为验证该电路的功能,设计了一种2.4 GHz PA,该电路基于单端三级结构设计,采用0.18 μm CMOS工艺制造,电路输入及输出阻抗匹配网络均集成于片内。测试结果表明,PA的增益为26.8 dB,S11和S22均小于-10 dB,OP1 dB为23.5 dBm,功率回退6 dB点PAE和峰值PAE分别为14%和24%。该PA对WLAN、ZigBee等2.4 GHz设备具有一定的应用价值。 相似文献
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本文简述了封装对CMOS VLSI电性能的影响及解决措施,重点介绍了封装在CMOS电路中引起的电噪声。 相似文献
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Vijay Kumar Sharma Manisha Pattanaik Balwinder Raj 《International Journal of Electronics》2013,100(2):200-215
Complementary metal oxide semiconductor (CMOS) technology scaling for improving speed and functionality turns leakage power one of the major concerns for nanoscale circuits design. The minimization of leakage power is a rising challenge for the design of the existing and future nanoscale CMOS circuits. This paper presents a novel, input-dependent, transistor-level, low leakage and reliable INput DEPendent (INDEP) approach for nanoscale CMOS circuits. INDEP approach is based on Boolean logic calculations for the input signals of the extra inserted transistors within the logic circuit. The gate terminals of extra inserted transistors depend on the primary input combinations of the logic circuits. The appropriate selection of input gate voltages of INDEP transistors are reducing the leakage current efficiently along with rail to rail output voltage swing. The important characteristic of INDEP approach is that it works well in both active as well as standby modes of the circuits. This approach overcomes the limitations created by the prevalent current leakage reduction techniques. The simulation results indicate that INDEP approach mitigates 41.6% and 35% leakage power for 1-bit full adder and ISCAS-85 c17 benchmark circuit, respectively, at 32 nm bulk CMOS technology node. 相似文献
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能量恢复型CVSL电路的设计及其应用 总被引：1，自引：0，他引：1
提出了采用交流能源的级联电压开关逻辑(CVSL)电路,其主要特点是输出与输入信号呈现相同相位,并消除了输出端悬空现象,适合于实现低功耗组合电路。应用0.25μmCMOS标准工艺的SPICE模拟表明,提出的电路具有正确的逻辑功能与可观的能量节省。 相似文献
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本文介绍通信LSI/VLSI电路制作技术中目前比较通用的工艺。总的来说,通信电路工艺是以前LSI/VLSI22艺的继续和发展。文中论述的重点是那些和过去LSI/VLSI工艺不同的方面,而这些方面主要体现在模拟电路的制作工艺上。 相似文献
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三态逻辑电路已被广泛应用于VLSI数字集成系统中.现在也有很多种实现三态逻辑的方法,但它们要么输出驱动能力不足够强要么占有较大的器件面积.在研究传统三态缓冲器的基础上设计了一种新型的三态缓冲器,据我们所知,这是使用晶体管数目最少的一种三态缓冲器结构.通过SPICE仿真实验表明,所设计的三态缓冲器与传统三态缓冲器相比具有更优的面积-延时积特性和更低的静态功耗. 相似文献
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This paper deals with the implementation of Full Adder chains by mixing different CMOS Full Adder topologies. The approach is based on cascading fast Transmission-Gate Full Adders interrupted by static gates having driving capability, such as inverters or Mirror Full Adders, thus exploiting the intrinsic low power consumption of such topologies. The obtained mixed-topology circuits are optimized in terms of delay by resorting to simple analytical models.Delay, power consumption and the Power-Delay Product (PDP) in both mixed-topology and traditional Full Adder chains were evaluated through post-layout Spectre simulations with a 0.35 μm, 0.18 μm and 90 nm CMOS technology considering different design targets, i.e., minimum power consumption, PDP, Energy-Delay Product (EDP) and delay. The results obtained show that the mixed-topology approach based on Mirror adders are capable of a very low power consumption (comparable to that of the low-power Transmission-Gate Full Adder) and a very high speed (comparable with or even greater than that of the very fast Dual-Rail Domino Full Adder). This also enables a high degree of design freedom, given that the same (mixed) topology can be used for a wide range of applications. This greater flexibility also affords a significant reduction in the design effort. 相似文献
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Sandeep Garg Tarun K. Gupta Amit K. Pandey 《International Journal of Electronics》2020,107(4):513-541
ABSTRACTThis paper proposes a 4:1 Multiplexer (MUX) designed using proposed Dual Chirality High-Speed Noise Immune Domino Logic (DCHSNIDL) technique for designing lower delay noise immune domino logic circuits in Carbon Nanotube Field Effect Transistors (CNTFETs) technology. Dynamic power consumption, speed and noise immunity of the circuit are improved by changing the threshold voltage of the CNTFETs. The chirality indices of the carbon nanotubes (CNTs) are varied to change the threshold voltage of the CNTFETs. Simulations are carried out for 32 nm Stanford CNTFET model in HSPICE for 2-, 4-, 8- and 16-input domino OR gates at a clock frequency of 200 MHz on a DC supply voltage of 0.9V. The proposed DCHSNIDL domino circuit reduces power consumption by a maximum of 61.77% and propagation delay by a maximum of 55.11% compared to Current-Mirror Based Process Variation Tolerant (CPVT) circuit in CNTFET technology. The proposed CNTFET-based domino technique shows a maximum reduction of 96.31% in power consumption compared to its equivalent circuit in CMOS technology for a 4-input OR gate. The proposed technique shows an improvement of 1.04× to 1.35× times in Unity Noise Gain (UNG) compared to various existing techniques in CNTFET technology. The 4:1 MUX designed using proposed technique has 48.91% lower propagation delay and consumes 52.80% lower power compared to MUX using CPVT technique. 相似文献
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By the reduction in the size of transistors and the development of submicron technology, as well as the construction of more integrated circuits on chips, leakage power has become one of the main concerns of electronic circuit designers. In this article, we first review techniques presented in recent years to reduce leakage power and then present a new technique based on the gate-level body biasing technique and the multi-threshold CMOS technique to minimize leakage power in digital circuits. Afterward, we develop another new method by improving the first proposed technique to achieve higher efficiency and simultaneously reduce leakage power and propagation delay in digital circuits. In the proposed technique, we use two dynamic threshold MOSFET transistors to reduce leakage current. In this paper, the body biasing generator structure is applied to reduce propagation delay. The proposed technique has been successfully validated and verified by post-layout simulation with Cadence Virtuoso based on the 32 nm process technology.We evaluate the efficiency of the proposed techniques by examining factors including power, delay, area, and the power delay product. The simulation results using HSPICE software and performance analysis to process corner variations based on the 32 nm process technology show that the proposed technique, in addition to having proper performance in different corners of the technology, significantly reduces leakage power and propagation delay in logic CMOS circuits. In general, the proposed technique has a very successful performance compared to previous techniques. 相似文献
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Amine Bermak Abdessellam Bouzerdoum Kamran Eshraghian 《Microelectronics Journal》2002,33(12):1091-1096
In this paper we propose an on-pixel Analogue-to-Digital Converter (ADC) based on pulse frequency modulation (PFM) scheme. This PFM based converter presents a viable solution for pixel-level based ADC. It uses a simple and robust circuit that can be implemented in a compact area resulting in a 23% fill-factor for a digital vision sensor in 0.25 μm CMOS technology. An in-built light adaptation mechanism has also been implemented which allows the sensor to better adapt to low-light intensity or to adjust the sensor saturation level. As a consequence, the proposed sensor features a programmable dynamic range. Image lag is eliminated since a reset of the photodetector is performed after the conversion period. A prototype comprising a 32×32 pixel array has been implemented in CMOS 0.25 μm technology. Each pixel occupies an area of 45×45 μm2 with an average power consumption of 85 μW per pixel. 相似文献
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This paper presents a new power gating structure with robust data retention capability using only one single double-gate device to provide both power gating switch and virtual supply/ground diode clamp functions. The scheme reduces the transistor count, area, and capacitance of the power gating structure, thus improving circuit performance, power, and leakage. The scheme is compared to the conventional power gating structure via mixed-mode physics-based two-dimensional numerical simulations. Analysis of virtual ground bounce for the proposed scheme is also presented. 相似文献
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This letter describes the design and implementation of a synchronizable compact CMOS oscillator. By using a fully differential topology, a reduction in area occupancy together with an improved robustness in front of on-chip interferences is achieved. Post-layout simulation results and experimental results for a standard CMOS 0.35 m technology are presented to validate the functionality of the tunable oscillator. 相似文献