An integrable temperature-insensitive gm –RC quadrature oscillator

A novel g_m –RC quadrature oscillator using operational transconductance amplifiers (OTAs) and grounded passive elements is proposed. The circuit provides two quadrature outputs of equal magnitude and the oscillation frequency is insensitive to temperature. The oscillation frequency can be linearly and electronically controlled without affecting the condition of oscillation. The active ω₀-sensitivity has been shown to be small. Experimental and simulation results that demonstrate the performance of the proposed oscillator are also included.     

Design of a low-power 8 × 8-bit parallel multiplier using MOS current mode logic circuit

This paper proposes an 8?×?8 bit parallel multiplier using MOS current mode logic (MCML) for low power consumption. The 8?×?8 bit multiplier is designed with the proposed MCML full adders and the conventional full adders. The proposed multiplier is achieved to reduce the power consumption by 9.4% and the power-delay-product by 11.7% compared with the conventional circuit. The validity and effectiveness are verified through HSPICE simulation. The proposed multiplier is designed with the Samsung 0.35?μm standard CMOS process.     

Low‐noise,low‐voltage,low‐power IF gain controlled amplifiers for wireless communication

Circuit solutions of various types of gain controlled IF amplifiers with digital and analog gain control are described. Advantages and disadvantages of the different solutions are shown. Requirements for lowpower, lowvoltage, low noise, high gain and linearity at high IFfrequencies from the system point of view are worked out. Solutions will be presented to optain optimum performance by technology and circuit design technique for digital wireless telephone systems used for GSM and PCN systems.     

Bulk-tuned Gm–C filter using current cancellation

A new approach for small transconductance (Gm) OTA designs, suitable for relatively low frequency filtering applications in the range of few kHz, is proposed. Small Gm values are achieved by a current cancellation technique, and are adjustable by bulk driving the MOS transistors of the input differential amplifier. The OTA design procedure takes into account Pelgrom׳s modeling of mismatch errors. A common-mode feedback control circuit based on floating gate common-mode voltage detector that shares the filter main capacitances is also presented. Experimental results obtained with a low-pass filter with tunable cutoff frequency implemented in a 0.35 μm CMOS process to verify the effectiveness of the design procedure have shown close agreement with the theory.     

Contactless vital signs monitoring based on few‐mode and multi‐core fibers

Few-mode and multi-core fibers are proposed and demonstrated for contactless vital signs monitoring in this paper.In-line optical fiber interferometers using few-mode and multi-core fibers are designed and offset splicing is utilized for mode excitation.Extinction ratio and insertion loss are analyzed experimentally under different offset distances.The fabricated in-line interferometers are packaged under the mattress to realize contactless vital signs signals collection.By using filtering techniques,both respiration and heartbeat signals can be recovered successfully,and respiration as well as heartbeat ratio are obtained.Mode excitation and interference are theoretically analyzed in few-mode fiber while curvature sensing experiments using multi-core fiber interferometer are performed to verify its excellent performance on vital signs monitoring.The successful demonstration on contactless vital signs monitoring makes few-mode and multi-core fibers promising candidates for healthcare applications.     

Current mode ADC design in a 0.5-μm CMOS process

This paper presents a pipelined current mode analog to digital converter（ADC） designed in a 0.5-μm CMOS process.Adopting the global and local bias scheme,the number of interconnect signal lines is reduced numerously,and the ADC exhibits the advantages of scalability and portability.Without using linear capacitance,this ADC can be implemented in a standard digital CMOS process;thus,it is suitable for applications in the system on one chip（SoC） design as an analogue IP.Simulations show that the proposed current mode ADC can operate in a wide supply range from 3 to 7 V and a wide quantization range from ±64 to ±256 μA.Adopting the histogram testing method,the ADC was tested in a 3.3 V supply voltage/±64 μA quantization range and a 5 V supply voltage/±256 μA quantization range,respectively.The results reveal that this ADC achieves a spurious free dynamic range of 61.46 dB,DNL/INL are-0.005 to ＋0.027 LSB/-0.1 to ＋0.2 LSB,respectively,under a 5 V supply voltage with a digital error correction technique.     

Current mode ADC design in a 0.5-μm CMOS process

This paper presents a pipelined current mode analog to digital converter (ADC) designed in a 0.5-μm CMOS process. Adopting the global and local bias scheme, the number of interconnect signal lines is reduced numerously, and the ADC exhibits the advantages of scalability and portability. Without using linear capacitance,this ADC can be implemented in a standard digital CMOS process; thus, it is suitable for applications in the system on one chip (SoC) design as an analogue IP. Simulations show that the proposed current mode ADC can operate in a wide supply range from 3 to 7 V and a wide quantization range from ±64 to ±256μA. Adopting the histogram testing method, the ADC was tested in a 3.3 V supply voltage/±64μA quantization range and a 5 V supply voltage/±256μA quantization range, respectively. The results reveal that this ADC achieves a spurious free dynamic range of 61.46dB, DNL/INL are -0.005 to +0.027 LSB/-0.1 to +0.2 LSB, respectively, under a 5 V supply voltage with a digital error correction technique.     

Evaluating scheduling in integrated‐services networks using a semi‐fluid‐flow model

An integratedservices network carries diverse traffic, which leads to diverse performance objectives. For example, voice and video packets typically have performance objectives based on the fraction of packets that will be delivered within a given delay bound, while data packets often have objectives based on mean delay. Greater loads can be supported in networks in which a voice or video packet is given priority over data packets if and only if the former is in danger of missing its deadline. Algorithms that allow this include CostBased Scheduling, occupancybased algorithms, the Priority Token Bank, and to a lesser extent, the Leaky Bucket. This paper presents an approach to evaluating performance with these algorithms in the realistic case where data arrivals are highly bursty, but voice and video packets are not. Mean queueing delay for data bursts is determined analytically in some important scenarios, and an efficient simulation approach based on the same model is described for cases where analysis is not currently possible. The model is a semifluidflow model in which voice or video packets are assumed to arrive as a continuous fluid flow, whereas data packets arrive in large bursts at discrete instants in time.     

A voltage mode buck DC–DC converter with automatic PWM/PSM mode switching by detecting the transient inductor current

This paper presents a voltage mode buck DC–DC converter that integrates pulse-width modulation (PWM) and pulse-skipping modulation (PSM) to achieve high efficiency under heavy and light load conditions, respectively. Automatic mode-switching is implemented simply by detecting the voltage drop of high-side power switch when it is on, which indicates the transient current flowing through the inductor. Unlike other methods based on average current sensing, the proposed auto-mode switching scheme is implemented based on voltage comparison and simple control logic circuit. In order to avoid unstable mode switching near the load condition boundary, the mode switching threshold voltage is set differently in PWM and PSM mode. Besides, a 16-cycle counter is also used to ensure correct detection of the change in the load condition and fast response of the converter. In addition, a dual-path error amplifier with clamp circuit is also adopted to realize loop compensation and ensure 100 % duty cycle operation. Fabricated in a 0.18-μm standard CMOS technology, the DC–DC converter is able to operate under supply voltage from 2.8 to 5.5 V with 3-MHz clock frequency. Measurement results show that the converter achieves a peak efficiency of 93 %, and an output voltage ripple of less than 40 mV, while the chip area is 1.02 mm².     

A high performance 1 GHz voltage controlled oscillator using neural system architecture

In this paper, an improved voltage controlled oscillator scheme with temperature compensated frequency, a wide linear range, low phase noise and low power dissipation is presented for application in transmitting signals of gas sensors from mines using RF communication. The basic unit of the oscillator is a ring based differential amplifier incorporating temperature compensated voltage dependent PMOS capacitors and standard PMOS triode connected load with temperature compensated biasing scheme. The increased nonlinearity in the presence of PMOS capaciors is reduced to 0.001% using a digitally programmable neural architecture which is simulated in the mixed signal domain of SYNOPSYS. Additionally, the temperature compensated PMOS capacitor improves the sensitivity of the VCO and the standard temperature compensated biasing scheme of the PMOS triode connected load reduces the drift in amplitude with temperature variation. The PMOS varactor lowers the phase noise of the VCO compared to parasitic capacitors without increasing the power dissipation. The entire VCO is designed using 0.18 μm typical technology of TSMC with 1.8 V power supply. The tuning range of the VCO is 0.3–1.7 V, maximum frequency is 1 GHz with a linear change of around 750 MHz, temperature sensitivity and power consumption are around 50 ppm/°C and 2 mW respectively. The phase noise is obtained to be around −123dBc/Hz at 1 MHz offset frequency.     

New current–mode special function continuous-time active filters employing only OTAs and OPAMPs

This paper reports three current mode second order filters, each of which realizes a specific function without any external passive elements. These filters realize low-pass notch (LPN), high-pass notch (HPN) and all-pass (AP) functions. Two OPAMPs, a double output OTA and a single output OTA are employed for each circuit. The filter structures can be easily cascaded since they have high output impedances. This property is especially useful for achieving high-order filters using these LPN and HPN filters as building blocks. The presented theory is verified with macro models in SPICE simulations and, using the SPICE parameters of the layout technology, post layout simulations are carried out, with parasitics extracted from the layouts of the filter chips.     

A 95 nA quiescent current hysteretic mode buck converter with sample and hold reference

A nano ampere (nA) hysteretic mode buck converter is presented in this paper. Nano ampere current sleep phase and fast response burst phase are implemented. The converter achieves nano-watt power consumption in sleep phase while ensures fast wake-up from sleep phase to burst phase. New developed ultra low power sample-hold voltage reference and 1 kHz oscillator draw currents of 20 and 10 nA respectively. The circuit was implemented in a 0.35 μm CMOS process. The measurement result shows that the converter’s quiescent current (Iq) in sleep phase is as low as 95 nA. Benefit from the ultra-low Iq, the circuit achieves conversion efficiency of 79.8% at 2 μA load, regulating output at 2.5 V with a 3.6 V supply. The peak efficiency is up to 94% at 50 mA load.     

A source degenerated LC quadrature VCO (SD-QVCO) using 0.18-μm SiGe BiCMOS

This letter presents a fully integrated BiCMOS quadrature voltage-controlled oscillator (QVCO). The QVCO consists of two nMOSFET cross-coupled oscillator stacked in series with source degenerated HBT transistors. SiGe HBT introduces low flicker noise compared to CMOS devices. To generate quadrature phase signals with strong coupling strength, the proposed design uses two MOS-coupled LC-tank cores instead of passive device-coupled cores. This source degeneration topology can improve the phase noise performance of the QVCO as compared to the sub-VCO. The proposed QVCO has been implemented with the TSMC 0.18 μm SiGe 3P6M BiCMOS process, can generate quadrature signals in the frequency range of 4.52–5.05 GHz with core power consumption of 5.76 mW at the dc bias of 1.8 V. At 4.53 GHz, phase noise at 1 MHz offset is ?124.52 dBc/Hz. The die area of the fabricated prototype is 0.453 × 0.898 mm².     

An improved method for the design of quadrature mirror filter banks using the Levenberg–Marquardt optimization

This paper presents an improved and efficient method for the design of a two-channel quadrature mirror filter (QMF) bank. In the proposed method, the filter bank design problem is formulated as a low-pass prototype filter design problem, whose responses in the passband and stopband are ideal and their filter coefficients value at quadrature frequency is 0.707. A new method is developed for the design of a low-pass prototype filter which minimizes the objective function by optimizing the filter taps weights using the Levenberg–Marquardt method. When compared with other existing algorithms, it significantly reduces peak reconstruction error (PRE), error in passband, stopband and transition band. Several design examples are included to show the increased efficiency and the flexibility of the proposed method over existing methods. An application of this method is considered in the area of subband coding of the ultrasound images.     

A new current mode APS in 0.18 μm standard CMOS process for smart image sensors

In this paper we present a new current mode structure for active pixel sensor (APS) which is an essential part in fast parallel processing Smart CMOS Image Sensors such as wireless capsule endoscopy. Using two diodes (N+/P-Well and P-Well/Deep-N-Well) in parallel like a pinned photo-diode (PD) improves sensing of optical signal and thus leads to higher sensitivity than a conventional PD. Also integrated signal amplification inside the collection area of the pixel increases the sensitivity of the device due to the amplification in the pixel. The proposed structure with regards to using Deep-N-Well/P-Substrate junction as a guard ring, suppresses the pixel cross-talk highly. In pixel delta reset sampling helps to make feasible on-chip parallel processing. A test structure, consist of 8 × 8 pixels of the proposed current mode APS has been simulated by standard 0.18 μm RF-CMOS technology of TSMC with a 21 × 23 μm² pixel size. Fill factor of the pixel is 24 %.     

High density and low leakage current based SRAM cell using 45 nm technology

This article is based on the observation of a Complementary Metal-Oxide Semiconductor (CMOS) five-transistor Static Random Access Memory (SRAM) cell (5T SRAM cell) for very high density and low power applications. This cell retains its data with leakage current and positive feedback without refresh cycle. This 5T SRAM cell uses one word-line and one bit-line and extra read-line control. The new cell size is 21.66% smaller than a conventional six-transistor SRAM cell using the same design rules with no performance degradation. Simulation and analytical results show purposed cell has correct operation during read/write and also the delay of new cell is 70.15% smaller than a six-transistor SRAM cell. The new 5T SRAM cell contains 72.10% less leakage current with respect to the 6T SRAM memory cell using cadence 45?nm technology.     

Cost reduction in location management using semi‐realtime movement information

This paper introduces a dynamic paging scheme based on the semirealtime movement information of an individual user, which allows a more accurate predication of the user location at the time of paging. In general, a realtime location tracking scheme may require complex control schemes and incur unacceptably high computation and messaging cost. Our proposed approach, namely the velocity paging scheme, relaxes the realtime constraints to semirealtime to provide a good combination of cost reduction and ease of implementation. The proposed velocity paging scheme utilizes semirealtime velocity information, namely velocity classes, of individual mobile terminals and dynamically calculates a paging zone (a list of cells to be paged) for an incoming call. Therefore, the total paging cost can be reduced due to the paging area reduction. Much consideration also has been given to reduce the complexity of the proposed scheme. As a result, it only requires minimal extra overhead and is feasible to implement in current cellular/PCS networks. The velocity paging can be combined with the movementbased registration or other registration schemes. Analytical and simulation results of the velocity paging and movementbased registration combination are provided to demonstrate the cost effectiveness of the scheme under various parameters in comparison with the location area scheme.     

3.6 mw low power wireless RF receiver front end using creative current recycle technique

This paper presents the design of low noise amplifier and mixer (LIXER) circuit for wireless receiver front ends using 65 nm CMOS technology. The circuit is implemented with CMOS transistors and uses 65 nm CMOS process. Proposed LIXER circuit achieves a maximum gain of 25 dB and DSB noise figure of 3.5 dB. In the given circuit, current shunt paths had created by using LC tank circuit with transistors Q5 and Q6. By using the creative current recycle technique circuit consumes 3.6 mW power with 1.2 V power supply. The operating frequency of the proposed structure is 2.4 GHz with 25 dB conversion gain and ?13 dBm IIP3. The operating of the receiver front end is 2.4 GHz is used for IEEE 802.11a WLAN, Bluetooth, and ZigBee applications.     

Physical parameters extraction from current–voltage characteristic for diodes using multiple nonlinear regression analysis

In this work, the two-step iteration combined with the nonlinear multiple regression technique to extract physical parameters for diodes, using a simple physical-based current–voltage (I–V) model is demonstrated. This statistical method can be applied for sampling for a wide variety of diodes including light-emitting diodes (LEDs) and Schottky diodes. Our results show the technique is an accurate and systematic approach for extracting diode parameters. The calculated recombination currents indicate the recombination efficiency for LEDs and the quality for Schottky diodes.     

Voltage oscillations in the case of the switching effect in thin layers of Ge–Sb–Te chalcogenides in the current mode

The I–V characteristics obtained for layers of chalcogenide vitreous semiconductor of the Ge–Sb–Te system in the current-generator mode are investigated. The instability region, i.e., the region of conductivity oscillations, observed in the case of the switching effect under conditions of a set current is revealed. The key parameters describing these oscillations and the conditions of their occurrence are investigated in detail. Analysis of the obtained data shows that, to explain the oscillations in the instability region, it is necessary to take into account an increase in the current density and the process of heat exchange between the current filament that arises in the film upon switching and the environment.