Compact analytical model for single gate AlInSb/InSb high electron mobility transistors

We have developed a 2D analytical model for the single gate Al In Sb/In Sb HEMT device by solving the Poisson equation using the parabolic approximation method.The developed model analyses the device performance by calculating the parameters such as surface potential,electric field distribution and drain current.The high mobility of the Al In Sb/In Sb quantum makes this HEMT ideal for high frequency,high power applications.The working of the single gate Al In Sb/In Sb HEMT device is studied by considering the variation of gate source voltage,drain source voltage,and channel length under the gate region and temperature.The carrier transport efficiency is improved by uniform electric field along the channel and the peak values near the source and drain regions.The results from the analytical model are compared with that of numerical simulations(TCAD) and a good agreement between them is achieved.     

Modeling of gate underlap junctionless double gate MOSFET as bio-sensor

In this work, the sensitivity of two types gate underlap Junctionless Double Gate Metal-Oxide-Semiconductor Field-Effect Transistor (JL DG MOSFET) has been compared when the analytes bind in the underlap region. Gate underlap region considered at source end and drain end once at a time in the channel of JL DG MOSFET. Separate models have been derived for both types of gate underlap JL DG MOSFETs and verified through device simulation TCAD tool sprocess and sdevice. To detect the bio-molecules, Dielectric Modulation technique has been used. The shift in the threshold voltage has been pondered as the sensing parameter to detect the presence of biomolecules when they are bound in gate underlap channel region of the devices.     

Quantum mechanical analytical modeling of nanoscale DG FinFET: evaluation of potential,threshold voltage and source/drain resistance

Two-dimensional (2D) quantum mechanical analytical modeling has been presented in order to evaluate the 2D potential profile within the active area of FinFET structure. Various potential profiles such as surface, back to front gate and source to drain potential have been presented in order to appreciate the usefulness of the device for circuit simulation purposes. As we move from source end of the gate to the drain end of the gate, there is substantial increase in the potential at any point in the channel. This is attributed to the increased value of longitudinal electric field at the drain end on application of a drain to source voltage. Further, in this paper, the detailed study of threshold voltage and its variation with the process parameters are presented. A threshold voltage roll-off with fin thickness is observed for both theoretical and experimental results. The fin thickness is varied from 10 nm to 60 nm. The percentage roll-off for our model is 77% and that for experimental result it is 75%. Form the analysis of source/drain (S/D) resistance, it is observed that for a fixed fin width, as the channel length increases, there is an enhancement in the parasitic S/D resistance. This can be inferred from the fact that as the channel length decreases, quantum confinement along the S/D direction becomes more extensive. For our proposed devices a close match is obtained with the results through the analytical model and reported experimental results, thereby validating our proposed QM analytical model for DG FinFET device.     

Two-dimensional analytical modeling of threshold voltages of short-channel MOSFET's

We present an analytical model of the threshold voltage of a short-channel MOSFET based on an explicit solution of two-dimensional Poisson's equation in the depletion region under the gate. This model predicts an exponential dependence on channel length (L), a linear dependence on drain voltage (VD), and an inverse dependence on oxide capacitance (εox/tox). An attractive feature of this model is that it provides an analytical closed-form expression for the threshold voltage as a function of material and device parameters (tox, VD, L, substrate bias, and substrate doping concentration) without making premature approximations. Also, this expression reduces to the corresponding expression for long-channel devices.     

Analysis of flicker and thermal noise in p-channel Underlap DG FinFET

In this paper, we analyze the flicker and thermal noise model for underlap p-channel DG FinFET in weak inversion region. During the analysis of current and charge model, minimum channel potential i.e. virtual source is considered. Initially, the drain current for both long and short channel of DG FinFET are evaluated and found to be well interpreted with experimental results. Further, the flicker and thermal noise spectral density are derived. The flicker noise power spectral density is compared with published experimental results, which shows a good agreement between proposed model and experimental result. During calculation we have considered variation of scattering parameter and furthermore, the degradation of effective mobility is taken into account for ultrathin body. The variation of structural parameters such as gate length (L_g), body thickness (t_Si) and underlap length (L_un) are also considered. The degradation of gate noise voltage with frequency, underlap length and gate length signify that p-channel DG FinFET device can be a promising candidate for analog and RF applications.     

Orientation and ion-implanted transverse effects in self-aligned GaAs MESFET's

The orientation dependence of the threshold voltage and device transconductance of ion-implanted GaAs FET's has been investigated and modeled. The threshold voltages of the devices along the [011] and [01bar{1}] directions are different when the gate length is short (≤ 3 µm). Experimental results and theoretical calculations show that this is primarily due to the strain in the active channel, induced by the dielectric overlayer. For the short self-aligned gate structure, the lateral spread of the ion-implanted n⁺layer is important as well. When these two effects are taken into account, calculated results agree well with the experimental data for standard self-aligned gate structures, and self-aligned structures with a sidewall or T-gate, fabricated using lamp- or furnace-annealing processes. This model also allows us to simulate the threshold voltage and transconductance dependence on the annealing time for different device parameters (such as gate length and channel doping)and process variables (i.e., sidewall or T-gate dimensions and impurity diffusion constant). We also calculated the gate length dependence of the transconductance for devices fabricated using a sidewall process. Results of this calculation are compared with the experimental data for different sidewall thicknesses.     

Double jeopardy in the nanoscale court [MOSFET modeling]

Physics-based compact short-channel models of threshold voltage and subthreshold swing for undoped symmetric double-gate MOSFETs are presented, developed from analytical solutions of the two-dimensional Poisson equations in the channel region. These models accurately characterize the subthreshold and near-threshold regions of operation by appropriately including essential phenomena such as volume inversion and the dominance of mobile charges over fixed charges under threshold conditions. Explicit, analytical expressions are derived for a scale length, which results from an evanescent-mode analysis. These equations readily quantify the impact of silicon film thickness and gate oxide thickness on the minimum channel length and device characteristics and can be used as an efficient guideline for device designs. These newly developed models are exploited to make a comprehensive projection on the scaling limits of undoped double-gate MOSFETs. On the individual device level, model predictions indicate that the minimum channel length can be scaled beyond 10 nm for a turn-off behavior of S=100 mV/dec for a silicon film thickness below 5 nm and an electrical equivalent oxide thickness below 1 nm.     

Gate dielectric engineering of quarter sub micron AlGaN/GaN MISHFET: A new device architecture for improved transconductance and high cut-off frequency

In this paper analytical modeling for a novel three region gate dielectric engineered AlGaN/GaN Metal Insulator Semiconductor heterostructure field effect transistor (MISHFET) device architecture is presented which shows high transconductance and enhanced cut-off frequency at quarter micron gate lengths. Using a three region analysis along the horizontal direction in the gate dielectric region the expressions for transconductance and cut-off frequency of the device are obtained. It has been observed that using these gate dielectric schemes, improvements on device performance are observed over conventional MISHFET structures. Relative comparison of T and Γ-gate shaped structures is done with uniform gate dielectric profile and enhancement in microwave performance is observed. The proposed model is capable of modeling electrical characteristics like drain current, output conductance and threshold voltage of various other existent structures like uniform gate dielectric MISHFETs, HFETs and T-gate HFETs. The present model is based on closed form expression and does not involve any fitting parameter. The results obtained are compared with experimental data and show excellent agreement, thereby proving the validity of the model.     

Nanoscale FinFETs with gate-source/drain underlap

Using two-dimensional numerical device simulations, we show that optimally designed nanoscale FinFETs with undoped bodies require gate-source/drain (G-S/D) underlap that can be effectively achieved via large, doable straggle in the S-D fin-extension doping profile without causing S-D punch-through. The effective underlap significantly relaxes the fin-thickness requirement for control of short-channel effects (SCEs) via a bias-dependent effective channel length (L/sub eff/), which is long in weak inversion and approaches the gate length in strong inversion. Dependence of L/sub eff/ on the S/D doping profile defines a design tradeoff regarding SCEs and S/D series resistance that can be optimized, depending on the fin width, via engineering of the doping profile in the S/D fin-extensions. The noted optimization is exemplified via a well-tempered FinFET design with an 18-nm gate length, showing further that designs with effective underlap yield minimal parasitic capacitance and reduce leakage components such as gate-induced drain leakage current.     

Modeling the drain current and its equation parameters for lightly doped symmetrical double-gate MOSFETs

A 2D model for the potential distribution in silicon film is derived for a symmetrical double gate MOSFET in weak inversion. This 2D potential distribution model is used to analytically derive an expression for the subthreshold slope and threshold voltage. A drain current model for lightly doped symmetrical DG MOSFETs is then presented by considering weak and strong inversion regions including short channel effects, series source to drain resistance and channel length modulation parameters. These derived models are compared with the simulation results of the SILVACO (Atlas) tool for different channel lengths and silicon film thicknesses. Lastly, the effect of the fixed oxide charge on the drain current model has been studied through simulation. It is observed that the obtained analytical models of symmetrical double gate MOSFETs are in good agreement with the simulated results for a channel length to silicon film thickness ratio greater than or equal to 2.     

Effect of underlap and gate length on device performance of an AlInN/GaN underlap MOSFET

We investigate the performance of an 18 nm gate length AlInN/GaN heterostructure underlap double gate MOSFET, using 2D Sentaurus TCAD simulation. The device uses lattice-matched wideband Al_0.83In_0.17N and narrowband GaN layers, along with high-k Al₂O₃ as the gate dielectric. The device has an ultrathin body and is designed according to the ITRS specifications. The simulation is done using the hydrodynamic model and interface traps are also considered. Due to the large two-dimensional electron gas (2DEG) density and high velocity, the maximal drain current density achieved is very high. Extensive device simulation of the major device performance metrics such as drain induced barrier lowering (DIBL), subthreshold slope (SS), delay, threshold voltage (V_t), I_on/I_off ratio and energy delay product have been done for a wide range of gate and underlap lengths. Encouraging results for delay, I_on, DIBL and energy delay product are obtained. The results indicate that there is a need to optimize the I_off and SS values for specific logic design. The proposed AlInN/GaN heterostructure underlap DG MOSFET shows excellent promise as one of the candidates to substitute currently used MOSFETs for future high speed applications.     

Threshold voltage model for small geometry AlGaN/GaN HEMTs based on analytical solution of 3-D Poisson's equation

A simple and accurate analytical model for the threshold voltage of AlGaN/GaN high electron mobility transistor (HEMT) is developed by solving three-dimensional (3-D) Poisson equation to investigate the short channel effects (SCEs) and the narrow width effects present simultaneously in a small geometry device. It has been demonstrated that the proposed model correctly predicts the potential and electric field distribution along the channel. In the proposed model, the effect of important parameters such as the thickness of the barrier layer and its doping on the threshold voltage has also been included. The model is, further, extended to find an expression for the threshold voltage in the sub-micrometer regime. The accuracy of the proposed analytical model is verified by comparing the model results with 3-D device simulations for different gate lengths and widths.     

Analytical threshold voltage model for cylindrical surrounding-gate MOSFET with electrically induced source/drain extensions

Physics-based analytical threshold voltage model for cylindrical surrounding-gate MOSFET with electrically induced source/drain extensions is presented. The effect of inversion carriers on the channel’s potential is considered in presented model. Using this analytical model, the characteristics of EJ-CSG are investigated in terms of surface potential and electric field distribution, threshold voltage roll-off, and DIBL. Results show that the application of electrically induced S/D extensions to the cylindrical surrounding-gate MOSFET will successfully suppress the hot-carrier effects, threshold voltage roll-off, and DIBL. It is also revealed that a moderate side-gate bias voltage, a small gate oxide thickness, and a small silicon channel radius are needed to improve device characteristics. The derived analytical model is verified by its good agreement with the three-dimensional numerical device simulator ISE.     

New optimized Dual-Material (DM) gate design to improve the submicron GaN-MESFETs reliability in subthreshold regime

In this paper, new Dual-Material-gate (DM) concept and optimization approach are proposed to improve the device immunity against the hot carrier and short channel effects (SCEs), and optimize the subthreshold electrical performance of the submicron Gallium Nitride (GaN)-MESFET. The 2D analytical analysis includes the modeling of the channel potential, subthreshold swing, threshold voltage, Drain-Induced Lowering Barrier (DIBL) and parasitic resistances. The influence of gate length and the work function of each gate region on subthreshold behavior was investigated using the developed analytical models. The developed analytical approaches are verified and validated by the good agreement found with the 2D numerical simulations for wide range of device parameters and bias conditions. The presented compact models are used to formulate the different objective functions, which are the pre-requisite of multi-objective genetic algorithms optimization, which will be used to optimize the device subthreshold performances. The optimized design can alleviate the critical problem and further improve the immunity of SCEs of submicron GaN-MESFET-based digital circuits for low power and high speed applications.     

A new approach to threshold voltage modelling of short-channel MOSFETS

A simple analytical model has been developed to predict the threshold voltage on drain bias dependence of an arbitrarily doped short-channel MOSFET. Based on an analytical solution of the two-dimensional Poisson equation, the potential distribution in the channel depletion region has been derived. The maximum surface field and the minimum surface potential are used to determine the threshold voltage. The influence of drain voltage on threshold voltage has been included by an equivalent shrinkage of the virtual channel length hereafter called “voltage-length transformation”. This simple but general procedure enables us to account for the drain effect and to extend other threshold voltage models derived under assumption of low drain-source voltage. Predictions for threshold voltage have been compared with results of two-dimensional numerical analysis and experimental data. The comparison has been made for a wide variety of doping profiles, channel length, substrate and drain bias, gate oxide thickness and junction depth. Excellent agreement has been obtained down to submicron channel length.     

Modeling and simulation of a nanoscale three-region tri-material gate stack (TRIMGAS) MOSFET for improved carrier transport efficiency and reduced hot-electron effects

Two-dimensional (2-D) analytical modeling for a novel multiple region MOSFET device architecture-Tri-Material Gate Stack MOSFET-is presented, which shows reduced short-channel effects at short gate lengths. Using a three-region analysis in the horizontal direction and a universal depletion width boundary condition, the 2-D potential and electric field distribution in the channel region along with the threshold voltage of the device are obtained. The proposed model is capable of modeling electrical characteristics like surface potential, electric field, and threshold voltage of various other existent MOSFET structures like dual-material-gate, electrically induced shallow junction/straddle-gate (side-gate), and single-material-gate MOSFETs, with and without the gate stack architecture. The 2-D device simulator ATLAS is used over a wide range of parameters and bias conditions to validate the analytical results.     

Characteristics of enhancement/depletion (E/D) gate MOSFET fabricated using ion implantation

The E/D gate MOSFET, which has an enhancement and depletion mode region under the same gate, is fabricated by using ion implantation as a tool for shifting threshold voltage. Threshold voltage, transconductance and drain breakdown voltage are studied as functions of implantation dose up to 12 × 10¹² cm^?2.It is found that, at an appropriate dose, the transconductance of this device is determined solely by the channel length of the enhancement mode region, and is larger than that of a short channel MOSFET with a standard structure but with the same drain breakdown voltage. Moreover, the dependence of threshold voltage on substrate bias measured in this device is found less sensitive to the transconductance than that in the standard short channel MOSFET.     

The effect of high fields on MOS device and circuit performance

A simple analytical model for the MOS device characteristics including the effect of high vertical and horizontal fields on channel carrier velocity is presented. Analytical expressions for the drain current, saturation drain voltage, and transconductance are developed. These expressions are used to examine the effect of scaling the channel length, the gate dielectric thickness, and the bias voltage on device characteristics. Experimental results from various geometry MOS devices are used to verify the trends predicted by the model. Using the physical understanding provided by the model, we examine the effect of device geometry scaling on circuit performance. We suggest that for gate capacitance-limited circuits one should reduce the channel length, and for parasitic capacitance-limited circuits one should reduce the gate dielectric thickness to improve circuit performance.     

Modeling and optimization of fringe capacitance of nanoscale DGMOS devices

We analyze the impact of gate electrode thickness and gate underlap on the fringe capacitance of nanoscale double-gate MOS (DGMOS) transistors. We propose an analytical fringe capacitance model considering gate underlap and finite source/drain length. A comparison with the simulation results show that the model can accurately estimate the fringe capacitance of the device. We show that an optimum gate underlap can significantly reduce the fringe capacitance resulting in higher performance and lower power consumption. Also, the effects of process variation in gate underlap devices are discussed. Simulation results on a three-stage ring oscillator show that with optimum gate underlap 32% improvement in delay can be achieved.     

A physical short-channel threshold voltage model for undoped symmetric double-gate MOSFETs

A compact, physical, short-channel threshold voltage model for undoped symmetric double-gate MOSFETs has been derived based on an analytical solution of the two-dimensional (2-D) Poisson equation with the mobile charge term included. The new model is verified by published numerical simulations with close agreement. Applying the newly developed model, threshold voltage sensitivities to channel length, channel thickness, and gate oxide thickness have been comprehensively investigated. For practical device designs the channel length causes 30-50% more threshold voltage variation than does the channel thickness for the same process tolerance, while the gate oxide thickness causes the least, relatively insignificant threshold voltage variation. Model predictions indicate that individual DG MOSFETs with good turn-off behavior are feasible at 10 nm scale; however, practical exploitation of these devices toward gigascale integrated systems requires development of novel technologies for significant improvement in process control.