High speed interconnect through device optimization for subthreshold FPGA

Field programmable gate array (FPGA) consumes a significant amount of static and dynamic power due to the presence of additional logic for providing more flexibility as compared to application specific integrated circuits (ASICs). The fabrication cost of ASICs is rising exponentially in deep submicron and hence it is important to investigate different techniques for reducing FPGA power consumption so that they can also be employed in place of ASICs in portable energy constrained applications. It is also important to investigate the possibility of extending the use of FPGA even to subthreshold region for ultra low power (ULP) applications. Interconnect resources of an FPGA consumes most of the chip power, area and also determines the overall circuit delay. Subthreshold circuits show orders of magnitude power saving over superthreshold circuits. Improving the performance of subthreshold circuits is a main design challenge at the circuit and device levels to spread their application area. This paper proposes to improve the performance of subthreshold FPGA in terms of delay and switching energy by optimizing and operating interconnect drivers in the near threshold operating region. The possibility of inserting repeaters and the suitability of CNT as an interconnect in the subthreshold region are also explored. The simulation of FPGA interconnect resources using the proposed technique shows 67%, 73.33% and 61.8% increase in speed and 35.72%, 39% and 35.44% reduction in switching energy for Double, Hex and Long interconnect segments, respectively, over the conventional one.     

Path reuse-aware routing for non-volatile memory based FPGAs

Non-volatile memory-based FPGAs (NV-FPGAs) are expected to replace traditional SRAM-based FPGAs to achieve higher scalability and lower power consumption. Yet the slow write performance of NVMs not only challenges FPGA reconfiguration speed and overhead but also constrains the programming cycles of FPGAs. To efficiently configure switch boxes, the majority component of an FPGA, this paper presents a routing path reuse technique. The reconfiguration cost of routing resources is first modeled mathematically and then minimized through a reuse-aware routing algorithm, which is incorporated into the standard VTR CAD tool. Experiments on standard MCNC and Titan benchmarks show that the proposed scheme is able to achieve as much as 58% path reuse rate and reduce as much as 45% configuration cost for routing resources.     

A Low-Power Field-Programmable Gate Array Routing Fabric

This paper describes a new programmable routing fabric for field-programmable gate arrays (FPGAs). Our results show that an FPGA using this fabric can achieve 1.57 times lower dynamic power consumption and 1.35 times lower average net delays with only 9% reduction in logic density over a baseline island-style FPGA implemented in the same 65-nm CMOS technology. These improvements in power and delay are achieved by 1) using only short interconnect segments to reduce routed net lengths, and 2) reducing interconnect segment loading due to programming overhead relative to the baseline FPGA without compromising routability. The new routing fabric is also well-suited to monolithically stacked 3-D-IC implementation. It is shown that a 3-D-FPGA using this fabric can achieve a 3.3 times improvement in logic density, a 2.51 times improvement in delay, and a 2.93 times improvement in dynamic power consumption over the same baseline 2-D-FPGA.     

Routability of Network Topologies in FPGAs

A fundamental difference between application-specific integrated circuits (ASICs) and field-programmable gate arrays (FPGAs) is that the wires in ASICs are designed to match the requirements of a particular design. Conversely, in an FPGA, the area is fixed and the routing resources exist whether or not they are used. In this paper, we investigate how well several common network topologies map onto a modern FPGA routing fabric. Different multiprocessor network topologies with between 8 and 64 nodes are mapped to a single large FPGA. Except for the fully-connected networks, it is observed that the difference in logic resources used and routing overhead among these topologies is insignificant for the systems tested. Fully-connected networks up to about 22 nodes are also feasible on the same FPGA although the logic and routing utilization clearly grows much faster. The conclusion is that a modern FPGA fabric is very rich in resources and capable of supporting highly interconnected topologies. For systems with a modest number of nodes implemented on current large FPGAs, it is not necessary to use the connectivity-limited topologies typically used for networks-on-chip. Rather, direct point-to-point connections between all communicating nodes can be considered.     

Sharing of SRAM Tables Among NPN-Equivalent LUTs in SRAM-Based FPGAs

This article introduces a novel lookup table (LUT) and its usage in the configurable logic block (CLB) architectures for SRAM-based field-programmable gate array (FPGA) architectures. The proposed CLB allows sharing of SRAM tables of LUTs among NPN-equivalent functions to reduce the size of memories used for storing the functions and also reduces the number of configuration bits required. We measured many different characteristics of FPGAs using our new CLB architecture, including area, delay, routing, and power requirements. We experimentally found that for many different FPGA architectures, CLBs can share one-fourth of their SRAM tables between two basic logic elements (BLEs), which reduced both power consumption and area without negatively affecting routing or wirelength, and there was only a negligible increase in critical path delay of 0.27%. Specifically, we find that FPGAs consisting of CLBs with 16 BLEs and 34 inputs can be implemented with eight normal SRAMs and four SRAMs shared between two BLEs, for an overall reduction of four out of sixteen SRAM tables per CLB. With this new CLB architecture, we measured an approximate reduction in overall power consumption of 2% and an estimated reduction in area of 3%     

Flexible Circuits and Architectures for Ultralow Power

Subthreshold digital circuits minimize energy per operation and are thus ideal for ultralow-power (ULP) applications with low performance requirements. However, a large range of ULP applications continue to face performance constraints at certain times that exceed the capabilities of subthreshold operation. In this paper, we give two different examples to show that designing flexibility into ULP systems across the architecture and circuit levels can meet both the ULP requirements and the performance demands. Specifically, we first present a method that expands on ultradynamic voltage scaling (UDVS) to combine multiple supply voltages with component level power switches to provide more efficient operation at any energy-delay point and low overhead switching between points. This system supports operation across the space from maximum performance, when necessary, to minimum energy, when possible. It thus combines the benefits of single-${V}_{rm DD}$ , multi-${V}_{rm DD}$, and dynamic voltage scaling (DVS) while improving on them all. Second, we propose that reconfigurable subthreshold circuits can increase applicability for ULP embedded systems. Since ULP devices conventionally require custom circuit design but the manufacturing volume for many ULP applications is low, a subthreshold field programmable gate array (FPGA) offers a cost-effective custom solution with hardware flexibility that makes it applicable across a wide range of applications. We describe the design of a subthreshold FPGA to support ULP operation and identify key challenges to this effort.      

Metro-on-FPGA: A feasible solution to improve the congestion and routing resource management in future FPGAs

Asynchronous serial transceivers have been recently used for data serializing in large on-chip systems to alleviate the routing congestion and improve the routability. FPGAs have considerable potential for using the asynchronous serial transmission but they have serious challenges to use this technology. In this paper, we present a new FPGA architecture corresponding with a new routing algorithm to use the asynchronous data serializing technique in modern FPGAs. Experimental results show that allocated routing tracks and routing congestion can be reduced considerably (18.81% and 48.73%, respectively) by using the asynchronous data serializing without any performance degradation in cost of reasonable overhead in area and power consumption. The resulting improvements will increase for larger and more complex FPGAs.     

GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering

This paper describes GlitchLess, a circuit-level technique for reducing power in field-programmable gate arrays (FPGAs) by eliminating unnecessary logic transitions called glitches. This is done by adding programmable delay elements to the logic blocks of the FPGA. After routing a circuit and performing static timing analysis, these delay elements are programmed to align the arrival times of the inputs of each lookup table (LUT), thereby preventing new glitches from being generated. Moreover, the delay elements also behave as filters that eliminate other glitches generated by upstream logic or off-chip circuitry. On average, the proposed implementation eliminates 87% of the glitching, which reduces overall FPGA power by 17%. The added circuitry increases the overall FPGA area by 6% and critical-path delay by less than 1%. Furthermore, since it is applied after routing, the proposed technique requires little or no modifications to the routing architecture or computer-aided design (CAD) flow.      

Low-Power Programmable FPGA Routing Circuitry

We consider circuit techniques for reducing field-programmable gate-array (FPGA) power consumption and propose a family of new FPGA routing switch designs that are programmable to operate in three different modes: high-speed, low-power, or sleep. High-speed mode provides similar power and performance to traditional FPGA routing switches. In low-power mode, speed is curtailed in order to reduce power consumption. Leakage is reduced by 28%–52% in low-power versus high-speed mode, depending on the particular switch design selected. Dynamic power is reduced by 28%–31% in low-power mode. Leakage power in sleep mode, which is suitable for unused routing switches, is 61%–79% lower than in high-speed mode. Each of the proposed switch designs has a different power/area/speed tradeoff. All of the designs require only minor changes to a traditional routing switch and involve relatively small area overhead, making them easy to incorporate into current commercial FPGAs. The applicability of the new switches is motivated through an analysis of timing slack in industrial FPGA designs. It is observed that a considerable fraction of routing switches may be slowed down (operate in low-power mode), without impacting overall design performance.      

Device optimization for digital subthreshold logic operation

Digital circuits operated in the subthreshold region (supply voltage less than the transistor threshold voltage) can have orders of magnitude power advantage over standard CMOS circuits for applications requiring ultralow power and medium frequency of operation. Although the implication of technology scaling on subthreshold operation is not obvious (since an obsolete technology node can deliver the same performance as a scaled technology in subthreshold), it has been shown that technology scaling helps to reduce the supply-voltage and, hence, the power consumption at iso-performance. It is possible to implement subthreshold logic circuits using the standard transistors that are designed primarily for ultra high performance super-threshold logic design. However, an Si MOSFET so optimized for performance in the super-threshold regime is not the best device to use in the subthreshold domain. We propose device designs apt for subthreshold operation. Results show that the optimized device improves the delay and power delay product (PDP) of an inverter chain by 44% and 51%, respectively, over the normal super-threshold device operated in the subthreshold region.     

Application of nanojunction-based RRAM to reconfigurable IC

A novel reconfigurable architecture, rFPGA, is developed by utilising high-density resistive memory (RRAM) circuits as FPGA components. Different from the existing CMOS-nano hybrid FPGAs that use crossbars, the rFPGA mainly consists of 1T1R RRAM structures (one CMOS transistor is integrated with a two-terminal resistive nanojunction) that can be fabricated using an efficient CMOS-compatible process. These 1T1R structures can significantly improve the FPGA memory and routing circuits, and enable the rFPGA to achieve at least a 2x density enhancement along with a 10% reduction of delay and power, compared with the corresponding CMOS FPGA.     

Designing efficient FPGA tiles for power-constrained ultra-low-power applications

High power consumption of Field-Programmable Gate Arrays (FPGAs) makes them a less attractive choice for ultra-low-power applications. Depending on the power source, ultra-low-power systems could either be constrained by power (energy harvesting systems) or by energy (battery-powered systems). In this work, we are evaluating four different FPGA tiles to find the one that is better suited for both power-constrained and energy-constrained systems. Ultra-low-power systems apply voltage downscaling to reduce the power consumption. However, the operational limits of different blocks do not allow conventional FPGA to be operated at very low voltage. Therefore, their logic capacity can only be increased by 2–4 times by applying voltage downscaling. In this work, we identified the blocks in FPGA tiles that are vulnerable at low voltage and replace them with alternate circuits. The results indicate that, by slight modifications in the conventional FPGA tiles, logic capacity can be increased up to 8 times, whereas power-delay-product can be reduced up to 74%.     

A regular fabric design methodology for applications requiring specific layout-level design rules

Regular fabrics have been introduced as an approach to bridge the gap between ASICs and FPGAs in terms of cost and performance. Indeed, compared to an ASIC, by predefining most of the manufacturing masks, they highly reduce time-to-market, non-recoverable engineering costs and lithography hazards. Also, thanks to hardwired configuration and interconnections their performance is closer to those of ASICs than those of FPGAs. They are therefore well suited to many applications requiring low to medium volume applications or higher performance than those provided by FPGAs.In this paper, we evaluate the interest of using a regular fabric to reduce time and design cost significantly in applications involving specific transistor level design (radiative/spacial conditions, side-channel attacks, NMR environment, etc.). With this aim in view, after a broad state of the art overview with an emphasis on architectures and design flows, we develop our approach of a regular fabric designed to limit layout level design, ad-hoc tools and technological migration cost. Then, we evaluate its performance in a 65 nm process versus FPGA and standard cell based ASIC implementations. For sequential designs, our proposed solution is on average 2.5×slower and 2.3×bigger than a standard cell implantation, but also on average 13×faster than a FPGA.     

Exploration and optimization of a homogeneous tree-based application specific inflexible FPGA

An Application Specific Inflexible FPGA (ASIF) is a modified form of an FPGA which is designed for a predefined set of applications that operate at mutually exclusive times. An ASIF is a compromise between FPGAs and Application Specific Integrated Circuits (ASICs). Compared to an FPGA, an ASIF has reduced flexibility and improved density while compared to an ASIC, it has larger area but improved flexibility. This work presents a new homogeneous tree-based ASIF and uses a set of 16 MCNC benchmarks for experimentation. Experimental results show that, on average, a homogeneous tree-based ASIF gives 64% area gain when compared to an equivalent tree-based FPGA. Further, the experiments are performed to explore the effect of look-up table (LUT) and arity size on a tree-based ASIF. Later, comparison between tree and mesh-based ASIF is performed and results show that tree-based ASIF is 12% smaller in terms of routing area and consumes 77% less wires than mesh-based ASIF. Finally the quality comparison between two ASIFs reveals that, on average, tree-based ASIF gives 33% area gain as compared to mesh-based ASIF.     

Utilizing Reverse Short-Channel Effect for Optimal Subthreshold Circuit Design

The impact of the reverse short-channel effect (RSCE) on device current is stronger in the subthreshold region due to reduced drain-induced barrier lowering (DIBL) and the exponential dependency of current on threshold voltage. This paper describes a device-size optimization method for subthreshold circuits utilizing RSCE to achieve high drive current, low device capacitance, less sensitivity to random dopant fluctuations, better subthreshold swing, and improved energy dissipation. Simulation results using ISCAS benchmark circuits show that the critical path delay, power consumption, and energy consumption can be improved by up to 10.4%, 34.4%, and 41.2%, respectively.     

Field programmable gate arrays in space

The use of field programmable gate arrays (FPGAs) in satellite and other spacecraft is on the rise. They are increasingly competitive when compared to traditional application-specific integrated circuits (ASICs). However, exposure to space radiation produces the same physical effects on both FPGAs and ASICs. How these radiation effects can translate to circuit malfunctions and how these problems can be prevented or mitigated is a complex, multifaceted issue that depends on the specific technology and the device's internal architecture. First and foremost, designers should implement a reliable ASIC/FPGA development methodology for the definition, design, verification, physical implementation and validation phases of any ASIC/FPGA to be flown as part of the spacecraft platform or critical payload. This should be contractually enforced. The European Space Agency (ESA) will continue to make available its own internal standard or any other equivalent methodology proposed by the contractor. As soon as the new ECSS standard on this subject is available, ESA will start using it as an applicable document in all projects where ASICs or FPGAs are to be developed.     

FPGAs achieve superior speed and density with antifuse advancements

FPGAs based on low-resistance, low-capacitance “antifuse” programmable elements offer very high-speed performance with small, cost-effective die sizes for high-volume production applications. FPGA vendors continue to invest in this technology to push further into the performance and density/cost realm previously dominated by conventional mask programmed ASICs. These high-performance, high-density antifuse based products will further distance themselves in speed, cost, and ease-of-use from slower, more costly RAM-based FPGAs.     

Hybrid Multi-FPGA Board Evaluation by Permitting Limited Multi-Hop Routing

Multi-FPGA Boards (MFBs) have been in use for more than a decade for implementing systems requiring high performance and for emulation/prototyping of multimillion gate chips. It is important to develop an MFB architecture which can be used for emulation or prototyping of a large number of circuits. A key feature of an MFB is its routing architecture defined by its inter-Field-Programmable Gate Array (FPGA) connections. There are two types of inter-FPGA connections, namely–fixed connections (FCs) connecting a pair of FPGAs through dedicated wires and programmable connections (PCs) which connect a pair of FPGAs through a programmable switch. An architecture which has a mix of both these type of connections is called a hybrid routing architecture. It has been shown in the literature [7] that a hybrid MFB architecture is more efficient for emulation than an architecture with only one type of connections. The cost of an MFB and delay of the emulated circuit on it depends on the number of PCs used for emulation. An objective of a designer of an MFB for circuit emulation is to minimize the required number of PCs. In this paper, we describe algorithms to evaluate the requirement of PCs for many hybrid routing architectures.The requirement of PCs can be reduced if some programmable connections are replaced by a connection using only FCs by routing through FPGAs. Such a routing is called multi-hop routing. We present an optimal and a heuristic algorithm for estimation of PCs when limited number of hops through FPGAs are permitted. The unique feature of our evaluation scheme is that it is generic and treat routing architecture as a parameter. We have used benchmark circuits as well as synthetic cloned circuits for testing our algorithms. Our heuristic algorithm is very fast and gives optimal results most of the time. Our algorithms can be used for actual routing during circuit emulation.     

Total Power Modeling in FPGAs Under Spatial Correlation

This work describes a novel approach for total power estimation in field-programmable gate arrays (FPGAs) while considering spatial correlation among the different signals in the design. The signal probabilities under spatial correlations are used to properly model the dynamic power dissipation and the state-dependency of the leakage power dissipation in the logic and routing resources of FPGAs. Moreover, the proposed model accounts for power due to glitches. The accuracy of the developed power estimation technique is compared with that of HSpice simulations and other FPGA power estimation techniques that assume spatial independence. It is found that the spatial independence assumption can overestimate power dissipation in FPGAs by an average of 19%.      

Glitch and Laser Fault Attacks onto a Secure AES Implementation on a SRAM-Based FPGA

Programmable devices are an interesting alternative when implementing embedded systems on a low-volume scale. In particular, the affordability and the versatility of SRAM-based FPGAs make them attractive with respect to ASIC implementations. FPGAs have thus been used extensively and successfully in many fields, such as implementing cryptographic accelerators. Hardware implementations, however, must be protected against malicious attacks, e.g. those based on fault injections. Protections have been usually evaluated on ASICs, but FPGAs can be vulnerable as well. This work presents thus fault injection attacks against a secured AES architecture implemented on a SRAM-based FPGA. The errors are injected during the computation by means of voltage glitches and laser attacks. To our knowledge, this is one of the first works dealing with dynamic laser fault injections. We show that fault attacks on SRAM-based FPGAs may behave differently with respect to attacks against ASIC, and they need therefore to be addressed by specific countermeasures, that are also discussed in this paper. In addition, we discuss the different effects obtained by the two types of attacks.