Current-mode square wave generators based on a single CDTA

This paper proposes two designs for current-mode square wave generators based on a current-differencing transconductance amplifier (CDTA). Both the proposed circuits are compact and employ a single CDTA with only two external passive components. The first circuit has a fixed duty-cycle topology and can generate a symmetrical square wave with variable frequency. The second circuit has a variable duty-cycle design and can operate in a current-controlled dual duty-cycle mode with a single-circuit topology. The proposed generators allow independent control of the operating frequency, output amplitude, and duty cycle by tuning diverse circuit parameters. This paper discusses several previous designs for square wave generators and presents the circuit principles, related governing formulas, and nonideal problems for the proposed circuits. In addition, computer simulations and experimental results, which are consistent with those of the theoretical analyses and confirm the feasibility of the new generators, are presented.     

Low-cost SI-POF analogue TIA and equaliser

This article proposes the two first blocks of an analogue front-end suitable for plastic optical fibre systems suitable for the standard IEEE 1394. These blocks consist of a preamplifier followed by an equaliser which employs low-cost commercial components and are designed with two different bipolar technologies. With a supply voltage of 3.3?V, the front-end consumes 396?mW. The total gain is 70?dBΩ and it operates at up to 800?Mb/s. At this bit rate, with fibre lengths of up to 30?m, the circuit has a BER?≤?10^?12 and a maximum jitter of 170?ps_rms.     

Comparative study of signalling methods for high-speed backplane transceiver

A combined analysis of transient simulation and statistical method is proposed for comparative study of signalling methods applied to high-speed backplane transceivers. This method enables fast and accurate signal-to-noise ratio and symbol error rate estimation of a serial link based on a four-dimension design space, including channel characteristics, noise scenarios, equalisation schemes, and signalling methods. The proposed combined analysis method chooses an efficient sampling size for performance evaluation. A comparative study of non-return-to-zero (NRZ), PAM-4, and four-phase shifted sinusoid symbol (PSS-4) using parameterised behaviour-level simulation shows PAM-4 and PSS-4 has substantial advantages over conventional NRZ in most of the cases. A comparison between PAM-4 and PSS-4 shows PAM-4 gets significant bit error rate degradation when noise level is enhanced.     

Intra-panel interface with clock-embedded differential signalling for large size digital television

Return to zero (RZ) and non-return to zero (NRZ) pulse formats are compared for multimode optical fibre systems. In both cases, the receiver filter bandwidth is optimized assuming a gaussian receiver filter response. In the case of 90 Mbps systems, the optimum bandwidth was found to be 0·6 times the symbol rate and 0·5 times the symbol rate for RZ and NRZ, respectively. Performances were evaluated at a 10^-11 bit error rate and NRZ showed a 1·5 dB peak optical power advantage over RZ when there was no band limitation by the fibre. However, NRZ superiority was found to be small when there was a significant fibre bandwidth limitation.     

Current-mode full-duplex (CMFD) signaling for high-speed chip-to-chip interconnect

In this work we propose a new current-mode full-duplex (CMFD) signaling scheme for high-speed chip-to-chip data communication. In this scheme, all the internal nodes of the link are maintained at low-impedance, facilitating high-speed data communication. A new hybrid circuit topology required for separating the inbound signal from the outbound signal is presented. The proposed current-mode hybrid is realized by a source-coupled main driver, a scaled down replica stage and a common-gate (CG) transimpedance amplifier (TIA). Detailed design, analysis, noise and jitter characterization of the proposed hybrid is presented. The hybrid is realized in 1.8 V, digital CMOS technology. Using this hybrid circuit topology, CMFD signaling over a chip-to-chip interconnect is demonstrated. The post-layout performance shows 8 Gb/s data transfer rate over a FR4 PCB trace of length 7.5 in. for a target bit-error rate (BER) of 10⁻¹². The FR4 PCB trace is modeled by measured 4-port S-parameters in the frequency range from 100 MHz to 20 GHz. The input-referred noise current of the receiver and output-noise voltage of transmitter are and 5.34 mV, respectively. The standalone power consumption of the hybrid is 14.64 mW.     

高速SPI接口在OSD中的应用

面对日益华丽的OSD开发,出现了加载OSD信息的速度瓶颈。设计基于SPI总线,在FLASH与视频字符处理模块之间建立一条高速通道。该设计使用Verilog HDL语言实现RTL设计,详细阐述了高速SPI的设计思路,详细说明了IP核的系统架构,接口信号和子模块设计。经过FPGA验证结果表明,传输速率大幅度提高,满足在了OSD应用中高带宽的速度要求。     

一种适应于flash memory的超低压和高速的感应放大器设计

A new low-voltage and high-speed sense amplifier is presented, based on a very simple direct current-mode comparison. It adopts low-voltage reference current extraction and a dynamic output method to realize its performance indicators such as low voltage, low power and high precision. The proposed amplifier can sense a 0.5 μ A current gap and work with a lowest voltage of 1 V. In addition, the current power of a single amplifier is optimized by 15%.     

应用于10Gb/s光接收机的全差分CMOS跨阻前置电路设计

设计了一种的低成本、低功耗的10 Gb/s光接收机全差跨阻前置放大电路。该电路由跨阻放大器、限幅放大器和输出缓冲电路组成,其可将微弱的光电流信号转换为摆幅为400 mVpp的差分电压信号。该全差分前置放大电路采用0.18 m CMOS工艺进行设计,当光电二极管电容为250 fF时,该光接收机前置放大电路的跨阻增益为92 dB,-3 dB带宽为7.9 GHz,平均等效输入噪声电流谱密度约为23 pA/(0~8 GHz)。该电路采用电源电压为1.8 V时,跨阻放大器功耗为28 mW,限幅放大器功耗为80 mW,输出缓冲器功耗为40 mW,其芯片面积为800 m1 700 m。     

A new low-voltage and high-speed sense amplifier for flash memory

A new low-voltage and high-speed sense amplifier is presented,based on a very simple direct current-mode comparison.It adopts low-voltage reference current extraction and a dynamic output method to realize its performance indicators such as low voltage,low power and high precision.The proposed amplifier can sense a 0.5μA current gap and work with a lowest voltage of 1V.In addition,the current power of a single amplifier is optimized by 15%.     

模块化高速计算机数据接口系统的设计和实现

为了满足高速数字系统的数据处理需求,实现数字前端与计算机之间的高速通信,设计并实现了一种基于FMC规范和PCI-Express协议的数据接口系统.对该接口系统的硬件系统的基本构成、在FPGA上实现基于PCI-E协议的高速数据传输及基于FMC规范的高度模块化硬件设计做了详细论述.该系统的传输速率可达34Gbps,且可以根据不同的数字前端进行通信接口模块调整.     

Current conveyor-based differential capacitance analog interface for displacement sensing application

A current conveyor-based analog electronic interface for differential capacitive sensors is here shown. The read-out circuit that utilizes second generation Current Conveyors (CCIIs) as active blocks is able to evaluate differential capacitive variations performing a capacitance-to-voltage conversion. This solution has been implemented both in a discrete element board and as integrated version in a standard 350  nm CMOS technology. Simulations and experimental results have shown a linear input/output characteristic and a good agreement with theoretical expectations, being the former performed for both the designed solutions, whereas the latter only for a discrete prototype board (employing a low cost commercial component (AD844). Sensitivity and resolution data on a practical case-study of a displacement sensor are constant and their values are satisfactory. Both simulated and measured results make the proposed architecture a good candidate as first stage of analog front-ends to be employed in differential capacitive instrumentation.     

基于USB3.0接口高速数据采集系统的设计

针对当前爆炸场测量中存在存储测试系统数据传输慢,经常出现丢点问题,综合运用数据采集技术、存储测试技术,设计了一种基于USB3.0的高速数据采集系统,采用并行采样技术,用两片采样率高达500 Msample/s的A/D芯片,实现高速并行数据采集,该采集系统将在XX爆炸威力试验场的模拟信号,经过模数转换送入FPGA中,再通过USB3.0接口高速传输给上位机,数据存储采用分时存储技术;该设计方法有效地解决了大容量数据采集过程中的数据的高速传输和存储问题。     

一种分段隔离差分总线接口电路

全双工差分并行总线广泛应用在邮政与物流自动化分拣设备上,但较长的总线在工程应用中对安装、维护和驱动能力等可能造成不利影响。本文提出一种分段隔离差分总线接口电路,应用在长总线的每个节点电路,此电路作为主控机与其相邻模块电路之间、模块电路与模块电路之间的总线接口电路。它既兼容控制系统的原通讯协议,又能对主控机和各模块之间的电路进行了电气隔离,可将一条长总线分割成若干段,每段的长度为主控机到相邻模块距离或两相邻模块间距离。此电路的应用方便了安装和维护,并能提高总线信号的驱动能力和抗干扰性能。     

高速电路设计与库模型应用的研究

通过对TSMC 0．18μm CMOS工艺库模型的分析，电路仿真结果比较以及实际限幅放大器电路流片测试结果的验证比较，提出在深亚微米工艺中，大信号高速电路的设计适宜选用混合信号管进行。     

A novel low-voltage low-power fully differential voltage and current gained CCII for floating impedance simulations

In this paper we present a new current-mode basic building block that we named voltage and current gained second generation current conveyor (VCG-CCII). The proposed active block allows to control and tune both the CCII current gain and the voltage gain through external control voltages. It has been designed, at transistor level in a standard CMOS technology (AMS 0.35 μm), with a low single supply voltage (2 V), as a fully differential active block. The proposed integrated solution, having both low-voltage (LV) and low-power (LP) characteristics, can be applied with success in suitable IC applications such as floating capacitance multipliers and floating inductance simulators, utilizing a minimum number of active components (one and two, respectively). Simulation results, related to floating impedance simulators, are in good agreement with the theoretical expectations.     

卫星通信终端通用测试平台高速接口设计

卫星通信系统向多频段多体制发展的趋势对卫星通信终端测试平台的通用性提出了更高的要求,基于通用处理器的软件无线电(GPP-SDR)技术可用于解决该问题。但目前GPP-SDR处理器和射频前端之间的高速数据传输仍是主要的技术瓶颈。本文针对卫星通信终端通用测试平台需求,提出了基于中断机制的PCI-e高速传输方法和流程设计,并通过移植Xenomai操作系统对高速接口传输的实时性进行优化;设计了一系列的测试实验对所设计接口的实际传输速率和中断丢失概率等指标进行测试。实验结果验证了所提方案具备高速率和低时延的传输特性,能够很好地满足当前卫星通信终端通用测试需求。     

Physical-layer air interface solutions for broadband high-speed wireless cellular systems

We propose the physical-layer (PHY) air interface solutions for downlink and uplink transmissions in broadband high-speed wireless cellular systems. A system based on low-density parity-check (LDPC) coded multiple-input-multiple-output (MIMO) orthogonal frequency-division multiplexing (OFDM) time-division multiple-accessing (TDMA) (with scheduling) is proposed for downlink transmission; and a system based on orthogonal space-time block coded (STBC) multi-carrier code-division multiple-accessing (MC-CDMA) is proposed for uplink transmission. The proposed scheme can support ∼100 Mbps peak rate over 25 MHz bandwidth downlink channels and ∼30 Mbps sum rate of multiple users over 25 MHz uplink channels. Moreover, the proposed solutions provide excellent performance and reasonable complexity for mobile station and for base station. Ben Lu received the B.S. and M.S. degrees in electrical engineering from Southeast University, Nanjing, China, in 1994 and 1997; the Ph.D. degree from Texas A & M University in 2002. From 1994 to 1997, he was a Research Assistant with National Mobile Communications Research Laboratory at Southeast University, China. From 1997 to 1998, he was with the CDMA Research Department of Zhongxing Telecommunication Equipment Co., Shanghai, China. From 2002 to 2004, he worked for the project of high-speed wireless packet data transmission (4G prototype) at NEC Laboratories America, Princeton, New Jersey. He is now with Silicon Laboratories. His research interests include the signal processing and error-control coding for mobile and wireless communication systems. Xiaodong Wang received the B.S. degree in Electrical Engineering and Applied Mathematics (with the highest honor) from Shanghai Jiao Tong University, Shanghai, China, in 1992; the M.S. degree in Electrical and Computer Engineering from Purdue University in 1995; and the Ph.D degree in Electrical Engineering from Princeton University in 1998. From July 1998 to December 2001, he was an Assistant Professor in the Department of Electrical Engineering, Texas A&M University. In January 2002, he joined the faculty of the Department of Electrical Engineering, Columbia University. Dr. Wang’s research interests fall in the general areas of computing, signal processing and communications. He has worked in the areas of digital communications, digital signal processing, parallel and distributed computing, nanoelectronics and bioinformatics, and has published extensively in these areas. Among his publications is a recent book entitled “Wireless Communication Systems: Advanced Techniques for Signal Reception”, published by Prentice Hall, Upper Saddle River, in 2003. His current research interests include wireless communications, Monte Carlo-based statistical signal processing, and genomic signal processing. Dr. Wang received the 1999 NSF CAREER Award, and the 2001 IEEE Communications Society and Information Theory Society Joint Paper Award. He currently serves as an Associate Editor for the IEEE Transactions on Communications, the IEEE Transactions on Wireless Communications, the IEEE Transactions on Signal Processing, and the IEEE Transactions on Information Theory. Mohammad Madihian (S’78-M’83-SM’88-F’98) received his Ph.D in electronic engineering from Shizuoka University, Hamamatsu, Japan, in 1983. He is presently the Chief Patent Officer and Department Head, NEC Laboratories America, Inc., Princeton, New Jersey, where he conducts Microwave as well as PHY/MAC layer signal processing activities for high-speed wireless networks and personal communications applications. He holds 35 Japan/US patents and has authored/co-authored more than 130 technical publications including 25 invited talks. He has received 8 NEC Distinguished R&D Achievement Awards, the 1988 IEEE MTT-S Best Paper Microwave Prize, and 1998 IEEE Fellow Award. He has served as Guest Editor to the IEEE Journal of Solid-State Circuits, Japan IEICE Transactions on Electronics, and IEEE Transactions on Microwave Theory and Techniques. He is currently serving on the IEEE Speaker’s Bureau, IEEE Compound Semiconductor IC Symposium Executive Committee, IEEE Radio and Wireless Symposium Executive Committee, IEEE International Microwave Symposium Technical Program Committee, IEEE MTT-6 Subcommittee, IEEE MTT Editorial Board, and Technical Program Committee of International Conference on Solid State Devices and Materials. Dr. Madihian is an Adjunct Professor at Electrical and Computer Engineering Department, Drexel University, Philadelphia, Pennsylvania.