一种具有快速锁定特性的自适应锁相环设计

基于传统电荷泵锁相环(CP-PLL)系统结构设计了一个具有快速锁定特性,环路带宽自适应调节的锁相环。对其中的电荷泵(CP)、低通滤波器(LPF)和环形振荡器(VCO)子模块电路采用了新颖的设计,用UMC 0.18μMix-mode CMOS工艺实现了电路,仿真结果表明系统有较高的性能,适用于USB2.0等高速串行数据传输系统。     

一个简单鉴频鉴相器结构实现的快速锁定低抖动锁相环

用简单的鉴频鉴相器结构实现了一个快锁定低抖动的锁相环.鉴频鉴相器仅仅由两个异或门组成,它可以同时获得低抖动和快锁定的性能.锁相环中的电压控制振荡器由四级环形振荡器来实现,每级单元电路工作在相同的频率,并提供45°的相移.芯片用0.18μm CMOS工艺来实现.PLL输出的中心频率为5GHz,在偏离中心频率500kHz处,测量的相位噪声为-102.6dBc/Hz.锁相环的捕获范围为280MHz,RMS抖动为2.06ps.电源电压为1.8V时,功耗仅为21.6mW(不包括输出缓冲).     

一个简单鉴频鉴相器结构实现的快速锁定低抖动锁相环

用简单的鉴频鉴相器结构实现了一个快锁定低抖动的锁相环.鉴频鉴相器仅仅由两个异或门组成,它可以同时获得低抖动和快锁定的性能.锁相环中的电压控制振荡器由四级环形振荡器来实现,每级单元电路工作在相同的频率,并提供45°的相移.芯片用0.18μm CMOS工艺来实现.PLL输出的中心频率为5GHz,在偏离中心频率500kHz处,测量的相位噪声为-102.6dBc/Hz.锁相环的捕获范围为280MHz,RMS抖动为2.06ps.电源电压为1.8V时,功耗仅为21.6mW(不包括输出缓冲).     

Design of a PLL with improved locking range and its biomedical applications

This paper describes a phase locked loop employing a low voltage VCO using modified ECL inverter cells. The VCO circuit employed, features a positive feed back scheme to improve the operating frequency. The phase detector used in the PLL also uses a positive feedback scheme to improve the locked range and to reduce supply voltage of operation of the entire circuit. An improvement of locked range of around 35% was obtained from circuit simulation (using PSPICE) as well as from practical circuit, using discrete components. The minimum supply voltage required here is 2.5 volts. Some biomedical applications of this PLL are also proposed.     

CMOS电荷泵锁相环中鉴频鉴相器的研究与设计

介绍了鉴频鉴相器(PFD)在其发展过程中产生的结构,并对每一种结构的优缺点进行了比较。通过对原有PFD电路结构进行重新设计,在传统D触发器PFD的基础上提出了两种新型PFD:传输门D触发器型PFD和基于锁存器的PFD。电路设计基于TSMC公司的0.18μm CMOS工艺,仿真环境为Candence Spectre,仿真结果显示电路可以工作在2GHz以上频率的应用环境下。相对于传统的PFD,新型PFD工作频率高、几乎无死区,而且具有噪声低、速度快的优点,在高速、低抖动、低噪声PLL中将有广泛的应用前景。     

An Analytical Approximation for the Pull‐Out Frequency of a PLL Employing a Sinusoidal Phase Detector

The pull‐out frequency of a second‐order phase lock loop (PLL) is an important parameter that quantifies the loop's ability to stay frequency locked under abrupt changes in the reference input frequency. In most cases, this must be determined numerically or approximated using asymptotic techniques, both of which require special knowledge, skills, and tools. An approximating formula is derived analytically for computing the pull‐out frequency for a second‐order Type II PLL that employs a sinusoidal characteristic phase detector. The pull‐out frequency of such PLLs can be easily approximated to satisfactory accuracy with this formula using a modern scientific calculator.     

A new all-digital phase-locked loop with high precision and low jitter

A new method is proposed in this article to accomplish the fine tune unit of the digitally controlled oscillator of an all-digital phase-locked loop (ADPLL). Instead of using adjustable currents, we utilise the difference of the equivalent capacitance obtained from the drain of MOS transistors between on and off states as the fine tune delay parameter. Based on post-layout simulation results, the time resolution of the fine tune delay element can achieve results as good as 1.7126 ps. The operating frequency of this presented ADPLL ranges from 308 to 587 MHz. As compared to prior arts, the power consumption per MHz is reduced over 15% and the jitter is as low as 5 ps, which is a significant improvement.     

A compact ADPLL based on symmetrical binary frequency searching with the same circuit

A compact all-digital phase-locked loop (C-ADPLL) based on symmetrical binary frequency searching (BFS) with the same circuit is presented in this paper. The minimising relative frequency variation error Δη (MFE) rule is derived as guidance of design and is used to weigh the accuracy of the digitally controlled oscillator (DCO) clock frequency. The symmetrical BFS is used in the coarse-tuning process and the fine-tuning process of DCO clock frequency to achieve the minimum Δη of the locked DCO clock, which simplifies the circuit architecture and saves the die area. The C-ADPLL is implemented in a 0.13 μm one-poly-eight-metal (1P8M) CMOS process and the on-chip area is only 0.043 mm², which is much smaller. The measurement results show that the peak-to-peak (Pk-Pk) jitter and the root-mean-square jitter of the DCO clock frequency are 270 ps at 72.3 MHz and 42 ps at 79.4 MHz, respectively, while the power consumption of the proposed ADPLL is only 2.7 mW (at 115.8 MHz) with a 1.2 V power supply. The measured Δη is not more than 1.14%. Compared with other ADPLLs, the proposed C-ADPLL has simpler architecture, smaller size and lower Pk-Pk jitter.     

Jitter and phase noise of ADPLL due to PSN with deterministic frequency

In this article, jitter and phase noise of all-digital phase-locked loop due to power supply noise (PSN) with deterministic frequency are analysed. It leads to the conclusion that jitter and phase noise heavily depend on the noise frequency. Compared with jitter, phase noise is much less affected by the deterministic PSN. Our method is utilised to study a CMOS ADPLL designed and simulated in SMIC 0.13?µm standard CMOS process. A comparison between the results obtained by our method and those obtained by simulation and measurement proves the accuracy of the predicted model. When the digital controlled oscillator was corrupted by PSN with 100?mVpk-pk, the measured jitters were 33.9?ps at the rate of f_G?=?192?MHz and 148.5?ps at the rate of f_G?=?40?MHz. However, the measured phase noise was exactly the same except for two impulses appearing at 192 and 40?MHz, respectively.     

一种锁相频率合成系统的设计

描述了以MC145152和MC1648芯片为核心,采用锁相频率合成技术来实现电压控制LC振荡器的设计思路、方法及指标测试。本系统可以产生高稳定度的正弦信号,输出频带在5~25 MHz范围内,并实时显示;输出频率的稳定度达到10-3以上。该系统在通信领域有广泛的应用前景。     

用步进锁相扫描技术改进VCO线性及调频带宽稳定性

选用HMC703LP4E小数频率综合器与专门设计的有源环路滤波器和商用VCO构成了步进扫描数字锁相环,改进了调频连续波的调频带宽稳定性和调频线性度。对设计的电路进行了制作和测试,实验结果表明在-30^+70℃温度范围内,调频信号的稳定度达到了1×10^-6,调频线性度接近于1.0,相位噪声为-90 dBc/Hz/10 kHz。     

锁相环敏感模块的单粒子效应与设计加固

应用于航天工程的锁相环(PLL)电路遭受太空高能粒子轰击时会发生单粒子效应(SEE),引起电路失锁,对系统造成灾难性影响.分析了鉴频鉴相器(PFD)和分频器(DIV)模块的单粒子效应导致失锁的机理,运用改进的双互锁结构(DICE)的锁存器和冗余触发器电路分别对其进行设计加固(RHBD),基于0.35μm CMOS工艺设计了加固的锁相环电路.仿真结果表明,加固PLL可以对输入20～40 MHz的信号完成锁定并稳定输出320～ 640 MHz的时钟信号.在250fC能量单粒子轰击下加固后PFD模块不会造成PLL失锁,加固DIV模块的敏感节点数目降低了80％.     

基于锁相环的Chirp超宽带信号源的设计与实现

在传统的模拟法产生Chirp超宽带信号的基础上,提出了一种基于锁相环（PLL）法的Chirp超宽带信号源设计方案。与传统的模拟方法相比,该方法产生的Chirp超宽带信号载频稳定性高,能够达到参考信号的频率稳定度。从理论上分析了该方法的可行性,并用相应的硬件电路实现了基于PLL的Chirp超宽带信号源。实验结果表明,该方法设计出的Chirp超宽带信号源具有易实现,稳定度高,灵活性和实用性强等优点。     

A voltage-controlled oscillator with an ultra-low supply voltage and its application to a fractional-N phase-locked loop

With feature size scaling, the supply voltage of digital circuits is becoming lower and lower. As a result, the supply voltage of analogue and RF circuits must also be reduced for system on chip (SoC) realisation. This article proposes an ultra-low-supply voltage-controlled oscillator (ULSVCO) and designs a sigma–delta fractional-N frequency synthesiser which adopts such ULSVCO. A mathematical phase-noise model is built here to describe the noise performance of the low-supply voltage-controlled oscillator (VCO). The substrate of the cross-coupled NMOSFETs in the proposed ULSVCO is not grounded but connected to the supply to further reduce the supply voltage. Implemented in 0.18 μm CMOS technology, the proposed ULSVCO can be operated at a supply voltage as low as 0.41 V, the central frequency is set to 1.55 GHz, the phase noise is ?116 dBc/Hz@1.0 MHz. The minimum supply voltage is decreased by about 11% after our idea is adopted and the power consumption of the ULSVCO is only 1.04 mW. With the proposed ULSVCO, we design a sigma–delta-modulator (SDM) fractional-N phase-locked loop frequency synthesiser, which has a 1.43–1.75 GHz frequency tuning range. When the loop bandwidth is set to 100 KHz, the phase noise of our PLL is ?110 dBc/Hz@1.0 MHz.     

一种500MHz高性能锁相环的设计

随着专用集成芯片（ASIC）和系统芯片（SOC）的飞速发展,芯片内部生成可变频率的稳定时钟变得至关重要,设计一个高性能锁相环正是适应了这样的需求。本文在传统锁相环结构的基础上设计了一种高速、低功耗、低噪声的高性能嵌入式混合信号锁相环结构。它可以在片内产生多分组高频稳定时钟信号,从而为先进的专用集成芯片（ASIC）和系统芯片（SOC）的实现提供最基础且最重要的可应用时钟产生电路。模拟结果表明：该锁相环可稳定输出500 MHz时钟信号,稳定时间小于700ns,在1．8V电源下的功耗小于18mW,噪声小于180mV。     

一种500MHz高性能锁相环的设计

在传统锁相环结构的基础上设计了一种高速、低功耗、低噪声的高性能嵌入式混合信号锁相环结构.它可以在片内产生多分组高频稳定时钟信号,从而为先进的专用集成芯片(ASIC)和系统芯片(SOC)的实现提供最基础且最重要的可应用时钟产生电路.模拟结果表明,该锁相环可稳定输出500MHz时钟信号,稳定时间小于700 ns,在1.8V电源下的功耗小于18mW,噪声小于180mV.     

基于辅助捕获的锁相环性能分析与仿真

锁相环作为测控系统中的重要工具,主要研究其信号捕获问题。而环路带宽的选择是目前锁相环研究中的重大难题。针对环路带宽大小的选择与对环路输入噪声的抑制和频率的牵引之间的相互制约关系,本文分析了传统锁相环的基本理论和构成,建立了辅助捕获锁相环的数学模型。通过仿真,给出了不同条件下的相轨迹和时间响应图以及任意初始相差对应的捕获带。实验表明,此方法有效解决了环路带宽与噪声滤除和频率牵引之间的矛盾,在工程应用中具有一定的指导意义。     

一种高性能鉴频鉴相器的设计

分析了电荷泵型锁相环中鉴相器和电荷泵的非理想因素及优化设计方法。基于台积电公司(TSMC)0.35μm 2层多晶硅4层金属(2P4M)CMOS工艺,设计了一种低杂散的鉴频鉴相器结构,该结构通过"自举"的方法,用单位增益放大器使充放电前后开关管各节点处的电压保持不变,从而消除了电荷共享的影响,减小了鉴相器的输出杂散。仿真结果表明相比于传统鉴相器结构,该鉴频鉴相器有效抑制了电荷共享问题,电荷泵开关管开启时的充放电电流尖峰大大减小了,鉴相前后的电压波动小于200μV,脉冲尖峰仅为3.07 mV,有效降低了鉴频鉴相器的输出杂散。     

A modified closed-loop auto frequency calibration technique for a 1.571-GHz integer-N PLL

In this paper, a modified closed-loop auto frequency calibration technique (MCL-AFC) is adopted in an integer-N phase-locked loop (PLL) for GPS-L1 application. The ignorance of circuit initial conditions setting in the closed-loop AFC may cause the start-up trap and long frequency calibration time. To solve these problems, the MCL-AFC technique is introduced. The process of MCL-AFC is listed below: first, initialisation process is only used for start-up of PLL; second, closed-loop voltage comparison process and open-loop switching process will take place alternately until optimum frequency control words are obtained. Tuning voltage searching range is reduced by half during the voltage comparison process since VCO’s tuning voltage is set to half of supply voltage through switching process. The MCL-AFC circuit is implemented in a 1-poly 6-metal 180 nm CMOS process and its chip area is 0.0167 mm². The measured locked output frequency of the PLL is 1.571 GHz and the out-band phase noise is ?131.9dBc/Hz at 1 MHz. The calibration time of PLL with MCL-AFC circuit is reduced to only 5µs while whole locking time is about 10.2µs.