Modeling of capacitor impedance in switching converters

Switched capacitor (SC) converters are gaining acceptance as alternatives to traditional, inductor-based switching power converters. Proper design of SC converters requires an understanding of all loss sources and their impacts on circuit operation. In the present work, an equivalent resistance method is developed for analysis, and equivalent resistance formulae are presented for various modes of operation. Quasiresonant converters are explored and compared to standard SC converters. Comparisons to inductor-based switching power converters are made. A number of capacitor technologies are evaluated and compared for applications to both SC converters and inductor-based converters. The resulting model can be used to accurately predict and optimize converter performance in the design phase.     

Extended operation of flying capacitor multilevel inverters

Recent research in flying capacitor multilevel inverters (FCMIs) has shown that the number of voltage levels can be extended by changing the ratio of the capacitor voltages. For the three-cell FCMI, four levels of operation are expected if the traditional ratio of the capacitor voltages is 1:2:3. However, by altering the ratio, the inverter can operate as a five-, six-, seven-, or eight-level inverter. According to previous research, the eight-level case is referred to as maximally distended (or full binary combination schema) since it utilizes all possible transistor switching states. However, this case does not have enough per-phase redundancy to ensure capacitor voltage balancing under all modes of operation. In this paper, redundancy involving all phases is used along with per-phase redundancy to improve capacitor voltage balancing. It is shown that the four- and five-level cases are suitable for motor drive operation and can maintain capacitor voltage balance under a wide range of power factors and modulation indices. The six-, seven-, and eight-level cases are suitable for reactive power transfer in applications such as static var compensation. Simulation and laboratory measurements verify the proposed joint-phase redundancy control.     

Pipelined multibit oversampled digital-to-analog converters with capacitor averaging

A combination of pipelined architecture and dynamic element matching technique is applied to multibit oversampled D/A (digital to analog) converters. The approach translates the harmonic distortion components of the nonideal internal DAC (digital-to-analog converter) of the oversampled DAC to high-frequency components, which can then be filtered out by the analog low-pass filter for anti-imaging. Computer simulations have confirmed that with this approach a third-order oversampled DAC employing a 3-bit quantizer, a 3-bit pipelined internal DAC with a random mismatch of 0.1%, can achieve a 94-dB dynamic range with an oversampling ratio of 64 while eliminating the harmonic distortion.This work was supported by NSERC (Canada).     

A unique fault-tolerant design for flying capacitor multilevel inverter

This paper presents a unique design for flying capacitor type multilevel inverters with fault-tolerant features. When a single-switch fault per phase occurs, the new design can still provide the same number of converting levels by shorting the fault power semiconductors and reconfiguring the gate controls. The most attractive point of the proposed design is that it can undertake the single-switch fault per phase without sacrificing power converting quality. Future more, if multiple faults occur in different phases and each phase have only one fault switch, the proposed design can still conditionally provide consistent voltage converting levels. This paper will also discuss the capacitor balancing approach under fault-conditions, which is an essential part of controlling flying capacitor type multilevel inverters. Suggested fault diagnosing methods are also discussed in this paper. Computer simulation and lab results validate the proposed controls.     

A generalized Undeland snubber for flying capacitor multilevel inverter and converter

This paper proposes a snubber circuit for a flying capacitor multilevel inverter and converter. It also explains the concept of constructing a snubber circuit for a multilevel inverter and converter. The proposed snubber circuit makes use of an Undeland snubber as a basic snubber unit, and thus can be regarded as a generalized Undeland snubber for a flying capacitor multilevel inverter and converter. It has such an advantage of Undeland snubber used in the two-level inverter. Compared with a conventional RLD/RCD snubber for multilevel inverter and converter, the proposed snubber keeps such good features as fewer number of components, reduction of voltage stress of main switching devices due to low overvoltage, and improved efficiency of system due to low snubber loss. In this paper, the proposed snubber is applied to a three-level flying capacitor inverter, and its features are in detail demonstrated by computer simulation and experimental result.     

Switching faults and safe control of an ARCP multicell flying capacitor inverter

The auxiliary resonant commutated pole (ARCP) multicell converter is a soft-switched variant of the multicell converter. It is shown in this paper that the ARCP technique can be very efficiently used in multicell flying capacitor converters. The main properties of the resulting soft switching multicell converter are very similar to those of the hard-switched version. They are presented and validated by simulations as well as experimental results. In practice, due to the damping, the ARCP multicell converter can suffer from switching faults as in two-level ARCP inverters, but in the case of a multicell converter failures can occur in different cells. So, the main control strategies are evaluated and the switching process is discussed step by step, taking account of the main imperfections of actual control circuits. When they can occur, the switching faults are described and analyzed. Finally, an original quasisoft switching control that should give a high safety of operation is proposed. Experimental results obtained with a 900 V-100 A ARCP multicell inverter leg are given and the performances are compared with those of a hard-switched multicell inverter leg of the same rating.     

Phase-controlled multilevel converters based on dual structureassociations

Multilevel converters, like neutral-point-clamped inverters or multilevel choppers, are particularly attractive in high-power applications. Nevertheless, in these structures, all switches are confronted to commutation stresses caused by their turn-on and turn-off control. Furthermore, the methods to balance the capacitor voltages or to control the neutral point voltage are complex enough. In this paper, the authors propose new multilevel converters based on series connection of zero-current-source (ZCS) inverter cells and parallel connection of zero-voltage-source (ZVS) inverters. These dual structure associations give soft-switching operation for all switches and allow the use of semiconductors, normally destined for medium-power applications, in high-power converters (up to 1 MW). The authors consider the structure design for several topologies to achieve DC-DC or DC-AC converters. The simulation results validate the simplicity of phase control techniques and give out the principal features of different topologies     

DSP-based control of a high frequency three cell flying capacitor inverter

The design, instrumentation and early operation results of a digitally controlled voltage source inverter (VSI) are described. This inverter has been structured from a three cell flying capacitor inverter (TCFCI). Two different inverter control modes – open-loop and closed-loop – are applied by a digital system based on a Texas Instrument TMS320C6713 digital signal processor (DSP) board. The VSI is able to generate AC voltage signals up to 120 V amplitudes at a maximal 6 A current, from ～9 kHz to ～60 kHz in ～900 Hz steps in both controls by varying the signal period through the square-wave command strategy. The multi-cell structure of the inverter provides an output frequency nearly three times that of the TCFCI semiconductor commutation. The power output of the TCFCI can drive a high frequency step-up transformer which, in turn, is associated with a cylindrical reactor where dielectric barrier discharges (DBD) are conducted.     

Forward converters for dual voltage switched reluctance motordrives

A new circuit is presented which allows a switched reluctance motor to operate from AC mains or a low voltage battery supply. In addition the AC mains can be used to charge the battery. The switched reluctance motor is used as the voltage-changing transformer, potentially reducing the cost of the system. The operation of the drive is explained, and results of an experimental prototype are presented     

Capacitor voltage balancing in full binary combination schema flying capacitor multilevel inverters

Recently, the full binary combination schema (FBCS) method has been introduced to control the flying capacitor multilevel inverter. This method has the primary advantage that the number of voltage levels can be increased for a given number of semiconductor devices when compared to the conventional control methods. However, due to the difficulty of balancing the capacitors, the new schema requires fixed floating sources to provide the DC voltages. This paper reveals an approach of balancing the capacitors, thus expanding the application fields of FBCS inverters to the family of the flying capacitor multilevel inverters under the condition of choosing a suitable modulation index. Simulation results demonstrate the proposed voltage balancing control.     

True noninverting integrators with single grounded capacitor

Four new active integrator configurations are reported. All the circuits use single grounded capacitors.     

A capacitor modeling method for integrated magnetic components in DC/DC converters

For the special case of dc/dc converters, the gyrator-capacitor model is revised by replacing gyrators with current sources to symbolize the electrical actions on windings. The revised capacitor model is suitable for analyzing integrated magnetic components. Several examples illustrate the usage of this approach. Comparisons between the revised capacitor model and the conventional reluctance model for magnetic calculation and integration are presented.     

Parasitic insensitive single amplifier switched capacitor bandpass biquad

Switched capacitor biquads based on a loop consisting of two integrators generally require two operational amplifiers. A bandpass biquad is proposed which is derived by following a different philosophy based on successive voltage inversions. This allows the use of a single operational amplifier and the realisation of a bilinear transformed continuous-time transfer function.<>     

Characteristic curves for analysing limit cycle behaviour inswitching converters

The concept of characteristic curves (CCs) for analysing the behaviour of limit cycles in elementary DC-DC switching converters is introduced. The CC is derived by considering opposite vector fields in the on and off configurations. Feedback regulated converters with PWM or hysteresis control are investigated using this approach     

基于双DSP的大功率变流器通用控制平台的设计

介绍一种大功率变流器通用控制平台,是以TMS320C6713B为浮点算法运算核,TMS320F2812为系统定点控制核的双DSP的控制系统架构.详细分析该系统设计各模块硬件电路和软件程序设计.该系统控制平台运算性能强,具有很好的通用性和扩展性,已成功应用于400 kVA岸电电源样机中.     

A new family of zero-voltage-transition PWM converters with dual active auxiliary circuits

A new family of active auxiliary circuits that allow the power switch in single switch, pulsewidth modulated converters to operate with zero-voltage switching is proposed in this paper. The main feature of an auxiliary circuit belonging to this family is that the auxiliary switch can operate with a zero-current switching turn-on and turn-off without increasing the peak current stresses of the main switch. This is an improvement over previous proposed auxiliary circuits where either the auxiliary switch operates with a hard turn-off or the circuit itself increases the peak stresses of the main switch. In this paper, the fundamental principles behind the proposed family of active auxiliary circuits are explained. Based on these principles, an example auxiliary circuit is systematically derived and presented along with several other auxiliary circuits belonging to the new family. The operation of a boost converter operating with the example auxiliary circuit is discussed in detail, and general guidelines for the design and implementation of auxiliary circuits belonging to the new family are given. The feasibility of the example auxiliary circuit is confirmed by experimental results obtained from a 500-W, 100-kHz boost converter laboratory prototype.     

Cascadable allpass filter with a single DO-CCII and a grounded capacitor

In the literature sufficient emphasis has not been given to dual-output current conveyors in all-pass filter designs. In this study, a cascadable voltage-mode all-pass filter with a grounded capacitor using a single dual-output current conveyor has been reported.     

A low-power ROM using single charge-sharing capacitor and hierarchical bit line

This paper describes a low-power read-only memory (ROM) using a single charge-sharing capacitor (SCSC) and hierarchical bit line (HBL). The SCSC-ROM reduces the power consumption in bit lines. It lowers the swing voltage of bit lines to a minimal voltage by using a charge-sharing technique with a single capacitor. It implements the capacitor with dummy bit lines to improve noise immunity and to make it easier to design. Furthermore, the HBL saves power by reducing the capacitance and leakage current in bit lines. The SCSC-ROM also reduces the power consumption in control unit and predecoder by using the hierarchical word line decoder. The simulation result shows that the SCSC-ROM with 4 K/spl times/32 bits consumes only 37% power of a conventional ROM. An SCSC-ROM chip is fabricated in a 0.25-/spl mu/m CMOS process. It consumes 8.2 mW at 240 MHz with 2.5 V.     

Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor

An analysis of an on-chip buck converter is presented in this paper. A high switching frequency is the key design parameter that simultaneously permits monolithic integration and high efficiency. A model of the parasitic impedances of a buck converter is developed. With this model, a design space is determined that allows integration of active and passive devices on the same die for a target technology. An efficiency of 88.4% at a switching frequency of 477 MHz is demonstrated for a voltage conversion from 1.2-0.9 volts while supplying 9.5 A average current. The area occupied by the buck converter is 12.6 mm/sup 2/ assuming an 80-nm CMOS technology. An estimate of the efficiency is shown to be within 2.4% of simulation at the target design point. Full integration of a high-efficiency buck converter on the same die with a dual-V/sub DD/ microprocessor is demonstrated to be feasible.     

Voltage and current stress reduction in single-stage power factorcorrection AC/DC converters with bulk capacitor voltage feedback

Single-stage power factor correction (PFC) AC/DC converters integrate a boost-derived input current shaper (ICS) with a flyback or forward DC/DC converter in one single stage. The ICS can be operated in either discontinuous current mode (DCM) or continuous current mode (CCM), while the flyback or forward DC/DC converter is operated in CCM. Almost all single-stage PFC AC/DC converters suffer from high bulk capacitor voltage stress and extra switch current stress. The bulk capacitor voltage feedback with a coupled winding structure is widely used to reduce both the voltage and current stresses in practical single-stage PFC AC/DC converters. This paper presents a detailed analysis of the bulk capacitor voltage feedback, including the relationship between bulk capacitor voltage, input current harmonics, voltage feedback ratio, and load condition. The maximum bulk capacitor voltage appears when the DC/DC converter operates at the boundary between CCM and DCM. This paper also reveals that only the voltage feedback ratio determines the input current harmonics under DCM ICS and CCM DC/DC operation. The theoretical prediction of the bulk capacitor voltage as well as the predicted input harmonic contents is verified experimentally on a 60 W AC/DC converter with universal-line input