Proposal of dual-powered superconducting logic circuits

A novel structure of high-speed Josephson logic circuits is proposed. Josephson logic gates have latching characteristics and can hold data as long as bias currents are supplied. Through effective use of these latching characteristics, logic circuits can be constructed with wide operating margins. Dual power supplies, properly phased, separately drive logic circuits divided into two groups. Logic signals are transferred from one logic group to the other or vice versa, and one group is reset into a zero voltage state when the other group is active for logic operation. For combinational circuits, the basic configuration of an astable flip-flop and a delay circuit are presented to prevent the logic circuit from `racing'. As an example of sequential circuits, a bistable flip-flop to store data is constructed without any superconducting loop.     

All-optical flip-flop multimode interference bistable laser diode

All-optical flip-flop operation of multimode interference bistable laser diodes (MMI-BLDs) was experimentally demonstrated for the first time. The MMI-BLD was prepared with a conventional ridge waveguide laser diode fabrication procedure, suitable for photonic integrated circuits. Bistable switching via two-mode bistability was obtained with approximately 0-dBm input powers due to cross-gain saturation and the saturable absorbers. Bit-length conversion was successfully obtained with noninverted and inverted outputs. This device will be useful in future photonic systems requiring all-optical latching functions such as optical memory, self-routing, and further optical signal processing.     

Parallel operation of a 32*16 symmetric self-electrooptic effect device array

Free-space optics for digital optical computing or for electrooptic interconnections is considered. Results of an experiment are presented in which 512 symmetric self-electrooptic effect devices (S-SEEDs) were simultaneously operated. In this experiment, simultaneous continuous bistable operation was shown for the 32*16 array of S-SEEDs, as well as simultaneously optical latching of optical data in a random access manner onto the array.<>     

Concise transient SPICE model for bipolar power transistor quasi-saturation simulation

A concise transient SPICE model is presented in this paper to predict both the static and the switching behaviour of power transistors, with emphasis placed on quasi-saturation effects. The model is proposed to simulate both ohmic and non-ohmic quasi-saturation phenomena by automatically adjusting the hole injection ratio term. The model incorporates the currently used Gummel-Poon (GP) model and an additional charge-control relation for the transistor's epitaxial collector. The turn-off charge removal phenomenon is not modelled specifically; however, the charge-control equation for the epitaxial collector region may partly simulate this effect where the quasi-saturation region is entered. The validity of the model is verified by comparison between the original SPICE bipolar junction transistor model and experimental data for both DC and turn-on conditions. Methods for determining the model parameters are described.     

High-speed demonstration of an output interface driver forsingle-flux quantum systems

The high-speed operation of a one-channel output interface for a single-flux quantum (SFQ) system has been demonstrated. The interface consisted of a Josephson latching driver, a room-temperature semiconductor amplifier, and a decision circuit module. The Josephson latching driver was fabricated by using a 2.5-kA/cm² standard Nb junction process and used to amplify an SFQ pulse into a 5.5-mV level signal at 10 Gb/s. The interface converted the SFQ pulse signal into a nonreturn-to-zero signal having an amplitude of 1 V at 10 Gb/s     

Design consideration and performance of a new MOS imaging device

The design considerations and performance of a new MOS imaging device with novel random noise suppression (RANS) circuits are described. This device consists of 492 × 388 photodiodes, a vertical shift register, and a horizontal BCD register integrated in p-wells. The RANS circuits accelerate the charge-transfer speed from vertical signal lines to a horizontal BCD register with 98-percent efficiency. They also decrease the effective signal line capacitance, so noise due to the transfer MOS switches is suppressed to obtain a high signal-to-noise ratio of 46 dB at a standard scene illumination of 180 lx (F1.4) with no image lag and blooming. Sweep out operation for the smear charge accumulated in the vertical signal lines realizes a sufficient signal-to-smear ratio of 69 dB at 1/10 vertical scene illumination.     

一种适用于锁式铁氧体器件的驱动电路

分析了锁式铁氧体器件的等效负载特性,在此基础上给出了专用驱动电路的设计,并分析了其原理以及应用结果。从中可以看出,该电路能用于驱动所有锁式铁氧体器件,特别适用于驱动锁式铁氧体移相器。     

Characteristics of bistable CW GaAs junction lasers operating above the delay-transition temperature

The conditions for bistable operation of CW GaAs junction lasers are developed in terms of the previously published double-acceptor trap theory. The experimental CW operation of such devices is shown to agree well with the theoretical results. In addition the fabrication of these bistable lasers is described and several pulsed experiments are reported that indicate a significant increase in the number of trapping centers in the vicinity of the junction.     

Very-high-speed Si bipolar static frequency dividers with newT-type flip-flops

This paper presents two circuit techniques for highspeed operation of a master-slave toggle flip-flop circuit (MSTFF). One circuit reduces the gain in latching circuits, and the other uses the transient current of the emitter followers to boost the switching speed. Both the SPICE simulations and the measured results for static 1/8 frequency dividers fabricated using 0.5-μm super self-aligned process technology (SSTIC) show that the maximum operating speed of our MS-TFF's is 10% and 30% faster than that of conventional ones. By applying these technologies, 19.1-GHz and 22.4-GHz Si bipolar static frequency dividers have been fabricated     

A new large signal HBT model

Several effects important for large signal operations of heterojunction bipolar transistor (HBTs) were not included in the previous HBT models used in most commercial circuit simulators. Exclusion of these effects resulted in large discrepancies between modeled and measured device characteristics. This paper presents a new large signal HBT model which takes into account those important effects for the device operation. The effects have been identified from measured device characteristics and can be justified from first principles. To make it easy to use, the model is made up of the elements available from SPICE. During the course of the model development, an extraction procedure for the model parameters has been established to minimize the uncertainty of the extracted parameter values. The new model has been applied to HBTs with various emitter sizes and excellent agreement has been achieved between modeled and measured data over a wide range of bias conditions and signal frequencies     

NAND Flash存储的坏块管理方法

针对NAND Flash海量存储时对数据可靠性的要求,提出了一种基于在FPGA内部建立RAM存储有效块地址的坏块管理方法。在海量数据存储系统中,通过调用检测有效块地址函数确定下一个有效块地址并存入建好的寄存器中,对NANDFlash进行操作时,不断更新和读取寄存器的内容,这样就可以实现坏块的管理。实验证明,本方法可以大大减小所需寄存器的大小并节省了FPGA资源,经过对坏块的管理,可以使数据存储的可靠性有很大的提升。     

Bistable operation of two semiconductor lasers in an external cavity: Rate-equation analysis

The steady-state and dynamic behavior of a bistable laser resonator containing two semiconductor elements is examined theoretically. We derive necessary conditions for the bistable operation of the cavity and the constraints on the amplifier and absorber element characteristics imposed by these conditions. Our rate equation model demonstrates turn-on and turn-off of the output via current pulses, overshoot and ringing using fast rise time pulses, and critical slowing down when either the absorber or amplifier is switched. We give numerical results on switching.     

Circuit modeling of multimode bistable laser diodes

A circuit model for multimode bistable laser diodes (BLD) has been developed from the rate equations. The model is simulated for dc sweep and transient conditions using circuit simulation program PSPICE. The hysteresis behaviour and the dynamic properties of the longitudinal modes of the BLD are studied. The dc sweep simulation shows “S”-shaped bistability for the fundamental mode, whereas the sidemodes exhibit a “loop”-like bistability. The transient simulation also shows similar behaviour     

Pass transistor with dual threshold voltage domino logic design using standby switch for reduced subthreshold leakage current

Dual threshold voltages domino design methodology utilizes low threshold voltages for all transistors that can switch during the evaluate mode and utilizes high threshold voltages for all transistors that can switch during the precharge modes. We employed standby switch can strongly turn off all of the high threshold voltage transistors which enhances the effectiveness of a dual threshold voltage CMOS technology to reduce the subthreshold leakage current. Subthreshold leakage currents are especially important in burst mode type integrated circuits where the majority of the time for system is in an idle mode. The standby switch allowed a domino system enters and leaves a low leakage standby mode within a single clock cycle. In addition, we combined domino dynamic circuits style with pass transistor XNOR and CMOS NAND gates to realize logic 1 output during its precharge phase, but not affects circuits operation in its evaluation and standby phase. The first stage NAND gates output logic 1 can guarantee the second stage computation its correct logic function when system is in a cascaded operation mode. The processing required for dual threshold voltage circuit configuration is to provide an extra threshold voltage involves only an additional implant processing step, but performs lower dynamic power consumption, lower delay and high fan-out, high switching frequencies circuits characteristics. SPICE simulation for our proposed circuits were made using a 0.18 µm CMOS process from TSMC, with 10 fF capacitive loads in all output nodes, using the parameters for typical process corner at 25 °C, the simulation results demonstrated that our designed 8-bit carry look-ahead adders reduced chip area, power consumption and propagation delay time more than 40%, 45% and around 20%, respectively. Wafer based our design were fabricated and measured, the measured data were listed and compared with simulation data and prior works. SPICE simulation also manifested lower sensitivity of our design to power supply, temperature, capacitive load and process variations than the dynamic CMOS technologies.     

A 1920(H)×1035(V) pixel high-definition CCD image sensor

A 1920(H)×1035(V)-pixel high-definition CCD (charge-coupled-device) image sensor compatible with an 1125-scanning-lines and 16:9 aspect-ratio television system is described. The device basically uses an interline scheme with a vertical overflow drain. To maintain 74.25-MHz ultrahigh-data-rate operation, the device adopts a dual-channel configuration for the horizontal CCD (H-CCD) register. To accomplish both vertical signal charge transfer in the vertical CCD (V-CCD) register and signal charge distribution from the V-CCD registers into the dual-channel horizontal CCD registers simultaneously within a 3.77-μs short horizontal blanking period, a one-horizontal-period signal storage memory electrode and optical black memory are introduced. Bipolar buffer transistor chips are hybridized in the same package as the device, so as to reduce parasitic capacitance at CCD output terminals and maintain a wide-bandwidth operation. The device operates successfully and 1000-TV-line limiting resolution was obtained for both vertical and horizontal directions. Total random noise was evaluated to be 41 electrons. Dynamic range reached 66 dB. Signal-to-noise ratio for a black/white (B/W) camera was 51.5 dB under F4.0 and 2000-lux illumination conditions     

NAND FLASH芯片K9F5608在MP3电子导游机中的应用

介绍了三星公司的K9F5608闪存的组织结构、I/O口线的特点、专用的命令指令和状态寄存器。给出了该Flash芯片在MP3电子导游机中的应用方法 ,同时给出了NANDFLASH与MSP430单片机的硬件连接和读写FLASH的程序实现流程。     

基于FPGA的NAND控制器设计与实现

在基于NAND型固态存储系统的开发中,接口芯片直接影响储存系统的性能,为了最大限度地提高读写性能,需对NAND控制器进行自主设计。通过分析NAND Flash的接口特性和NAND控制器的组成结构,采用了状态机对NAND控制器的主逻辑以及常用编程命令进行了描述,同时运用FPGA对该状态机逻辑进行实现,并对NAND主要操作命令进行了仿真试验。试验结果表明,该设计符合NAND Flash的操作时序要求。     

Enhanced architectures for soft error detection and correction in combinational and sequential circuits

In this paper two new methods for the design of fault-tolerant pipelined sequential and combinational circuits, called Error Detection and Partial Error Correction (EDPEC) and Full Error Detection and Correction (FEDC), are described. The proposed methods are based on an Error Detection Logic (EDC) in the combinational circuit part combined with fault tolerant memory elements implemented using fault tolerant master–slave flip-flops. If a transient error, due to a transient fault in the combinational circuit part is detected by the EDC, the error signal controls the latching stage of the flip-flops such that the previous correct state of the register stage is retained until the transient error disappears. The system can continue to work in its previous correct state and no additional recovery procedure (with typically reduced clock frequency) is necessary. The target applications are dataflow processing blocks, for which software-based recovery methods cannot be easily applied. The presented architectures address both single events as well as timing faults of arbitrarily long duration. An example of this architecture is developed and described, based on the carry look-ahead adder. The timing conditions are carefully investigated and simulated up to the layout level. The enhancement of the baseline architecture is demonstrated with respect to the achieved fault tolerance for the single event and timing faults. It is observed that the number of uncorrected single events is reduced by the EDPEC architecture by 2.36 times compared with previous solution. The FEDC architecture further reduces the number of uncorrected events to zero and outperforms the Triple Modular Redundancy (TMR) with respect to correction of timing faults. The power overhead of both new architectures is about 26–28% lower than the TMR.     

SPICE source code implementation of aDC model for the non pinchoff depletion mode MOSFET

The implementation of the Lin model for the non pinchoff depletion mode MOSFETs directly into the source code of the SPICE 2G.5 circuit simulation program is described. The computational advantages of our implementation over Lin's subcircuit approach are pointed out, and, more significantly, certain previously undiscovered limitations of both methods are discussed. The encoding of the model into SPICE is described in sufficient detail so as to be duplicable by other interested researchers. Our results compare favorably to experiment and to the more comprehensive El-Mansy model. Finally, a new method of parameter extraction is described for the El-Mansy model, which makes it possible to derive the parameters of the Lin and El-Mansy models simultaneously.