A simple,direct and reliable extraction method applied to GaN devices

In this article, a simple, direct and reliable extraction method has been developed and applied to different sizes of Gallium Nitride (GaN) high electron mobility transistors (HEMTs). Instead of high-voltage gate-forward measurements with risk of device damage, the proposed approach uses only uncritical cold S-parameters at pinch-off (V_GS < V_p, V_DS = 0 V) and in the off-state (V_GS = 0 V, V_DS = 0 V). The extraction procedure is validated by small- and large-signal measurements. Very good agreement is obtained. Scaling of parasitic elements with the device size is confirmed.     

Highly Stretchable,High‐Mobility,Free‐Standing All‐Organic Transistors Modulated by Solid‐State Elastomer Electrolytes

Highly stretchable, high‐mobility, and free‐standing coplanar‐type all‐organic transistors based on deformable solid‐state elastomer electrolytes are demonstrated using ionic thermoplastic polyurethane (i‐TPU), thereby showing high reliability under mechanical stimuli as well as low‐voltage operation. Unlike conventional ionic dielectrics, the i‐TPU electrolyte prepared herein has remarkable characteristics, i.e., a large specific capacitance of 5.5 µF cm^?2, despite the low weight ratio (20 wt%) of the ionic liquid, high transparency, and even stretchability. These i‐TPU‐based organic transistors exhibit a mobility as high as 7.9 cm² V^?1 s^?1, high bendability (R_c, radius of curvature: 7.2 mm), and good stretchability (60% tensile strain). Moreover, they are suitable for low‐voltage operation (V_DS = ?1.0 V, V_GS = ?2.5 V). In addition, the electrical characteristics such as mobility, on‐current, and threshold voltage are maintained even in the concave and convex bending state (bending tensile strain of ≈3.4%), respectively. Finally, free‐standing, fully stretchable, and semi‐transparent coplanar‐type all‐organic transistors can be fabricated by introducing a poly(3,4‐ethylenedioxythiophene):polystyrene sulfonic acid layer as source/drain and gate electrodes, thus achieving low‐voltage operation (V_DS = ?1.5 V, V_GS = ?2.5 V) and an even higher mobility of up to 17.8 cm² V^?1 s^?1. Moreover, these devices withstand stretching up to 80% tensile strain.     

Bias stress effect in solution-processed organic thin-film transistors: Evidence of field-induced emission from interfacial ions

Though bias-stress instability in organic thin film transistors (OTFTs) has been studied in a variety of architectures, it is as yet poorly understood. We have investigated the bias-stress effect in fully solution-processed TIPS-pentacene based OTFTs with polymer dielectric by applying prolonged gate-source voltage (V_GS). The interface is deliberately defect engineered to obtain excellent adhesion and reasonably good steady state characteristics. Both increasing and decreasing behavior of drain-source current (I_DS) drift over 3000s have been observed, and analyzed in terms of electron capture and emission respectively. The step-by-step change in V_GS is compared with the one step change from V_GS = 0V to V_GS = −40V. It has been observed that, for the case of step-wise increase in gate bias, the I_DS transients are slower by many orders of magnitude than if the V_GS is directly switched to deep bias (−40V) in a single step. A phenomenological model is used to explain the I_DS decaying transients. The field induced emission of carriers from interfacial traps is shown to be central to the model and experimental features. The effect due to a prolonged application of drain-source voltage (V_DS) is small, though noticeable in terms of increasing the I_DS only by 3% with continuous application of V_DS for 3000 s.     

Low and high temperature device reliability investigations of buried p-channel MOSFETs of a 0.17 μm technology

The hot carrier degradation of buried p-channel MOSFETs of a 0.17 μm technology is assessed in the temperature range between −40°C and 125°C. Within this temperature range, the degradation of the electrical parameter is investigated for different drain voltages and channel lengths (0.2–0.3 μm) in the gate voltage range between V_GS=0 V and V_GS=V_DS. The analysis of the experimental results is presented and the physical processes responsible for the observed degradation at different stress conditions are discussed by reviewing previous works. Based on hot carrier modelling and lifetime extrapolation to operating conditions the stressing voltage conditions are analysed. For the experimentally investigated temperature range the worst case stress condition is identified at low temperatures for gate voltage at the maximum of the gate current (I_Gmax). In the case of V_GS corresponding to I_Gmax two activation energies are determined for low and high temperatures. For temperatures above 125°C the worst case bias condition changes from V_GS=V_GS@I_Gmax to V_GS=V_DS.     

Low frequency noise in gate and drain of PHEMT’s and related correlation

Low frequency noise investigations have been carried out in GaAs based psuedomorphic high electron mobility in order to model the up-converted noise in nonlinear applications of these devices. Gate and channel noises are studied versus frequency and versus device biases. The results are analysed with an equivalent circuit issued from conduction investigations. Correlation between input and output noises is also measured. For V_GS<0 V, the main origin of the coherence is located between gate and drain, whereas for V_DS>0 V, the access source resistance must be taken into account.     

Comparative studies of Pt and Ir schottky contacts on undoped Al0.36Ga0.64N

Schottky contacts of Pt and Ir on undoped Al_0.36Ga_0.64N have been fabricated and the ideality factor, the built-in voltage and the reverse bias current were determined using current–voltage measurements to make a comparison.The smallest ideality factors, the lowest reverse bias current and the highest built-in voltages have been obtained for Ir Schottky contacts.We have studied the effect of an annealing for Pt and Ir Schottky contacts, on the ideality factor, the built-in voltage and the reverse bias current. A decrease of the ideality factor and the reverse bias current associated to an increase of the built-in voltage have been obtained except for high annealing temperature (T > 400 °C).Reductions of 37% and 43% of the ideality factor and improvements of 24% and 41% of the built-in voltage have been obtained for Pt and Ir Schottky contacts, respectively, after an annealing performed at 350 °C during 30 min.Two different electrical stresses have also been applied on the ohmic and Schottky contacts during 164 h to study the reliability of the employed technology. In a first time, the devices have been stressed with a drain-to-source voltage V_DS of 20 V and a gate-to-source voltage V_GS of −5 V to submit the devices to an electrical field only and not to a thermal effect induced by the electrical current. In a second time, the aging stress has been applied for a V_DS of 20 V and for a V_GS of 0 V in order to study the impact of the electrical field and the thermal effect induced by the drain current on the electrical behaviours of Al_0.36Ga_0.64N/GaN transistors. This study has also shown the existence of electrical traps in the device structure and proved the good reliability of the involved technology.These comparative studies demonstrate that Ir is a better candidate than Pt for the realisation of Schottky contacts on undoped Al_0.36Ga_0.64N.     

A study on the leakage current of poly-Si TFTs fabricated by metal induced lateral crystallization

Leakage current of poly-Si TFT fabricated by a metal induced lateral crystallization(MILC) process was investigated in terms of metal contamination and crystallization mechanisms. MILC poly-Si TFTs showed a higher leakage current than those by the solid phase crystallization method at high drain voltages. It turned out that the Ni rich phases in the depleted junction region played the role of trapping and recombination centers to generate the leakage currents and that the leakage current was generated by thermionic field emission. The leakage current could be drastically reduced to 5 pA/μm at V_GS=0 V and V_DS=15 V after the exclusion of the Ni-rich phase from the junction region by a Ni offset MILC process.     

SiC JBS二极管和SiC MOSFET的空间辐照效应及机理

基于第六代650 V 碳化硅结型肖特基二极管(SiC JBS Diode)和第三代900 V 碳化硅场效应晶体管(SiC MOSFET),开展SiC功率器件的单粒子效应、总剂量效应和位移损伤效应研究。20~80 MeV质子单粒子效应实验中,SiC功率器件发生单粒子烧毁(SEB)时伴随着波浪形脉冲电流的产生,辐照后SEB器件的击穿特性完全丧失。SiC功率器件发生SEB时的累积质子注量随偏置电压的增大而减小。利用计算机辅助设计工具(TCAD)开展SiC MOSFET的单粒子效应仿真,结果表明,重离子从源极入射器件时,具有更短的SEB发生时间和更低的SEB阈值电压。栅-源拐角和衬底-外延层交界处为SiC MOSFET的SEB敏感区域,强电场强度和高电流密度的同时存在导致敏感区域产生过高的晶格温度。SiC MOSFET在栅压偏置(U_GS=3 V,U_DS=0 V)下开展钴源总剂量效应实验,相比于漏压偏置(U_GS=0 V,U_DS=300 V)和零压偏置(U_GS=U_DS=0 V),出现更严重的电学性能退化。利用中带电压法分析发现,栅极偏置下氧化层内的垂直电场提升了陷阱电荷的生成率,加剧了阈值电压的退化。中子位移损伤会导致SiC JBS二极管的正向电流和反向电流减小。在漏极偏置下进行中子位移损伤效应实验,SiC MOSFET的电学性能退化最严重。该研究为空间用SiC器件的辐射效应机理及抗辐射加固研究提供了一定的参考和支撑。     

Enhanced characteristics in gate-recessed and sidewall-recessed AlGaAs/InGaAs PHEMTs by citric-based selective wet etching

Improved device performance in Al_0.2Ga_0.8As/In_0.15Ga_0.85As gate-recessed enhancement-mode pseudomorphic high electron mobility transistors (E-PHEMTs) and sidewall-recessed depletion-mode PHEMTs (D-PHEMTs) using a newly developed citric buffer etchant are reported. The innovated etchant near room temperature (23°C) possesses a high GaAs/Al_0.2Ga_0.8As or In_0.15Ga_0.85As/Al_0.2Ga_0.8As etching selectivity (>250) applied to an etched stop surface. For E-PHEMTs, the transconductance (G_m) of 315?mS/mm and high linearity of 0.46?V-wide gate voltage swing (drop of 10% peak G_m), corresponding to 143?mA/mm-wide I_DS, even at a gate length of 1?µm is obtained. For microwave operation, this 1?µm-gate E-PHEMT shows the f_max (maximum operation frequency) of 29.2?GHz and the f_T (cut-off frequency) of 11.2?GHz, respectively. The measured minimum noise figure (NF_min), under V_DS?=?3?V and I_DS?=?7.5?mA, is 0.56?dB at 1?GHz with the associated gain of 10.86?dB. The NF_min is less than 1.5?dB in the frequency range from 1 to 4?GHz. In addition, an effective and simple method of selective gate sidewall recess is utilized to etch the low barrier in In_0.15Ga_0.85As channel at mesa sidewalls for D-PHEMTs. For D-PHEMTs with 1?×?100?µm² exhibit a very low gate leakage current of 2.4?μA/mm even at V_GD?=??10?V and high gate breakdown voltage over 25?V. As compared to that of no sidewall recess, nearly two orders of reduction in magnitude of gate leakage current and 100% improvement in gate breakdown voltage are achieved.     

Control of threshold voltage and improved subthreshold swing in enhancement-mode InGaP/InGaAs metal-oxide-semiconductor pseudomorphic high-electron-mobility transistor

The InGaP/InGaAs metal-oxide-semiconductor pseudomorphic high-electron-mobility transistor (MOS-PHEMT) with an oxidized GaAs gate by liquid phase oxidation (LPO) is demonstrated. With the help of the LPO, the threshold voltage (V_th) can be shifted positively to 0.07 V, and enhancement-mode MOS-PHEMT is fabricated. The device with a gate metal of 1 × 100 μm² shows a maximum transconductance of 171 mS/mm at V_DS = 5 V and a maximum drain current density of 182 mA/mm at V_GS = 2 V. It also exhibits a lower leakage current and an improved subthreshold swing compared to the referenced Schottky-gate InGaP/InGaAs PHEMT.     

High-temperature and self-heating effects in fully depleted SOI MOSFETs

In this paper, the high-temperature and self-heating effects in the fully depleted enhancement lightly doped SOI n-MOSFETs are investigated over a wide range of temperatures from 300 to 600 °K by using the SILVACO¹ TCAD tools. In particular, we have studied their current-voltage characteristics (I_D-V_GS and I_D-V_DS), threshold voltages and propagation delays. Simulation results show that there exists a biasing point where the drain current and the transconductance are temperature independent. Such a point is known as the zero temperature coefficient (ZTC) bias point. The drain current ZTC bias points are identified in both the linear and saturation regions whereas the transconductance ZTC bias point exists only in the saturation region. We have observed that decreasing the film thickness could reduce the threshold voltage sensitivity of the SOI MOSFET with temperature and that the drain current decreases with increasing temperature. We have also noted that due to the self-heating effects, the drain current decreases with increasing drain bias exhibiting a negative conductance and that the self-heating effects reduced at a higher operating temperature. Self-heating effects are more pronounced for higher gate biases and thinner silicon films whereas the bulk device shows negligible self-heating effects.     

Comparison of modulation doped effect in negative differential resistance field effect transistors (NDRFETs)

N-shaped negative differential resistance field effect transistors (NDRFETs) have been fabricated and demonstrated. The interesting N-shaped NDRs are three terminal controlled phenomena. This N-shaped NDR behavior is found in the higher drain-to-source voltage (V_DS) regime and is obtained both at positive and negative gate-to-source bias (V_GS). We believe that the NDR phenomena are attributed to the real space transfer (RST) effect. Due to the modulation doped effect and different barrier height, the NDR behavior can easily be controlled. The influence of V_GS bias on the NDR characteristics is also investigated.     

On-state and off-state stress-induced degradation in unhydrogenated solid phase crystallized polysilicon thin film transistors

The effects of DC bias gate and drain on-state and off-state stresses on unhydrogenated solid phase crystallized polysilicon thin film transistors were investigated. The observed, under gate bias stress, threshold voltage turnaround from an initial negative shift due to hole trapping to positive shift with logarithmic time dependence attributed to electron trapping was suppressed when a drain bias was added for a combined gate–drain on-state stress; this suppression was more effective for larger gate bias. The subthreshold swing, the midgap trap state density and the transconductance exhibited logarithmic degradation, in line with the positive V_th shift. The stressing time needed for V_th turnaround decreased, indicating increase of electron trapping, and the midgap trap state density increased in correlation with increasing stressing current I_DS as stressing V_DS increased, for a given on-state stressing V_GS. Off-state gate–drain stressing resulted in logarithmic positive V_th shift, after a small initial negative shift, and in reduction of the leakage current due to stress-induced shielding of the gate field. An applied inverse stress resulted in less severe V_th degradation due to stress-induced effects being more concentrated near the source rather than the drain in that case.     

A flip-chip packaged 80-nm In0.7Ga0.3As MHEMT for millimeter-wave low-noise applications

In this paper, we present a flip-chip 80-nm In_0.7Ga_0.3As MHEMT device on an alumina (Al₂O₃) substrate with very little decay on device RF performance up to 60 GHz. After package, the device exhibited high I_DS = 435 mA/mm at V_DS = 1.5 V, high g_m = 930 mS/mm at V_DS = 1.3 V, the measured gain was 7.5 dB and the minimum noise figure (NF_min) was 2.5 dB at 60 GHz. As compared to the bare chip, the packaged device exhibited very small degradation in performance. The result shows that with proper design of the matching circuits and packaging materials, the flip-chip technology can be used for discrete low noise FET package up to millimeter-wave range.     

Field and hot electron-induced degradation in GaN-based power MIS-HEMTs

We investigate the degradation of AlGaN/GaN MIS-HEMTs submitted to gate step-stress experiments, and demonstrate the existence of field- and hot-electron induced processes. When the devices are submitted to gate-step stress with high V_DS > 50 V, four different regimes are identified: (i) for V_GS < − 10 V, no significant degradation is observed, since the devices are in the off-state; (ii) for − 10 V < V_GS < 0 V, hot electrons flow through the channel, as demonstrated by the (measurable) electroluminescence signal. These hot electrons can be trapped within device structure, inducing an increase in the threshold voltage. (iii) for V_GS > 0 V, the density of hot electrons is significantly reduced, due to the increased interface scattering and device temperature. As a consequence, EL signal drops to zero, and the electrons trapped during phase (ii) are de-trapped back to the channel, where they are attracted by the high 2DEG potential. (iv) Finally, for V_GS > 5 V, a significant increase in threshold voltage is detected. This effect is observed only for high positive voltages, i.e. when a significant leakage current flows through the gate. Such gradual degradation is ascribed to the injection of electrons from the 2DEG to the gate insulator, which is a field-driven effect. These results were obtained by combined electrical and optical characterization carried out at different voltages during the step stress.     

Underlap channel metal source/drain SOI MOSFET for thermally efficient low-power mixed-signal circuits

In this paper it has been shown that employing an underlap channel created by varying the lateral doping straggle in dopant-segregated Schottky barrier SOI MOSFET not only improves the scalability but also suppresses the self-heating effect of this device. Although in strong inversion region the reduced effective gate voltage due to voltage drop across the underlap lengths reduces the drive current, in weak/moderate inversion region defined at I_D=5 μA/μm and V_DS=0.5 V the analog figures of merit such as transconductance, transconductance generation factor and intrinsic gain of the proposed underlap device are improved by 15%, 35% and 20%, respectively over the conventional overlap channel structure. In addition to this, at V_DD=0.5 V the gain-bandwidth product in a common-source amplifier based on proposed underlap device is improved by ～20% over an amplifier based on the conventional overlap channel device. The mixed-mode device/circuit simulation results of CMOS inverter, NAND and the NOR gates based on these devices also show that at V_DD=0.5 V the switching energy, static power dissipation and the propagation delay in the case of proposed underlap device are reduced by ～10%, ～35% and ～25%, respectively, over the conventional overlap device. Thus, significant improvement in analog figures of merit and the reduction in digital design metrics at lower supply voltage show the suitability of the proposed underlap device for low-power mixed-signal circuits.     

Current saturation effect for pentacene-based static induction transistor under negative drain-source and gate voltages

Usually, the drain-source current (I_DS) increases with positive drain-source voltage (V_DS) for pentacene-based organic static induction transistor (OSIT) ITO(Source)/Pentacene/Al(Gate)/Pentacene/Au(Drain) and it shows an inherent rectifying property under negative gate voltages (V_G), i.e. the slope of I_DS vs. V_DS curve increases with V_DS but without any current saturation effect. In this paper, we investigated the electrical characteristics of pentacene-based OSIT ITO/Pentacene(80 nm)/Al(15 nm)/Pentacene(80 nm)/Au under negative V_DS and V_G, and found that I_DS changed from rectifying property to saturation effect when the magnitude of negative V_DS was increased from 0 V to −6 V under negative V_G, and the turn-on voltage (V_ON) moved to larger negative voltages when the magnitude of negative V_G increased and the movement step of V_ON gets smaller after keeping the device for a long time, and the possible mechanisms for such a kind of current modulation were discussed.     

A Novel Body-tied Silicon-On-Insulator(SOI) n-channel Metal-Oxide-Semiconductor Field-Effect Transistor with Grounded Body Electrode

A novel body-tied silicon-on-insulator(SOI) n-channel metal-oxide-semiconductor field-effect transistor with grounded body electrode named GBSOI nMOSFET has been developed by wafer bonding and etch-back technology. It has no floating body effect such as kink phenomena on the drain current curves, single-transistor latch and drain current overshoot inherent in a normal SOI device with floating body. We have characterized the interface trap density, kink phenomena on the drain current (I_DS-V_DS) curves, substrate resistance effect on the I_DS-V_DS curves, subthreshold current characteristics and single transistor latch of these transistors. We have confirmed that the GBSOI structure is suitable for high-speed and low-voltage VLSI circuits.     

Indirect fitting procedure to separate the effects of mobility degradation and source-and-drain resistance in MOSFET parameter extraction

A new procedure is presented to separate the effects of source-and-drain series resistance and mobility degradation factor in the extraction of MOSFET model parameters. It requires only a single test device and it is based on fitting the I_D(V_GS, V_DS) equation to the measured characteristics. Two types of bidimensional fitting are explored: direct fitting to the drain current and indirect fitting to the measured source-to-drain resistance. The indirect fitting is shown to be advantageous in terms of fewer number of iterations needed and wider extent of initial guess values range.     

HCS degradation of 5 nm oxide high-voltage PLDMOS

Hot carrier (HC) injection, inducing drain and gate leakage current increase in 5 nm oxide p-channel LDMOS transistors, is investigated. Devices with two different drain implants are studied. At low gate voltage (V_GS) and high drain voltage (V_DS), reduction of the ON-resistance (R_ON) is observed. At stress times at which R_ON almost reaches its constant level, an increase of the drain leakage in OFF state (V_DS = −60 V, V_GS = 0 V) is observed. Longer stress time leads to increased gate leakage and in some cases oxide breakdown. In contrast to what was reported for devices with 25 nm gate oxide thickness, the threshold voltage of 5 nm gate oxide PLDMOS transistors does not drift. The experimental data can be fully explained by hot carrier injection and the oxide damage can be explained by two different and competing degradation mechanisms. By combining experimental data and TCAD simulations we are further capable to locate the hot spot of maximum oxide damage in the accumulation (Acc) region of the PLDMOS.