Design and Evaluation of Adiabatic Arithmetic Units

Adiabatic design is an attractive approach to reducingenergy consumption in VLSI circuits after exhausting the potentialof conventional energy-saving techniques. Despite the plethoraof adiabatic logic architectures that have been proposed in recentyears, several practical considerations in the design of nontrivialadiabatic circuits remain largely unexplored. Moreover, it isstill unclear whether adiabatic circuits of significant sizeand complexity can achieve substantial savings in energy dissipationover corresponding conventional designs. We recently designedseveral low-power arithmetic units using a dual-rail adiabaticlogic design style. We also designed static CMOS versions ofthese units and compared their energy dissipation with theircorresponding adiabatic designs. In this paper we describe ourimplementations, discuss architecture and logic-level issuesrelated to our adiabatic designs, and present the findings ofour empirical comparison. Our results suggest that adiabaticlogic can be used for the implementation of relatively complexVLSI circuits that dissipate significantly less energy than theircorresponding CMOS designs.     

Turning silicon on its edge [double gate CMOS/FinFET technology]

Double-gate devices will enable the continuation of CMOS scaling after conventional scaling has stalled. DGCMOS/FinFET technology offers a tactical solution to the gate dielectric barrier and a strategic path for silicon scaling to the point where only atomic fluctuations halt further progress. The conventional nature of the processes required to fabricate these structures has enabled rapid experimental progress in just a few years. Fully integrated CMOS circuits have been demonstrated in a 180 nm foundry-compatible process, and methods for mapping conventional, planar CMOS product designs to FinFET have been developed. For both low-power and high-performance applications, DGCMOS-FinFET offers a most promising direction for continued progress in VLSI.     

Semistate theory and analog VLSI design

Semistate theory as applied to electronic circuits is reviewed in a tutorial fashion. The resulting theory is applied to the design of linear VLSI circuits using an admittance framework for which the main components are MOS capacitors, differential pairs and current mirrors. The results are extended to nonlinear designs through the use of CMOS multipliers.     

Physical design of testable VLSI: techniques and experiments

It is shown that the layout of VLSI circuits can affect testability and in some cases reduce the number of faults likely in a design, easing test generation. A method for analyzing circuits at the symbolic layout level and enhancing testability using local transformations is presented. To demonstrate the application of the technique a set of CMOS standard cells was redesigned. The standard cells are used in the MIS synthesis system, allowing the designer to modify interactively designs to perform tradeoff analysis on testable designs. To show the usefulness of the technique, an experiment was performed: example circuits were synthesized, and test vectors were generated and then used in a transistor-level fault simulator. It was found that the modified designs have significantly higher fault coverage than unmodified designs. A strategy for the synthesis of easily testable combinational random logic circuits is presented     

Fault model for sub-micron CMOS ULSI circuits reliability assessment

A new fault model, based on the general Percolation theory applied to long-channel CMOS VLSI circuits, has been recently introduced. It was shown that a reliability risk appears only when process-related defects create a pattern independent current path in standby mode. An acceptable reliability risk defines pass/fail criteria. A screening technique, based on this model, presents a strong correlation between rejected devices and Early Failure Rate.In this paper, the general Percolation approach was applied to short-channel CMOS VLSI circuits. Unlike long-channel CMOS VLSI, defect-free short-channel CMOS VLSI circuits inherently have a pattern-independent standby current. It results from a short-channel MOSFET current in the off state. In this case, the defect-related component of this current might be released only by means of a multi parameter fail criterion. Experimental results that confirm this conclusion are presented and discussed. The Reliability Risk assessment technique employing this model shows a strong correlation between rejected devices and long term reliability for 32-bit 0.35 μM CMOS microprocessors.     

一种基于符号逻辑的神经元模型和电路实现

为了实现基于符号逻辑的神经网络系统,本文定义了一种逻辑神经元模型,并采用了电流型CMOS工艺实现这种神经元电路的各种逻辑功能,最后通过电路模拟,证明设计的正确性。     

Layout reconstruction of complex silicon chips

A semiautomated, fast-turnaround and high-reliability procedure for the layout reconstruction of complex VLSI circuits is presented together with details of the equipment and processes employed. The techniques have been verified using both simple CMOS gate array chips and complex VLSI microprocessor circuits and may be applied, in principle, to arbitrarily large or complex devices     

Thermal Modeling, Analysis, and Management in VLSI Circuits: Principles and Methods

The growing packing density and power consumption of very large scale integration (VLSI) circuits have made thermal effects one of the most important concerns of VLSI designers. The increasing variability of key process parameters in nanometer CMOS technologies has resulted in larger impact of the substrate and metal line temperatures on the reliability and performance of the devices and interconnections. Recent data shows that more than 50% of all integrated circuit failures are related to thermal issues. This paper presents a brief discussion of key sources of power dissipation and their temperature relation in CMOS VLSI circuits, and techniques for full-chip temperature calculation with special attention to its implications on the design of high-performance, low-power VLSI circuits. The paper is concluded with an overview of techniques to improve the full-chip thermal integrity by means of off-chip versus on-chip and static versus adaptive methods.     

Efficient algorithms for multilevel power estimation of VLSI circuits

This paper presents a methodology for calculating highly accurate mean power estimates for integrated digital CMOS circuits. A complementary calibration scheme for ASIC library cells to extract the power relevant parameters is proposed. The circuit models presented allows the prediction of mean power dissipation of gate-level designs in CMOS technologies with an accuracy that is comparable to a SPICE simulation but up to 10 000 times faster. The outlined approach is capable of handling complex circuits consisting of more than 20 000 cells and thousands of memory elements. Very large sets of input data with several millions of patterns can, thus, be simulated in an efficient way. This allows the prediction of mean power dissipation of VLSI circuits in a realistic functional context which provides new assessment possibilities for digital CMOS low-power design methods. Experimental results for some benchmark circuits are detailed in order to demonstrate the significant improvements in terms of performance, accuracy, and flexibility of this approach compared to state-of-the-art power estimation methods     

On circuit techniques to improve noise immunity of CMOS dynamic logic

Dynamic CMOS logic circuits are widely employed in high-performance VLSI chips in pursuing very high system performance. However, dynamic CMOS gates are inherently less resistant to noises than static CMOS gates. With the increasing stringent noise requirement due to aggressive technology scaling, the noise tolerance of dynamic circuits has to be first improved for the overall reliable operation of VLSI chips designed using deep submicron process technology. In the literature, a number of design techniques have been proposed to enhance the noise tolerance of dynamic logic gates. An overview and classification of these techniques are first presented in this paper. Then, we introduce a novel noise-tolerant design technique using circuitry exhibiting a negative differential resistance effect. We have demonstrated through analysis and simulation that using the proposed method the noise tolerance of dynamic logic gates can be improved beyond the level of static CMOS logic gates while the performance advantage of dynamic circuits is still retained. Simulation results on large fan-in dynamic CMOS logic gates have shown that, at a supply voltage of 1.6 V, the input noise immunity level can be increased to 0.8 V for about 10% delay overhead and to 1.0 V for only about 20% delay overhead.     

Statistical modeling of MOS devices for parametric yield prediction

In the manufacturing of VLSI circuits, engineering designs should take into consideration random variations arising from processing. In this paper, statistical modeling of MOS devices is reviewed, and effective and practical models are developed to predict the performance spread (i.e., parametric yield) of MOS devices and circuits due to the process variations. To illustrate their applications, the models are applied to the 0.25 μm CMOS technology, and measured data are included in support of the model calculations.     

A Design Style for VLSI CMOS

CMOS is an attractive technology for the realization of VLSI systems. However conventional static CMOS design techniques lead to circuits which are slower and much less densely packed than equivalent NMOS circuits. After a brief review of precharge-discharge techniques, a novel method for designing clocked dynamic CMOS is described. This uses a four-phsse clocking scheme that is free from race and charge-sharing problems and results in faster, more compact layouts. A test chip and a full custom 25 000 transistor serial signal processing chip have been designed using this technique. Results obtained by probing the test ship are presented.     

Floating-body effects in partially depleted SOI CMOS circuits

This paper presents a detailed study on the impact of a floating body in partially depleted (PD) silicon-on-insulator (SOI) MOSFET's on various CMOS circuits. Digital very large scale integration (VLSI) CMOS circuit families including static and dynamic CMOS logic, static cascade voltage switch logic (static CVSL), and dynamic cascade voltage switch logic (dynamic CVSL) are investigated with particular emphasis on circuit topologies where the parasitic bipolar effect resulting from the floating body affects the circuit operation and stability. Commonly used circuit building blocks for fast arithmetic operations in processor data-flow, such as static and dynamic carry lookahead circuits and Manchester carry chains, are examined. Pass-transistor-based designs including latch, multiplexer, and pseudo two-phase dynamic logic are then discussed. It is shown that under certain circuit topologies and switching patterns, the parasitic bipolar effect causes extra power consumption and degrades the noise margin and stability of the circuits. In certain dynamic circuits, the parasitic bipolar effect is shown to cause logic state error if not properly accounted for     

An efficient current-based logic cell model for crosstalk delay analysis

Logic cell modelling is an important component in the analysis and design of CMOS integrated circuits, mostly due to nonlinear behaviour of CMOS cells with respect to the voltage signal at their input and output pins. A current-based model for CMOS logic cells is presented, which can be used for effective crosstalk noise and delta delay analysis in CMOS VLSI circuits. Existing current source models are expensive and need a new set of Spice-based characterisation, which is not compatible with typical EDA tools. In this article we present Imodel, a simple nonlinear logic cell model that can be derived from the typical cell libraries such as NLDM, with accuracy much higher than NLDM-based cell delay models. In fact, our experiments show an average error of 3% compared to Spice. This level of accuracy comes with a maximum runtime penalty of 19% compared to NLDM-based cell delay models on medium-sized industrial designs.     

Two schemes for detecting CMOS analog faults

A design-for-testability scheme for detecting CMOS analog faults was reported by Favalli et al. (see ibid., vol.25, no.5, p.1239-46, 1990). The authors propose two alternative designs, one for small circuits and another for large circuits, which require significantly less area overhead (about 1/4 to 1/3) than that of Favalli's design. With the proposed modification in the first design, the untestable problem, which occurred in Favalli's design, can be alleviated. Furthermore, the proposed schemes are also fit to be implemented in VLSI circuits     

微纳米CMOS VLSI电路可靠性仿真与设计

介绍了CMOS VLSI的可靠性建模和仿真技术的发展历史、相应的仿真工具、失效机理等效电路和算法,重点总结了当前最新的CMOS超大规模集成电路可靠性建模仿真技术,为促进我国集成电路可靠性设计水平起到积极的作用。     

Automated design of switched-current filters

This paper describes the automated design and synthesis of switched-current (SI) filters using SCADS, a flexible CAD system integrated in a major VLSI design suite. With this system, the nonspecialist can produce high performance analog filters suitable for mixed signal CMOS IC's fabricated using only standard digital processes. To achieve high levels of performance on silicon, filter designs are realized using an enhanced differential circuit technique (S²I) in its integrators and sample-and-hold cells. The design system is described in terms of the embedded circuits, its integrated tool set, the filter design flow and the engineering procedures for ensuring reliable circuit operation. Examples of high performance video frequency filters are presented, each generated automatically by SCADS within one day. Fabricated in a 0.8 μm standard CMOS process, they demonstrate state-of-the-art performance     

Current Mode Circuits for Programmable WTA Neural Network

In this article prototype AB class programmable synaptic connection and WTAcircuits that set foundations for low power VLSI neural networks and other applications areproposed. The analysis of the circuits is given. A qualitative comparison of currentconsumption is made between standard A class and proposed AB class circuits. Layouts ofthe AB class transconductance programmable synaptic connection and 2-WTA circuits havebeen designed and then the prototype CMOS circuits have been manufactured and measured.Measured characteristics have been compared to simulated ones.     

Impact of gate induced drain leakage on overall leakage ofsubmicrometer CMOS VLSI circuits

In this paper, the impact of gate induced drain leakage (GIDL) on the overall leakage of submicrometer VLSI circuits is studied. GIDL constitutes a serious constraint, with regards to off-state current, in scaled down complimentary metal-oxide-semiconductor (CMOS) devices for DRAM and/or EEPROM applications. Our research shows that the GIDL current is also a serious problem in scaled CMOS digital VLSI circuits. We present the experimental and simulation data of GIDL current as a function of 0.35-μm CMOS technology parameters and layout of CMOS standard cells. The obtained results show that a poorly designed standard cell library for VLSI application may result in extremely high leakage current and poor yield     

Performance advantages of 3-D digital integrated circuits in a mixed SOI and bulk CMOS design space

Three-dimensional (3-D) integrated circuits (ICs), with multiple stacked device layers, offer a unique design opportunity to use both bulk and partially depleted (PD) silicon-on-insulator (SOI) CMOS devices in a single circuit design. Such 3-D designs can, for example, minimize the body effect common in bulk designs and reduce adverse floating-body effects (FBE) common in PD SOI designs. Sequential 3-D technology such as exfoliation-based single-crystal silicon layer transfer allows a low-temperature approach to 3-D integration with high-density interconnectivity. Using the characteristics of this technology, we present the mixed SOI bulk (MSB) design approach that effectively re-maps conventional VLSI designs to the 3-D design space. Tradeoffs in delay, noise margin, power, and circuit footprint are analyzed and demonstrated through analyzes of static, dynamic, pass-transistor, and SRAM circuits.