基于电流测试的混合电路故障诊断

在运用小波神经网络进行混合电路故障诊断的过程中,测试参数的选取至关重要。研究了一种基于电流测试的故障诊断。该方法即通过PSPICE模拟电路的静态及动态电流信息,再通过小渡神经网络的结合,证明了该方法在混合电路故障诊断中的可行性,为提高混合电路的故障诊断率提供了一种新的方法。     

Wideband precision current sources for integrated circuits

This article introduces two new configurations for precision current sources and current mirrors. Both circuits use n-p-n bipolar devices, but one provides a current source while the other provides a current sink. This permits the use of current sources in IC designs implemented with processes that do not allow p-n-p devices. Analog building blocks such as voltage-to-current converters, active loads, and sink and source current mirrors can be constructed from the new circuits using only n-p-n devices. Furthermore, because these circuits achieve the required precision without the use of high-gain amplifiers, the bandwidths of the circuits are large compared to conventional configurations. The source currents are dependent on a single reference voltage and exhibit good temperature sensitivity.     

New tunable synthetic floating inductors

Three new active RC synthetic floating inductance circuits are proposed which realise lossless f.i. and series and parallel RL impedance, respectively employing three and two second-generation current conveyors as active elements. The novel features of the new circuits are that (i) in contrast to available operational-amplifier circuits for f.i.s, the circuits presented here do not require component matching for the desired realisation; (ii) the new circuits employ a minimum possible number of passive elements (only two resistors and a capacitor); (ii) in all the new circuits, the inductance value is independently controllable through a single resistance.     

Generation of Generalized Impedance Converter Circuits Using NAM Expansion

The generation of the voltage generalized impedance converter (VGIC) circuits using a nodal admittance matrix (NAM) expansion is given in detail. Thirty-two equivalent circuits using current conveyors (CCII) or inverting current conveyors (ICCII) or a combination of both are generated. The reported circuits are suitable for realizing inductors or frequency dependent negative resistors (FDNR) using grounded passive elements. Similarly the generation of the current generalized impedance converter (CGIC) circuits published recently is reexamined and this resulted in 16 more new CGIC circuits using an alternative NAM expansion. Modification of two of the generated circuits to realize a floating inductor or floating FDNR is also given together with Spice simulation results.     

Parallel feedforward class-AB control circuits for low-voltage bipolar rail-to-rail output stages of operational amplifiers

A new family of class-AB control circuits for bipolar rail-to-rail output stages of operational amplifiers is presented. Step by step, we report the development of five simple class-AB control circuits showing the advantages of using parallel feedforward. The circuits have been designed in such a way that temperature, supply voltage and process parameters have little influence. To test the output stages, one of them has been implemented in a very simple two-stage operational amplifier on a semi-custom chip. Measurements show a bandwidth of 2.5 MHz, a gain of 40 dB, a quiescent current of 23µA and a maximum output current of 250µA. Simulation results of three other simple operational amplifiers with the new class-AB control circuits are shown, which have a higher gain and maximum output current.     

New simple square-rooting circuits based on translinear current conveyors

Two new square-rooting circuits, based on second-generation current-controlled current conveyors (CCCIIs), are presented. The first square-rooting circuit consists of two CCCIIs, one current-controlled resistor and two grounded resistors. The input signal of the first circuit is a voltage, and output is the voltage proportional to the square root of input voltage. The second one consists of two CCCIIs and a current-controlled resistor. In the second circuit, the input signal is a current, and output is the current proportional to the square root of input current. Each circuit realizes by using a current-mode technique; hence the proposed square-rooting circuits are simple circuitry, wide dynamic range and wide bandwidth. The proposed square-rooting circuits were confirmed by using PSPICE simulation.     

A current-controlled latch sense amplifier and a staticpower-saving input buffer for low-power architecture

Two new power-saving schemes for high-performance VLSIs with a large-scale memory and many interface signals are described. One is a current-controlled latch sense amplifier that reduces the power dissipation by stopping sense current automatically. This sense amplifier reduces power without degrading access time compared with the conventional current-mirror sense amplifier. The other is a static power-saving input buffer (SPSIB) that reduces DC current in interface circuits receiving TTL high input level. The effectiveness of these new circuits is demonstrated with a 512-kb high-speed SRAM     

Semicustom Design Methodology of Power Gated Circuits for Low Leakage Applications

The application of power gating to cell-based semi- custom design typically calls for customized cell libraries, which incurs substantial engineering efforts. In this brief, a semicustom design methodology for power gated circuits that allows unmodified conventional standard-cell elements is proposed. In particular, a new power network architecture is proposed for cell-based power gating circuits. The impact of body bias on current switch design and the layout method of current switch for flexible placement are investigated. The circuit elements that supplement cell-based power gating design are then discussed, including output interface circuits and state retention flip-flops. The proposed methodology is applied to ISCAS benchmark circuits and to a commercial Viterbi decoder with 0.18-mum CMOS technology.     

Pathological realizations of the DCVC (CDBA) and applications to oscillators and filters

The historical origin of the introduction of the differential current voltage conveyor (DCVC) also known as the current differencing buffered amplifier (CDBA) is reviewed. Pathological realizations of the modified differential current conveyor (MDCC) and of the DCVC are given. Generation of alternative equivalent oscillator and filter circuits using voltage followers (VF), current followers (CF), voltage inverters (VI) and current inverters (CI) from known CDBA oscillators and filters is demonstrated by several examples. It is found that there is duplication in some of the recently published circuits and new simplified oscillator and filter circuits are reported.     

新型电流控制电流传输器

提出了一种新型电流控制电流传输器(CCCII)电路。该CCCII电路由跨导线性环电路和双极性Wilson电流镜构成。为实现该新型CCCII电路,还提出了双端输出的双极型Wilson电流镜。该CCCII电路具有输出阻抗高、电压及电流传输精度高、易于实现、便于集成等优点。文中分析了电路的工作原理,给出了实验结果,验证了电路的正确性。     

Temperature compensation of translinear current conveyor and OTA

A simple and integrable temperature compensation scheme for translinear current conveyor-based circuits and OTA-based circuits is introduced. It uses a new bias circuit which has a current that is directly proportional to the absolute temperature, and can also be electronically varied. Performance of the scheme is confirmed through PSPICE simulation results     

Novel Cascadable All-Pass/Notch Filters Using a?Single?FDCCII and Grounded Capacitors

Four new second-order voltage-mode cascadable all-pass/notch filters are proposed using only a single active element and four passive components. The active element used is a fully differential current conveyor. All the circuits possess high-input and low-output impedance, which is a desirable feature for voltage-mode circuits. A non-ideal and parasitic study is also performed. The proposed circuits are verified through PSPICE simulation results.     

一种双极型基本电流镜的改进电路

在低电压、低功耗电流模式信号处理电路设计中，电流镜是必不可少的器件。他不仅实现电流信号的复制或倍乘/倍减，极性互补的电流镜还可以实现差动--单端电流信号的交换，还可提供高输出阻抗以便产生稳定的电流。在本文双极型电流镜的改进电路中，通过利用复合管的放大作用，实现了跟随误差的减小。     

FDCCII-based FDNR simulator topologies

In this article, three new circuits for realising frequency-dependent negative resistance (FDNR) are proposed. All proposed circuits employ a single fully differential current conveyor, grounded capacitors and resistor. Proposed circuits consist of minimum number of passive and active elements. All proposed circuits are lossless FDNR. The performance of the proposed FDNR is demonstrated on the third-order Butterworth low-pass filter. Simulation results are included to verify the theory.     

Analyses and design of bias circuits tolerating output voltages above BV/sub CEO/

Due to the inevitable tradeoff between speed and breakdown voltage, the spectacular speed improvement of modern SiGe processes in recent history has partially been achieved at the cost of a reduction in breakdown voltages. Because supply voltages have hardly been reduced however, circuits operating at a supply voltage above the collector-emitter breakdown voltage (BV/sub CEO/) are common practice today and collector-base avalanche currents are therefore of major concern. Transistors that need to handle a collector-emitter voltage above (BV/sub CEO/) are typically found as output transistors in output driver stages and in bias current circuits. Such circuits can be designed to tolerate collector-emitter voltages above (BV/sub CEO/) by driving the base terminal with a relatively low impedance. This paper analyzes various conventional as well as two new bias current circuits supporting operation at collector voltages above (BV/sub CEO/). In the new circuits, feedforward and feedback avalanche current compensation techniques are introduced that obtain a substantial increase in output breakdown voltage of the bias circuits and improve the accuracy of the current mirror at output voltages above (BV/sub CEO/). With the feedback technique, a measured increase in output breakdown voltage by more than 2 V is demonstrated while the accuracy of the current mirror ratio at output voltages of 2 to 3 times (BV/sub CEO/) is improved by an order of magnitude.     

Full-swing Schottky BiCMOS/BiNMOS and the effects of operatingfrequency and supply voltage scaling

Novel full-swing BiCMOS/BiNMOS logic circuits which use Schottky diode in the pull-up section for low supply-voltage regime are developed. The full-swing pull-up operation is performed by saturating the bipolar transistor with a base current pulse. After which, the base is isolated and bootstrapped to a voltage higher than V_DD. The BiCMOS/BiNMOS circuits do not require a PNP bipolar transistor. They outperform other BiCMOS circuits at low supply voltage, particularly at 2 V using 0.5 μm BiCMOS technology. Delay, area, and power dissipation comparisons have been performed. The new circuits offer delay reduction at 2 V supply voltage of 37% to 56% over CMOS. The minimum fanout at which the new circuits outperform CMOS gate is 2 to 3. Furthermore, the effect of the operating frequency on the delay of a wide range of BiCMOS and BiNMOS circuits is reported for the first time, showing the superiority of the Schottky circuits     

Duet: an accurate leakage estimation and optimization tool fordual-Vt circuits

Presents a new approach for the estimation and optimization of standby power dissipation in large MOS digital circuits. We introduce a new approach for accurate and efficient calculation of the average standby or leakage current in large digital circuits by introducing the concepts of "dominant leakage states" and the use of state probabilities. Combined with graph reduction techniques and simplified nonlinear simulation, the method achieves speedups of three to four orders of magnitude over exhaustive SPICE simulations while maintaining very good accuracy. The leakage current calculation is then utilized in a new leakage and performance optimization algorithm for circuits using dual V_t processes. The approach is the first to consider the assignment of both the V_t and the width of a transistor, simultaneously. The optimization approach uses incremental calculation of leakage and performance sensitivities and can take into account a partially defined circuit state constraint for the standby mode of the device     

Three port gyrator circuits using transconductance amplifiers or generalized conveyors

The three port gyrator was introduced and defined in [1] in two alternative forms of the admittance matrix (Y). Four alternative realizations of the three port gyrator using three transconductance amplifiers (TA) are given, three of them are new. Sixteen alternative three port gyrator circuits using four current conveyors (CCII) or four inverting current conveyors (ICCII) or a combination of both of them and four grounded resistors are given. Eight alternative three port gyrator circuits using two CCII or two ICCII or a combination of both of them, balanced output current conveyors (BOCCII) and three grounded resistors are also introduced. Eight alternative three port gyrator circuits using two CCII or two ICCII or a combination of both of them, differential voltage current conveyors (DVCC) and three grounded resistors are also introduced. Finally four equivalent three port gyrator circuits using a combination of DVCC and BOCCII and two grounded resistors are also introduced, three of them are new.     

一种新型电荷泵电路的设计

文章提出了一种新的全差分电荷泵结构，与传统电荷泵电路相比，这个电路具有输出范围大和无跳跃现象的优点，同时还可以有效地解决电荷泄漏和充放电失配等问题。     

Applications of a first-generation current conveyor in current-mode circuits

In current-mode filter circuits which utilise a single current conveyor as the only active device, the first-generation current conveyor permits feedback of the response without connecting filter elements to the output port. Complex poles can be realised in such circuits while maintaining high output impedance. The utility of this observation is illustrated by the derivation of new second-order, complex-pole, current-mode, all-pass networks that employ a single current conveyor. Laboratory and simulation results are compared.<>