Measuring the high frequency performance of digital imageacquisition systems

A new method for measuring the two dimensional modulation transfer function of an image acquisition system containing a CCD array has been described. The results were as predicted by theory. System signal aliasing and feature representation have been discussed. Horizontal cutoff frequencies as low as 40% of the vertical were recorded     

Clock frequency and latency in synchronous digital systems

The tradeoffs in the design of synchronous digital systems between clock frequency and latency in terms of the circuit characteristics of a pipelined data path are described. A design paradigm relating latency and clock frequency as a function of the level of pipelining is developed for studying the performance of a synchronous system. This perspective permits the development of design equations for constrained and unconstrained design problems which describe these performance parameters in terms of the delays of the logic, interconnect, registers, clock skew, and the number of logic states. These results provide an approach to the design of those synchronous digital systems in which latency and clock frequency are of primary importance. From the behavioral specifications for the proposed system, the designer can use these results to select the best logic architecture and the best available device technology to determine if the performance specifications can be satisfied, and, if so, what design options are available for optimization of other system attributes, such as area     

International fixed satellite systems in synchronous digital hierarchy transport networks

This paper discusses functional and architectural aspects and suitable networks scenarios for the integration of international fixed satellite systems, such as the INTELSAT system, in and between digital networks implementing the new CCITT synchronous digital hierarchy (SDH). The paper presents SDH transmission network functional requirements, and combines them with current and anticipated future FSS operational requirements. It is shown that integration permits the use of SDH functions and features for enhanced network service provisioning by FSS in the international network fabric, and leads to new FSS system design criteria.     

Measuring the end-to-end performance of digital video systems

Significant research and development efforts by industry and government laboratories were brought to fruition in 1996 with the approval of the American National Standard (ANSI) T1.801.03 entitled “American National Standard for Telecommunications-Digital Transport of One-Way Video Signals-Parameters for Objective Performance Assessment.” This standard provides a set of objective parameters that have consistently demonstrated high correlation levels with subjective evaluations of digital video impairments. The parameters are technology-independent and may be used to measure the performance of a wide range of digital video compression, storage, and transmission systems. This paper presents an overview of the ANSI T1.801.03 parameters and summarizes other relevant standards activities and contributions     

Pipelining with common operands for power-efficient linear systems

We propose a systematic pipelining method for a linear system to minimize power and maximize throughput, given a constraint on the number of pipeline stages and a set of resource constraints. Unlike most existing pipelining approaches, our method takes the number of pipeline stages as one of the constraints and considers the pipelining as an aspect of power minimization. Operations are retimed so that as many operations as possible take common operands as their inputs, using a novel technique called force-directed retiming; operand sharing is then determined, based on list scheduling. Experimental results show that the proposed approach reduces the power consumption of functional units by 27.8% on average and by more than 50% in some cases, compared to the state-of-the-art pipelining and operand sharing techniques.     

Pipelining communications in large VLSI/ULSI systems

A simple and very effective solution to the delay incurred while propagating data through long interconnection wires is presented. Such delays can be found in large VLSI/ULSI or wafer scale systems. The basic idea of the technique relies on the fragmentation of the wires and in reconnecting them with a special device called repeater in order to form a bidirectional pipeline. A method for determining the optimum configuration of the pipeline is presented. It is shown that, even in presence of an appreciable skew in synchronous systems, the technique improves the transmission speed by 150% for 32-byte messages, when a 10 cm 8-bit bus implemented in a 1.2 μm CMOS technology is used. The improvement increases for longer messages and for larger skews. It is also shown that the actual transmission time is close (to within a factor of 2) to the theoretical limit that could be achieved with a zero-length wire. A method based on repeaters operating at a multiple of the basic system clock frequency is also proposed. It is shown that this technique may speedup data transfer by an order of magnitude. The extension of the technique to asynchronous self-timed repeaters is also discussed. Finally, a VLSI implementation of the synchronous reconnection device is described     

Error correction performance in digital subscriber looptransmission systems

The author describes an error correction system for digital subscriber loop transmission systems which use time compression multiplexing (TCM). An interleaved block code is used to correct the burst errors due to impulse noise from analog telephone circuits. This interleaving method requires no extra hardware and contributes no additional delay. To evaluate the transmission performance of this error correction system, the bit error rate after decoding is derived on the basis of a burst error model for 200 kb/s digital subscriber transmission using the alternate mark inversion (AMI) line code. The experimental results for a 200 kb/s TCM system show that burst errors are substantially reduced     

Accurate and efficient simulation of synchronous digital switching noise in systems on a chip

A new method is presented to compress switching information in large synchronous digital circuits. This is combined with an efficient generation of digital cell library noise signatures and results in an accurate estimation of the switching noise in digital circuits. It provides a practical approach to generating the digital switching noise for simulating substrate coupling noise in mixed-signal ICs. Nearly two orders of magnitude reduction in the memory and simulation time are achieved using this approach without significant loss of accuracy.     

New high power, high performance power converter systems

A new, high performance, low cost power converter system architecture is proposed. The system consists of a main converter and a multifunctional load conditioner. The main converter deals with most of the power flow running at a low switching frequency. The load conditioner is designed at a much lower power level running at a high-switching frequency. The load conditioner can (1) act like a current source and inject harmonic currents required by the load; (2) act like an active resistor to provide damping to the main converter; and (3) for three-phase inverters, decouple the coupling sources in the main inverter model in the rotating coordinates to make the control loop design for the main inverter much easier. The concept has been proved by simulation and experimental results on a 150 kW high performance three-phase utility power supply prototype. The proposed system configuration can be used in high power DC-DC converters, inverters, PFC and UPS applications     

一种快速无线电监测接收机实现

研究了一种快速准确的信号识别系统,可应用于无线电监测。系统由模拟接收、数字接收和处理终端等部分构成,模拟接收部分和现有的无线电监视接收机具有相同的功能,数字接收包括适应不同带宽信号的多速率数据采集和数字下变频,数据实时地由 PCI 总线传输到处理终端,处理终端由微机和加裁的信号识别应用软件构成。试验证实了系统能正确完成数据采集、数据分析和快速准确识别信号等设计功能。系统还具有通用性的特点、功能可选择。     

Influence of terrain-induced reflections on the performance ofhigh-capacity digital radio systems

The performance of a high-capacity digital radio system is evaluated in the presence of ground-induced reflections and atmospheric fading. Results indicate that ground reflections significantly contribute to outage even when their amplitude is 20-25 dB below the main signal. A three-path channel model is used to simulate reflections from the terrain and atmosphere. With this model, the group delay suffers extremely rapid phase transitions and the amplitude pattern shows the presence of minima deeper than that produced by either ray alone     

A synchronous digital hierarchy network management system

The critical issues in multivendor environments and operation systems of telecommunication networks essential to speeding up the handling of service orders and service restoration after failures are discussed. To overcome these problems as the software backlog grows, the authors propose the application of a telecommunications management network (TMN) architecture together with an object-oriented network resource (ONR) model. The second phase of the synchronous digital hierarchy (SDH) network management system, which is based on the TMN architecture and ONR model, is examined     

Broadband transport — the synchronous digital hierarchy

All data networks require a physical transmission medium to convey information between network nodes. Within a local environment this physical medium might, for example, take the form of an Ethernet LAN, but wide area connections are provided using telecommunications constant bit rate transmission equipment. Furthermore, the assumption that data networking is simply the provision of WAN connectivity for large corporate networks is becoming dated. The explosion of interest in the Internet means that, for transport networks, the term data may encompass voice, video and multimedia applications for delivery to both home and office. This places additional requirements on the network infrastructure as each service has specific transport requirements.Network operators are currently in the process of deploying core networks of equipment conforming to the ITU-T Recommendations for a synchronous digital hierarchy (SDH), but many networks also contain a significant proportion of older transmission technologies. This paper provides a review of transmission technology and describes the impact of such networks on the transport of data.     

Clock distribution networks in synchronous digital integratedcircuits

Clock distribution networks synchronize the flow of data signals among synchronous data paths. The design of these networks can dramatically affect system-wide performance and reliability. A theoretical background of clock skew is provided in order to better understand how clock distribution networks interact with data paths. Minimum and maximum timing constraints are developed from the relative timing between the localized clock skew and the data paths. These constraint relationships are reviewed, and compensating design techniques are discussed. The field of clock distribution network design and analysis can be grouped into a number of subtopics: 1) circuit and layout techniques for structured custom digital integrated circuits; 2) the automated layout and synthesis of clock distribution networks with application to automated placement and routing of gate arrays, standard cells and larger block-oriented circuits; 3) the analysis and modeling of the timing characteristics of clock distribution networks; and 4) the scheduling of the optimal timing characteristics of clock distribution networks based on architectural and functional performance requirements. Each of these areas is described the clock distribution networks of specific industrial circuits are surveyed and future trends are discussed     

Automatic aperture performance measurement for high speed analogue?digital convertors

A technique for assessing the dynamic aperture performance of high speed analogue?digital convertors is proposed which treats the test unit as a black box. Details of data processing and analysis are included which give a performance measure in terms of effective convertor resolution.     

The impact of G.826 [digital systems error performance]

The International Consultative Committee for Telephone and Telegraph (CCITT) recommendation G.826, the error performance recommendation for digital systems operating at or above the primary rate, is summarized. The relationship between block-based error performance parameters and the bit error rate (BER) is reviewed. The transition from the previous recommendation, G.821, to G.826 is discussed, including a brief statement of the main points found in G.826. The conversion of block-based error performance objectives (EPOs) to BER criteria is discussed in a nonmathematical way. The implications of G.826 and some conclusions are presented     

一种高动态性能数字DC-DC算法建模与芯片设计

降压型DC-DC模块在手机、笔记本等便携式设备中应用极其广泛,它能给基带芯片提供不随负载变化的稳定电压,使整个设备正常工作.随着消费电子的发展,复杂的功能转换导致基带芯片负载的快速变化,因而要求电源芯片有更好的动态性能.采用直接数字法对DC-DC进行建模,利用根轨迹与开环波特图来联合设计补偿函数,并设计新的电路结构,将整个算法压缩至一个周期内完成,仿真达到良好的动态响应.最后以手机基带芯片供电这一应用为背景,采用UMC 0.18 μm工艺,完成了全部芯片设计,其工作频率为1 MHz,输入电压变化范围为3.3 V到2.4 V,输出电压为1.25 V,纹波小于0.5%,负载变化范围为50 mA到800 mA,电压稳定时间小于140 μs.     

MPSK数字解调器同步方案的实现

多进制相移键控MPSK调制信号的解调中,为提高解调性能,得到精确快速的载波同步和时钟同步,需要对载波检测和时钟检测作精心的设计。对MPSK的数字解调方法做了一些探讨,在载波同步中,分析了基于功率检测的频差检测方法及基于相差检测进行相位锁定的方法;详细介绍了时钟同步的波形估计方法的基本原理及幅度和频谱宽度对定时误差的影响。