Modeling and simulation of combinational CMOS logic circuits by ANFIS

In this paper, application of adaptive neuro-fuzzy inference system (ANFIS) in modeling of CMOS logic gates as a tool in designing and simulation of CMOS logic circuits is presented. Structures of the ANFIS are developed and trained in MATLAB 7.0.4 program. We have used real hardware data for training the ANFIS network. A hybrid learning algorithm consists of back-propagation and least-squares estimation is used for training. Influence of the structure of the proposed ANFIS model on accuracy and network performance has been analyzed through some combinational circuits. For the comparison of the ANFIS simulation results, we have simulated the circuits in HSPICE environment with 0.35 μm process nominal parameters. The comparison between ANFIS, HSPICE, and real hardware shows the feasibility and accuracy of the proposed ANFIS modeling procedure. The results show the proposed ANFIS simulation has much higher speed and accuracy in comparison with HSPICE simulation and it can be simply used in software tools for designing and simulation of complex CMOS logic circuits.     

A 5-GHz low-voltage and low-power CMOS LC voltage controlled oscillator for 802.11a wireless LAN applications

In this paper, a low phase noise and low power 5.15?GHz LC-tank VCO is presented and analysed. The phase noise achieved is??91,??116 and??126?dBc/Hz at 100?KHz, 1?MHz and 3?MHz offsets respectively from the carrier frequency of 5.15?GHz, with 1.8?V power supply voltage and giving a very low power consumption of about 2.5?mW by considering the proposed oscillator topology, which consumes less power than the classical oscillator using the traditional differential transconductor pair. A broad tuning range has been achieved by means of standard mode PMOS varactors. The tunability of the designed VCO covers 530?MHz, from 4.78?GHz up to 5.31?GHz. Predicted performance has been verified by analyses and simulations using ELDO-RF tool with 0.35?µm CMOS TSMC parameters.     

由pnp双极型晶体管和PMOS构成的CMOS负阻单元

使用pnp双极型晶体管和pMOS,按照正反馈产生负阻I-V特性的原理,采用CMOS工艺,设计研制成功CMOS负阻单元,并对它进行了实际的测试与验证,效果良好,而且可以用它作为基础性器件,构成与CMOS工艺相兼容的负阻型逻辑电路,比常规CMOS电路节省大量器件。     

Design of two Low-Power full adder cells using GDI structure and hybrid CMOS logic style

Full adder is one of the most important digital components for which many improvements have been made to improve its architecture. In this paper, we present two new symmetric designs for Low-Power full adder cells featuring GDI (Gate-Diffusion Input) structure and hybrid CMOS logic style. The main design objectives for these adder modules are not only providing Low-Power dissipation and high speed but also full-voltage swing.     

Pass transistor with dual threshold voltage domino logic design using standby switch for reduced subthreshold leakage current

Dual threshold voltages domino design methodology utilizes low threshold voltages for all transistors that can switch during the evaluate mode and utilizes high threshold voltages for all transistors that can switch during the precharge modes. We employed standby switch can strongly turn off all of the high threshold voltage transistors which enhances the effectiveness of a dual threshold voltage CMOS technology to reduce the subthreshold leakage current. Subthreshold leakage currents are especially important in burst mode type integrated circuits where the majority of the time for system is in an idle mode. The standby switch allowed a domino system enters and leaves a low leakage standby mode within a single clock cycle. In addition, we combined domino dynamic circuits style with pass transistor XNOR and CMOS NAND gates to realize logic 1 output during its precharge phase, but not affects circuits operation in its evaluation and standby phase. The first stage NAND gates output logic 1 can guarantee the second stage computation its correct logic function when system is in a cascaded operation mode. The processing required for dual threshold voltage circuit configuration is to provide an extra threshold voltage involves only an additional implant processing step, but performs lower dynamic power consumption, lower delay and high fan-out, high switching frequencies circuits characteristics. SPICE simulation for our proposed circuits were made using a 0.18 µm CMOS process from TSMC, with 10 fF capacitive loads in all output nodes, using the parameters for typical process corner at 25 °C, the simulation results demonstrated that our designed 8-bit carry look-ahead adders reduced chip area, power consumption and propagation delay time more than 40%, 45% and around 20%, respectively. Wafer based our design were fabricated and measured, the measured data were listed and compared with simulation data and prior works. SPICE simulation also manifested lower sensitivity of our design to power supply, temperature, capacitive load and process variations than the dynamic CMOS technologies.