Relationship between settling time and pole–zero placements for three-stage CMOS opamp

In this article, the effect of pole–zero placements on settling time has been analysed for a three-stage CMOS operational amplifier (opamp) with nested Miller compensation (NMC) and reversed nested Miller compensation (RNMC) schemes. In this study, optimised balancing of speed and power is done for a three-stage CMOS opamp for a given load condition (on-chip opamp). Optimum values of circuit parameters have been derived for power efficient shifting of poles and zeros. The effect of placement of poles and zeros on dynamic settling error (DSE) is analysed by means of numerical simulation using MATLAB. This analysis will be useful to ascertain the relationship between pole–zero placements and settling time. The study of the effects of compensation elements on pole–zero placements has been done to assist the circuit designers to achieve better performance. Analysis of the effect of capacitive load on pole–zero placements and DSE has been done in this study. A technique has been developed to find out the upper and lower limits of compensation capacitor that allows fast settling with low power. The validity of the analytical work has been checked by simulation using Tanner tool in 0.35-µm CMOS technology. In the case of RNMC scheme, a power dissipation of 60.17?µw and a settling time of 340?ns are achieved; the results obtained are better than the earlier reported design technique. In the case of NMC, the simulation has been done to validate the analytical analysis.     

Design procedure for two-stage CMOS opamp with optimum balancing of speed,power and noise

This article presents a basic two-stage CMOS opamp design procedure that provides the circuit designer with a means to establish optimised balancing between speed, power and noise for a given load condition. The proposed design steps allow opamp designers to optimise the power consumption for the given constraints of settling time, accuracy, noise and load. The key factor is to establish the optimum combination of ratios of transconductance of second stage to first stage and load capacitor to compensation capacitor. So, required accuracy and settling time can be established with minimum power consumption. Unlike the earlier reported design procedures, in this article a systematic method is presented to set the quiescent voltages at the transistors of the first and second stages of the opamp. This work will be helpful to select appropriate method of implementation of Miller compensation for given constraints. To verify the viability of the proposed design steps, SPICE simulation results for the proposed procedure are given. Best simulation results obtained on Tanner tool show settling time and power dissipation equal to 320 ns and 188.5 μW, respectively, for 5 pf capacitive load.     

A 14-bit 250 kS/s two-step inverter-based incremental $$\varSigma \varDelta$$ ADC for CMOS image sensor in $$0.18\,\upmu \hbox {m}$$0.18μm technology

This paper presents an ultra-low-power, bulk-driven, source-degenerated fully differential transconductor (FD-OTA), operating in subthreshold region. The source-degeneration (SD) and bulk-drive ensure linearity and rail-to-rail input swing. The flipped voltage follower and SD resistor perform V–I conversion in input core with power efficient class AB mode of operation. The reduction in open loop gain and gain bandwidth (GBW) of bulk-drive is compensated by applying partial positive feedback at diode connected MOSFET pair. The current gain from input core to output load side is set (1:1) in OTA₁ and (1:4) in OTA₂. The OTA₂ offers increased transconductance and GBW whereas self-cascode load increases the output impedance and overall gain of the FD-OTAs. Both the input core and common source self-cascode load operate in class AB mode so these FD-OTAs provide enhanced slew rates. These OTAs have been employed to implement Biquadratic low-frequency G_m-C filter suitable for bio-signal applications. The proposed OTA₂ has used dual supply voltage of ± 0.3 V and dissipates around 70 nW power and provides 62 dB FD-open loop gain with GBW of 7.73 kHz while driving the FD-load of 2 × 15 pF. The Cadence VIRTUOSO environment using UMC 0.18 µm CMOS process technology has been used to simulate the proposed circuit. The Simulation results verified fully differential total harmonic distortion of ? 72 dB, for 1.2 V_p–p signal at 200 Hz frequency in unity gain configuration with resistive degeneration of 1 MΩ for OTA₁.     

High-gain,high-bandwidth,rail-to-rail,constant-gm CMOS operational amplifier

This study presents a high-gain, high-bandwidth, constant-g_m , rail-to-rail operational amplifier (op-amp). The constant transconductance is improved with a source-to-bulk bias control of an input pair. A source degeneration scheme is also adapted to the output stage for receiving wide input range without degradation of the gain. Additionally, several compensation schemes are employed to enhance the stability. A test chip is fabricated in a 0.18?µm complementary metal-oxide semiconductor process. The active area of the op-amp is 181?×?173?µm² and it consumes a power of 2.41?mW at a supply voltage of 1.8?V. The op-amp achieves a dc gain of 94.3?dB and a bandwidth of 45?MHz when the output capacitive load is connected to an effective load of 42.5?pF. A class-AB output stage combining a slew rate (SR) boost circuit provides a sinking current of 6?mA and an SR of 17?V/µs.     

Inductor-less PVT robust gain switching balun LNA for multistandard applications

An inductor-less single to differential low-noise amplifier (LNA) is proposed for multistandard applications in the frequency band of 0.2–2 GHz. The proposed LNA incorporates noise cancellation and voltage shunt feedback configuration to achieve minimum noise characteristics and low power consumption. In addition to noise cancellation, trans-conductance of common-source stage is scaled to improve the noise performance. In this way, noise figure (NF) of LNA below 3 dB is achieved. An additional capacitor C_c is used to correct the gain and phase imbalance at the output. The gain switching has been enabled with a step size of 4 dB for high linearity and power efficiency. The bias point of all transistors is chosen such that the variation in g_m is not more than 10%. The proposed LNA is implemented in UMC 0.18-μm RF CMOS technology. The core area is 182 μm × 181 μm. Moreover, the LNA has better ratio of relevant performance to area. The proposed balun LNA is validated by rigorous Monte Carlo simulation. The 3σ deviation of gain and NF is less than 5%. Finally, the proposed LNA is robust to unavoidable PVT variations.     

A Reconfigurable Low-Noise Amplifier Using a Tunable Active Inductor for Multistandard Receivers

A reconfigurable low-noise amplifier (LNA) based on a high-value active inductor (AI) is presented in this paper. Instead of using a passive on-chip inductor, a high-value on-chip inductor with a wide tuning range is used in this circuit and results in a decrease in the physical silicon area when compared to a passive inductor-based implementation. The LNA is a common source cascade amplifier with RC feedback. A tunable active inductor is used as the amplifier output load, and for input and output impedance matching, a source follower with an RC network is used to provide a 50 Ω impedance. The amplifier circuit has been designed in 0.18 µm CMOS process and simulated using the Cadence Spectra circuit simulator. The simulation results show a reconfigurable frequency from 0.8 to 2.5 GHz, and tuning of the frequency band is achieved by using a CMOS voltage controlled variable resistor. For a selected 1.5 GHz frequency band, simulation results show S ₂₁ (Gain) of 22 dB, S ₁₁ of ?18 dB, S ₂₂ of ?16 dB, NF of 3.02 dB, and a minimum NF (NFmin) of 1.7 dB. Power dissipation is 19.6 mW using a 1.8 V dc power supply. The total LNA physical silicon area is (200×150) µm².     

Figure of merit for integrated bipolar transistors

The maximum frequency of operation, ω_max, which is the frequency of operation when the unilateral power gain goes to zero, and ω_T, the unity current gain-bandwidth product, are used as figures of merit for bipolar transistors. Both of these figures of merit are inadequate for state-of-the-art integrated bipolar devices. This is because ω_max is based on neutralizing the feedback between the transistor output and input circuitry by complex networks which are quite impractical in integrated circuits, and ω_T is obtained with the output short circuited and thus has no relevance to a practical application.In this paper, we argue the case for using ω_PT the frequency at which the power transferred between identical amplifiers goes to unity as a practical figure of merit for the integrated bipolar transistor.     

Jitter and phase noise of ADPLL due to PSN with deterministic frequency

In this article, jitter and phase noise of all-digital phase-locked loop due to power supply noise (PSN) with deterministic frequency are analysed. It leads to the conclusion that jitter and phase noise heavily depend on the noise frequency. Compared with jitter, phase noise is much less affected by the deterministic PSN. Our method is utilised to study a CMOS ADPLL designed and simulated in SMIC 0.13?µm standard CMOS process. A comparison between the results obtained by our method and those obtained by simulation and measurement proves the accuracy of the predicted model. When the digital controlled oscillator was corrupted by PSN with 100?mVpk-pk, the measured jitters were 33.9?ps at the rate of f_G?=?192?MHz and 148.5?ps at the rate of f_G?=?40?MHz. However, the measured phase noise was exactly the same except for two impulses appearing at 192 and 40?MHz, respectively.     

一种新型高速CMOS全差分运算放大器设计

设计了一种基于流水线模/数转换系统应用的低压高速CMOS全差分运算放大器。该运放采用了折叠式共源共栅放大结构与一种新型连续时间共模反馈电路相结合以达到高速度及较好的稳定性。设计基于SMIC 0.25μm CMOS标准工艺模型,在Cadence环境下对电路进行了Spectre仿真。在2.5V单电源电压下,驱动0.5pF负载时,开环增益为71.1dB,单位增益带宽为303MHz,相位裕度为52°,转换速率高达368.7V/μs,建立时间为12.4ns。     

Harmonic Distortion in Switched Current Cells Due to Settling Error

An analysis of the harmonic distortion in switched-current cells produced by the non-linear settling error is presented. Two approaches for computing the harmonic components are addressed: discrete-time Fourier series and power series expansion. They are based on the large signal behavior of the SI cell. A compact and flexible expression is obtained with series expansion. An alternative expression is presented for cases where only the settling error magnitude is required. The effect of charge redistribution between the input and the sampling nodes is analyzed. It is shown that including that effect, the harmonic distortion is increased, and the DC gain of the SI integrator is reduced. An analysis of the total harmonic distortion when clock-feed-through and non-linear settling error are both taken into account is presented. It is demonstrated that minimum distortion is reached for a given capacitive value. For a SI cell designed with 0.8 μm standard CMOS technology working at a sampling frequency of 8 MHz, a minimum THD of ?72 dB can be obtained with a C _gs ≈ 2.4 pF.     

Design of a low power voltage regulator for high dynamic range of load current

This paper presents a design technique of a low power, linear voltage regulator for high dynamic range of load current with good transient performances. It has been achieved by introducing a dynamic leakage path (pull down) at the driver stage of the voltage regulator. The pull down current through the dynamic leakage path is kept very small in steady condition for minimizing internal static power. While in high-to-low load current transition, the current through the dynamic leakage path is magnified for a small duration of time to achieve smaller settling time. The concept of the dynamic leakage path proves to be a more power efficient method than the static leakage method, especially in low standby current applications. The circuit is implemented in 0.18?µ CMOS technology and the voltage regulator generates 1.9?V from 3.3?V supply. The dynamic leakage path consumes additional 37?µA current, averaged over 7.2?µS time when the load current switches from high to low value, but consumes only 14?µA current in steady state.     

Scaling characteristics of fNQS and ft in NMOSFETs with uniform and non-uniform channel doping

Extensive process and device simulations are performed to investigate the non-quasi-static transition frequency (f_NQS ) and unity gain frequency (f_t ) behaviour of the NMOSFETs at different technology nodes, varying from 0.5?µm to 90?nm. The scaled transistors are constrained to have identical leakage current (I_OFF ) at scaled voltages to facilitate a fair comparison. f_NQS exhibits a turn-around in the 100?nm regime irrespective of the channel engineering. We attribute this effect to the reduced gate over-drive (V_GS-V_t ) and lower mobility; which inturn degrades the transconductance (g_m ). f_t also shows a similar trend. The turn around effect of f_NQS and f_t disappears, when I_OFF constraint is relaxed or the gate over-drive is increased.     

A fast-transient high-PSR output-capacitor-free low-dropout regulator for low-power embedded systems

A low-power fast-transient output-capacitor-free low-dropout regulator (LDO) with high power-supply rejection (PSR) is presented in this paper. The proposed LDO utilizes a non-symmetrical class-AB amplifier as the input stage to improve the transient performances. Meanwhile, PSR enhancement circuit, which only consumes 0.2-µA quiescent current at light load, is utilized to form a feedforward cancellation path for improving PSR over wide frequency range. The LDO has been designed and simulated in a mixed signal 0.13-µm CMOS process. From the post simulation results, the LDO is capable of delivering 100-mA output current at 0.2-V dropout voltage, with 3.8-µA quiescent current at light load. The undershoot, the overshoot and the 1 % settling time of the proposed LDO with load current switching from 50 µA to 100 mA in 300 ns are about 100 mV, 100 mV and 1 µs, respectively. With the help of proposed PSR enhancement technique, the LDO achieves a PSR of ?69 dB at 100 kHz frequency for a 100-mA load current.     

Characterization of indoor time reversal UWB communication systems: Spatial,temporal and frequency properties

In this paper, an indoor UWB communications system that applies time reversal (TR) for transmitting the desired signal is proposed. First we define equivalent channel model of TR‐UWB, which is the convolution of channel impulse response and its complex conjugate time‐reversed version. Then spatial, temporal and frequency characteristics of equivalent channel are analyzed and the analytical or semi‐analytical results are validated by comparing measurements with simulation. (Semi) analytical expression of equivalent channel transfer function, TR UWB power delay profile (PDP), focusing gain, spatial correlation and power azimuth spectrum (PAS) is performed. Also probability density function (PDF) of TR‐UWB amplitude and path‐gain is derived. Analysis and simulation results of different distributions, such as uniform, Laplacian and Gaussian for PAS, are considered and presented. It is shown that uniform and truncated Laplacian distributions are appropriate fits to the measurement results for power azimuth spectrum of TR‐UWB. It is seen that for distances greater than λ/2 from the authorized receiver, received signal decreases 10 dB, where λ is the wavelength of the central frequency. Finally, PDF of TR‐UWB path‐gain is described. Measurement results show that for small time windows, the densities of the path‐gain are highly non‐Gaussian. But for starting time of 10T_w or more, and window size of 2T_w or more the densities are nearly Gaussian, where T_w is the transmitted pulse duration. Copyright © 2010 John Wiley & Sons, Ltd.     

基于GaN HEMT新型负反馈结构固态宽带功率放大器的研究

The design and fabrication of an ultra-broadband power amplifier based on a Ga N HEMT, which operates in the frequency range from 3 to 8 GHz, is presented in this paper. A TGF2023-02 Ga N HEMT chip from Tri Quint is adopted and modeled. A novel negative feedback structure is applied in the circuit. The measured results show that the amplifier module has a wide range frequency response that is almost consistent with those of simulation at frequencies from 3 to 6.5 GHz. The measured power gain is greater than 7 d B between 3 and 6.5 GHz.The saturated output power is 38.5 d Bm under DC bias of Vds D28 V, Vgs D 3:5 V at the frequency of 5.5 GHz.     

FVF LDO regulator with dual dynamic-load composite gain stage

A low-voltage output-capacitorless low-dropout regulator using dual dynamic-load composite gain stage for flipped voltage follower topology is presented. It also incorporates a delay discharge circuit which aims to reduce the long discharge time arising from the large capacitive load, thus achieving the overshoot time reduction and sustaining fast transient characteristic when driving low-power digital system with internal heavy capacitive load requirement. The regulator can support a minimum of 0.75 V input voltage with 0.5 V output voltage. It consumes 49.4 µA whilst maintaining the stability for a capacitance load range from 470 pF to 10 nF. For a current load transient from 0 to 10 mA with 200 ps edge time, the settling time is 0.38 µs for the load capacitance of 3 nF. The obtained transient figure-of-merit is 0.42 mV. This transient metric outperforms the representative prior-art reported works.     

Structural modification of semiconductor optical amplifiers for wavelength division multiplexing systems

In this paper, the semiconductor optical amplifier is analyzed for in-line and pre-amplifier for wavelength division multiplexing (WDM) transmission having minimum crosstalk and power penalty with sufficient gain. It is evaluated that the cross gain saturation of the SOA can be reduced by settling crosstalk at lower level and also minimizing the power penalty by slight increase in the confinement factor. At an optimal confinement factor of 0.41069, high amplification is obtained up to saturation power of 20.804 mW. For this confinement factor, low crosstalk of −9.63 dB and amplified spontaneous emission noise power of 119.4 μW are obtained for −15 dBm input signal. It has been demonstrated for the first time that twenty channels at 10 Gb/s WDM can transmit up to 5600 km by use of this optimization. In this, cascading of in-line SOA is done at the span of 70 km for return zero differential phase shift keying modulation format with the channel spacing of 100 GHz. The optical power spectrum and clear eye are observed at the transmission distance of 4340 and 5600 km in RZ-DPSK system. The bit error rate for all channels increases more than 10⁻¹⁰ with the increase in launched input power.     

一种高速低压用增益增强型运算跨导放大器设计

设计了一种全差分增益增强CMOS运算跨导放大器,用于12位100 MHz采样频率的流水线A/D转换器。详细分析了辅助运放产生的零极点对,优化了建立时间。电路采用中芯国际（SMIC）0.18μm混合信号CMOS工艺设计, 1.8 V电压供电。仿真结果表明,运算放大器的开环增益为102 dB,在3pF负载电容下单位增益带宽为1.27G,精度为0.01%时的建立时间为4.3 ns。     

AC analysis of nanoscale GME-TRC MOSFET for microwave and RF applications

In this paper, the RF performance for Gate Material Engineered-Trapezoidal Recessed Channel (GME-TRC) MOSFET has been investigated and the results so obtained are compared with Trapezoidal Recessed Channel (TRC) MOSFET and Rectangle Recessed Channel (RRC) MOSFET, using device simulators; ATLAS and DEVEDIT. Further, the impact of technology parameter variations in terms of negative junction depth (NJD), gate metal workfunction difference, substrate doping (N_A) and corner angle, on GME-TRC MOSFET has also been evaluated. The simulation study shows the increase in transconductance and decrease in parasitic capacitance, which further contributes towards a significant improvement in cut-off frequency (f_t) in GME-TRC MOSFET as compared to conventional TRC and RRC MOSFETs. Moreover, the significant enhancement in maximum available power gain (Gma), maximum transducer power gain (G_MT), maximum unilateral power gain (MUG), maximum frequency of oscillation (f_MAX) and stern stability factor (K) have also been observed for GME-TRC MOSFET due to reduced short channel effects (SCEs) and enhanced current driving capabilities. Further, the experimental data for grooved gate MOSFET has also been verified with the simulated data and a good agreement between their results is obtained.     

A hybrid NMOS/PMOS capacitor-less low-dropout regulator with fast transient response for SoC applications

In this paper, a new architecture of a fully integrated low-dropout voltage regulator (LDO) is presented. It is composed of hybrid architecture of NMOS/PMOS power transistors to relax stability requirements and enhance the transient response of the system. The LDO is capable of producing a stable output voltage of 1.1 V from 1.3 V single supply with recovery settling time about 680 nsec. It can supply current from 10 µA to 100 mA consuming quiescent current of 20.5 µA and 95 µA, respectively. It supports load capacitance from 0 to 50 pF with phase margin that increases from 43° at low load (10 µA) to 74° at high load (100 mA) and power supply rejection ratio (PSRR) less than −20 dB up to 100 kHz. The proposed LDO is designed in 130 nm CMOS technology and occupies an area of 0.11 mm². Post layout simulations show better performance compared with other reported techniques.