ARM多点源诱偏仿真试验的线阵实现方法

研究了ARM的对抗技术及有源诱偏原理,提出了仿真试验系统在不具备面天线阵的情况下,利用线天线阵进行内场仿真试验的实现方法。研究了反辐射导弹两点源诱偏导引信号模型,分析了两点源诱偏和多点源诱偏线阵实现方法的联系与区别,建立了在线阵上利用两点源诱偏实现多点源诱偏的方案,并分析了试验中的关键问题。利用仿真对所提出的方法进行了验证,证实了该方法的可行性。     

Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor

A novel approach for using an embedded processor to aid in deterministic testing of the other components of a system-on-a-chip (SOC) is presented. The tester loads a program along with compressed test data into the processor's on-chip memory. The processor executes the program which decompresses the test data and applies it to scan chains in the other components of the SOC to test them. The program itself is very simple and compact, and the decompression is done very rapidly, hence this approach reduces both the amount of data that must be stored on the tester and reduces the test time. Moreover, it enables at-speed scan shifting even with a slow tester (i.e., a tester whose maximum clock rate is slower than the SOC's normal operating clock rate). A procedure is described for converting a set of test cubes (i.e., test vectors where the unspecified inputs are left as X's) into a compressed form. A program that can be run on an embedded processor is then given for decompressing the test cubes and applying them to scan chains on the chip. Experimental results indicate a significant amount of compression can be achieved resulting in less data that must be stored on the tester (i.e., smaller tester memory requirement) and less time to transfer the test data from the tester to the chip.     

Test generation for specification test of analog circuits using efficient test response observation methods

In this paper, a new automated test generation methodology for specification testing of analog circuits using test point selection and efficient analog test response waveform capture methods for enhancing the test accuracy is proposed. The proposed approach co-optimizes the construction of a multi-tone sinusoidal test stimulus and the selection of the best set of test response observation points. For embedded analog circuits, it uses a subsampling-based digitization method compatible with IEEE 1149.1 to accurately digitize the analog test response waveforms. The proposed specification approach uses ‘alternate test’ framework, in which the specifications of the analog circuit-under-test are computed (predicted) using statistical regression models that are constructed based on process variations and corresponding variations of test responses captured from different test observation points. The test generation process and the test point selection process aim to maximize the accuracy of specification prediction. Experimental results validating the proposed specification test approach are presented.     

Multiple Scan Chain Design for Two-Pattern Testing

Non-standard fault models often require the application of two-pattern testing. A fully-automated approach for generating a multiple scan chain-based architecture is presented so that two-pattern test sets generated for the combinational core can be applied to the sequential circuit. Test time and area overhead constraints are considered.     

Features of a Scan and Clock Resource chip for providing access to board-level test functions

The architecture and some of the specific features of a Scan and Clock Resource (SCR) chip are described. This chip is currently being used in a high-end workstation product to provide access to the testability features of the individual chips and/or printed circuit boards. Using a board-level controller to gain access to the testability features of system components and interfacing the controller to a diagnostics processor (or external tester) is emerging as a common strategy for designing testable digital systems. Based upon experience gained from such an application, controller features that are deemed useful are discussed.This paper is an enhanced version of the author's earlier paper titled Towards a Standard Approach for Controlling Board-Level Test Functions, presented at the IEEE International Test Conference, ITC'90, Washington D.C., September 1990.     

Reducing Average and Peak Test Power Through Scan Chain Modification

Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test vector loading techniques result in frequent transitions in the scan chain, which in turn reflect into significant levels of circuit switching unnecessarily. Judicious utilization of logic in the scan chain can help reduce transitions while loading the test vector needed. The transitions embedded in both test stimuli and the responses are handled through scan chain modifications consisting of logic gate insertion between scan cells as well as inversion of capture paths. No performance degradation ensues as these modifications have no impact on functional execution. To reduce average and peak power, we herein propose computationally efficient schemes that identify the location and the type of logic to be inserted. The experimental results confirm the significant reductions in test power possible under the proposed scheme.     

Avoiding linear dependencies in LFSR test pattern generators

Linear Feedback Shift Registers (LFSRs) constitute a very efficient mechanism for generating pseudoexhaustive or pseudo-random test sets for the built-in self-testing of digital circuits. However, a well-known problem with the use of LFSRs is the occurrence of linear dependencies in the generated patterns. In this paper, we show for the first time that the amount of linear dependencies can be controlled by selecting appropriate characteristic polynomials and reordering the LFSR cells. We identify two classes of such polynomials which, by appropriate LFSR cell ordering, guarantee that a large ratio of linear dependencies cannot occur. Experimental results show significant enhancements on the fault coverage for pseudo-random testing and support the theoretical relation between minimization of linear dependencies and effective fault coverage.This work was partially supported by NSF grant MIP-9409905, a 1993–94 ACM/IEEE Design Automation Scholarship and a grant from Nissan Corporation. A preliminary version of this work appeared in A Class of Good Characteristic Polynomials for LFSR Test Pattern Generators, in Proc. of IEEE International Conference on Computer Design, Oct. 1994, pp. 292–295, where it received the ICCD'94 Best Paper Award.     

软件测试模型及其改进方案

当前软件企业面临着用户需求日益复杂、软件产品架构日益扩大等问题。这些问题向软件测试提出了更高的要求。该文对传统测试模型进行了介绍和分析,在分析V模型、W模型以及X模型等软件测试模型的特点和局限性的基础上．利用增加单元测试准则的方法对软件测试模型进行了改进。基于以上工作,以CMMI的标准为指导对软件测试流程以及测试模型的改进提出了思路和方法。     

基于线性递减系数粒子群优化算法的组卷实现

为了避免目前常用的组卷算法组卷时间长、程序结构复杂、收敛速度慢等缺陷,提出基于线性递减系数粒子群优化算法的组卷策略。通过调整惯性系数,使得步长较小,惯性权系数的变化幅度小,这种减小趋势较为缓慢的方法能够避免陷入局部最优。并对数学模型以及线性递减惯性权系数进行了理论设计,同时通过编程实现了该算法。测试结果表明加入线性递减系数后运算迭代次数明显减少,证明加入线性递减系数后的组卷策略收敛性好,能够高效准确地按照一定的预期条件进行组卷,符合预期要求。     

某型试验指挥系统的软件测试方法

随着军用软件在军事装备中的规模、比例的不断增大,军用软件对武器装备作战使用效能的发挥起着举足轻重的作用,从某型试验指挥系统软件设计原理和功能需求入手,设计了具体的测试方法,经过测试,保证了该型试验指挥系统软件的长期稳定可靠运行,对现在军用软件的测试方法的改进有一定的借鉴作用。     

Testing for Bounded Faults in RAMs

We study the class of bounded faults in random-access memories;these are faults that involve a bounded number of cells. This is avery general class of memory faults that includes, for example, theusual stuck-at, coupling, and pattern-sensitive faults, but also manyother types of faults. Some bounded faults are known to requiredeterministic tests of length proportional to n log2 n, where nis the total number of memory cells. The main result of this paper isthat, for any bounded fault satisfying certain very mild conditions,the random test length required for a given level of confidence isalways O(n).     

Techniques for estimating test length under random test

When a circuit is tested using random or pseudorandom patterns, it is essential to determine the amount of time (test length) required to test it adequately. We present a methodology for predicting different statistics of random pattern test length. While earlier methods allowed estimation only of upper bounds of test length and only for exhaustive fault coverage, the technique presented here is capable of providing estimates of all statistics of interest (including expected value and variance) for all coverage specifications.Our methodology is based on sampling models developed for fault coverage estimation [1]. Test length is viewed as awaiting time on fault coverage. Based on this relation we derive the distribution of test length as a function of fault coverage. Methods of approximating expected value and variance of test length are presented. Accuracy of these approximations can be controlled by the user. A practical technique for predicting expected test length is developed. This technique is based on clustering faults into equal detectability subsets. A simple and effective algorithm for fault clustering is also presented. The sampling model is applied to each cluster independently and the results are then aggregated to yield test lengths for the whole circuit. Results of experiments with several circuits (both ISCAS '85 benchmarks and other practical circuits) are also provided.This work was done while the author was with the Department of Electrical Engineering, Southern Illinois University, Carbondale, IL 62901.     

Economic modeling of board test strategies

A long and deep recession, coupled with continuous competitive pressure to reduce costs, is forcing many companies to review their test strategies. Testing costs have become a more significant proportion of the overall manufacturing cost even though manufacturing yields have increased dramatically over the past ten or twelve years. This causes attention to be focused on testing costs as a key source of cost reduction. The increased use of DFT and the integration of design and test are very positive moves towards controlling testing costs but other methods employed can often backfire. The increased use of low priced testers is one such method. The pressure to reduce costs, higher process yields and exhortations that testing adds no value can lead the test engineering manager to take the cheap route. In reality this can often turn out to be an expensive decision. The only way to avoid expensive mistakes is to perform an economic analysis of the alternative courses of action. In most cases this is done, but not always in the right manner or with the necessary amount of detail to make the comparisons meaningful. This article discusses the need for effective cost analysis of test strategies and highlights some of the pitfalls.     

Generation of Primary Input Blocking Pattern for Power Minimization during Scan Testing

In this paper we propose a new approach to generate a primary input blocking pattern for applying to the primary inputs during shift cycle such that the switching activity occurred in the combinational part of the circuit under test can be suppressed as much as possible. The primary input blocking technique suppresses transitions of gates in the combinational part during scan by assigning controlling values to one of the gates' inputs. However, simultaneously assigning controlling values to the gates may result in conflicts in the setting of binary values on the primary inputs. Instead of the heuristics based on fanout in other approaches, we use the impact function which is based on transition density to determine the priorities of the gates to be blocked. Experiments performed on the ISCAS 89 benchmark circuits show that the proposed approach can always produce better results than the existing approaches.

Fault-based ATPG for linear analog circuits with minimal size multifrequency test sets

An automatic test pattern generation (ATPG) procedure for linear analog circuits is presented in this work. A fault-based multifrequency test approach is considered. The procedure selects a minimal set of test measures and generates the minimal set of frequency tests which guarantee maximum fault coverage and, if required, maximal fault diagnosis, of circuit AC hard/soft faults. The procedure is most suitable for linear time-invariant circuits which present significant frequency-dependent fault effects.For test generation, the approach is applicable once parametric tests have determined DC behaviour. The advantage of this procedure with respect to previous works is that it guarantees a minimal size test set. For fault diagnosis, a fault dictionary containing a signature of the effects of each fault in the frequency domain is used. Fault location and fault identification can be achieved without the need of analog test points, and just in-circuit checkers with an observable go/no-go digital output are required for diagnosis.The procedure is exemplified for the case of an analog biquadratic filter. Three different self-test approaches for this circuit are considered. For each self-test strategy, a set of several test measures is possible. The procedure selects, in each case, the minimal set of test measures and the minimal set of frequency tests which guarantee maximum fault coverage and maximal diagnosis. With this, the self-test approaches are compared in terms of the fault coverage and the fault diagnosability achieved.This work is part of AMATIST ESPRIT-III Basic Research Project, funded by CEC under contract #8820.     

面向基于漏洞检测的安全产品优化测试方案研究

传统面向基于漏洞检测的安全产品的测试方法虽然涵盖了几乎全部的功能和性能要点,但却存在着成本高、周期长等不足,严重滞后了此类安全产品的上线部署。本文详细介绍了一种新型的测试方案,在严格遵从测试原则的前提下,从中挑选了准确性、完备性和及时性、方便性、可用性、可靠性5个关键内容进行优化性测试;不仅精简了此类产品的测试内容、缩短了测试周期、降低了测试费用,还可以推广至其他类似的应用层安全产品测试工作。     

基于双模式LFSR的低功耗BIST结构

传统的BIST结构中,由于LFSR产生大量的测试矢量在测试过程中消耗了大量的功耗。为了减少测试矢量的数目而不影响故障覆盖率,我们提出了一种新的基于双模式LFSR的低功耗BIST结构。首先介绍了功耗模型和延迟模型的基础知识,然后给出了用于生成双模式LFSR的矩阵,并介绍了解矩阵方程式的算法。随后说明了新的BIST结构和用于矢量分组的模拟退火算法。最后,基于Benchmark电路的实验证明这种结构可以在不降低故障覆盖率的同时减少70％的功耗。     

Boundary scan test,test methodology,and fault modeling

The test technique called boundary scan test (BST) offers new opportunities in testing but confronts users with new problems too. The implementation of BST in a chip has become an IEEE standard and users on board level are the next group to begin thinking about using the new possibilities. This article addresses some of the questions about changes in board-level testing and fault diagnosis. The fault model itself is also affected by using BST. Trivial items are extended with more sophisticated details in order to complete the fault model. Finally, BST appears to be a test technique that offers a high degree of detectability on board level, but for diagnosis, some additional effort has to be made.     

基于WATIR的WEB自动化回归测试框架

由于在迭代开发模式中需要执行大量的回归测试,针对其测试项目重复率高的特点,提出了一种Web自动化回归测试框架来改进全手工的作业。通过对现有测试工具和测试脚本技术的对比研究,选择Watir作为驱动程序,设计了关键字驱动机制的测试框架WATF。实际使用WATF进行回归测试,和人工测试相比提高了75％的测试效率,大幅减少在回归测试上的人力投入。     

基于支持向量机的线性轮廓图控制方法研究

在质量控制的应用中,一些过程或产品质量可以由响应变量与多个解释变量之间的关系（轮廓图）更好地表征.提出了一种基于支持向量机的控制方法来检测第二阶段中线性轮廓图的变化.通过计算机仿真模拟实验与其他几种传统方法以及神经网络的方法做比较发现,仿真得出所提出的控制方法在检测截距和斜率的变化方面表现优异.