ARM多点源诱偏仿真试验的线阵实现方法

研究了ARM的对抗技术及有源诱偏原理,提出了仿真试验系统在不具备面天线阵的情况下,利用线天线阵进行内场仿真试验的实现方法。研究了反辐射导弹两点源诱偏导引信号模型,分析了两点源诱偏和多点源诱偏线阵实现方法的联系与区别,建立了在线阵上利用两点源诱偏实现多点源诱偏的方案,并分析了试验中的关键问题。利用仿真对所提出的方法进行了验证,证实了该方法的可行性。     

Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor

A novel approach for using an embedded processor to aid in deterministic testing of the other components of a system-on-a-chip (SOC) is presented. The tester loads a program along with compressed test data into the processor's on-chip memory. The processor executes the program which decompresses the test data and applies it to scan chains in the other components of the SOC to test them. The program itself is very simple and compact, and the decompression is done very rapidly, hence this approach reduces both the amount of data that must be stored on the tester and reduces the test time. Moreover, it enables at-speed scan shifting even with a slow tester (i.e., a tester whose maximum clock rate is slower than the SOC's normal operating clock rate). A procedure is described for converting a set of test cubes (i.e., test vectors where the unspecified inputs are left as X's) into a compressed form. A program that can be run on an embedded processor is then given for decompressing the test cubes and applying them to scan chains on the chip. Experimental results indicate a significant amount of compression can be achieved resulting in less data that must be stored on the tester (i.e., smaller tester memory requirement) and less time to transfer the test data from the tester to the chip.     

Test generation for specification test of analog circuits using efficient test response observation methods

In this paper, a new automated test generation methodology for specification testing of analog circuits using test point selection and efficient analog test response waveform capture methods for enhancing the test accuracy is proposed. The proposed approach co-optimizes the construction of a multi-tone sinusoidal test stimulus and the selection of the best set of test response observation points. For embedded analog circuits, it uses a subsampling-based digitization method compatible with IEEE 1149.1 to accurately digitize the analog test response waveforms. The proposed specification approach uses ‘alternate test’ framework, in which the specifications of the analog circuit-under-test are computed (predicted) using statistical regression models that are constructed based on process variations and corresponding variations of test responses captured from different test observation points. The test generation process and the test point selection process aim to maximize the accuracy of specification prediction. Experimental results validating the proposed specification test approach are presented.     

Polytype target coverage scheme for heterogeneous wireless sensor networks using linear programming

Sensing coverage is one of fundamental problems in wireless sensor networks. In this paper, we investigate the polytype target coverage problem in heterogeneous wireless sensor networks where each sensor is equipped with multiple sensing units and each type of sensing unit can sense an attribute of multiple targets. How to schedule multiple sensing units of a sensor to cover multiple targets becomes a new challenging problem. This problem is formulated as an integer linear programming problem for maximizing the network lifetime. We propose a novel energy‐efficient target coverage algorithm to solve this problem based on clustering architecture. Being aware of the coverage capability and residual energy of sensor nodes, the clusterhead node in each cluster schedules the appropriate sensing units of sensor nodes that are in the active status to cover multiple targets in an optimal way. Extensive simulations have been carried out to validate the effectiveness of the proposed scheme. Copyright © 2012 John Wiley & Sons, Ltd.     

Multiple Scan Chain Design for Two-Pattern Testing

Non-standard fault models often require the application of two-pattern testing. A fully-automated approach for generating a multiple scan chain-based architecture is presented so that two-pattern test sets generated for the combinational core can be applied to the sequential circuit. Test time and area overhead constraints are considered.     

Multiple multicast for a half‐duplex butterfly network: a deterministic approach

We investigate the multicast throughput of a butterfly network, which may be a promising topology for network coding application in next‐generation wireless communication systems. The butterfly network consists of two sources, two destinations and a relay, where each destination requires decoding of data from two independent sources. It is assumed that all the nodes are operated in half‐duplex mode. Each end‐to‐end packet transmission should be completed in a two‐phase period. In order to reduce processing complexity and multiple interference, other nodes should keep silent when the relay transmits a signal. By using Avestimehr, Diggavi and Tse's deterministic model, we first introduce a deterministic butterfly network and demonstrate that its maximal multicast rate region can be achieved by employing a network coding policy. According to the results obtained in deterministic case, we then put forward a near‐optimal design on the transmitted signal and decoding scheme for Gaussian scenarios based on a nested lattice code. It is proved that the gap between the achievable rate region and an outer bound is less than 3bits/s/Hz, which is not related to the signal‐to‐noise ratio. That is, the proposed scheme can approach the maximal multicast throughput. Finally, numerical results demonstrate that the gap is robust to both channel gains and time division of the two phases. Copyright © 2014 John Wiley & Sons, Ltd.     

Features of a Scan and Clock Resource chip for providing access to board-level test functions

The architecture and some of the specific features of a Scan and Clock Resource (SCR) chip are described. This chip is currently being used in a high-end workstation product to provide access to the testability features of the individual chips and/or printed circuit boards. Using a board-level controller to gain access to the testability features of system components and interfacing the controller to a diagnostics processor (or external tester) is emerging as a common strategy for designing testable digital systems. Based upon experience gained from such an application, controller features that are deemed useful are discussed.This paper is an enhanced version of the author's earlier paper titled Towards a Standard Approach for Controlling Board-Level Test Functions, presented at the IEEE International Test Conference, ITC'90, Washington D.C., September 1990.     

A novel QO-STBC scheme with linear decoding

A new quasi-orthogonal space-time block code(QO-STBC)scheme,based on eigen value decomposition(EVD),is explored in this paper.The new scheme can significantly reduce the QO-STBC decoding complexity at receiver and achieves better bit-error rate(BER)performance as well.With EVD manipulations,the detection matrix and the channel matrix can be redefined to remove all interference terms which come from other antennas,and therefore the conventional maximum likelihood(ML)decoding method with less complexity can b...     

Reducing Average and Peak Test Power Through Scan Chain Modification

Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test vector loading techniques result in frequent transitions in the scan chain, which in turn reflect into significant levels of circuit switching unnecessarily. Judicious utilization of logic in the scan chain can help reduce transitions while loading the test vector needed. The transitions embedded in both test stimuli and the responses are handled through scan chain modifications consisting of logic gate insertion between scan cells as well as inversion of capture paths. No performance degradation ensues as these modifications have no impact on functional execution. To reduce average and peak power, we herein propose computationally efficient schemes that identify the location and the type of logic to be inserted. The experimental results confirm the significant reductions in test power possible under the proposed scheme.     

Low-voltage linear transconductor and a memory current using the MIFGMOS Transistor

The aim of this article is to probe the advantages that the Multi-Input Floating Gate MOS (MIFGMOS) transistor has versus the conventional MOSFET transistor in order to design analogue circuits with low-voltage operation and good linearity. To show this, the design and implementation of both a voltage to current converter (VIC) cell and a memory current cell (MIC) using MIFGMOS transistors is presented. The development is based on mathematical and simulation analysis as well as experimental results. Both cells present good performance and linearity according to theoretical analysis with a supply voltage of 1.7 V and a power consumption of about 20 μW, despite the long channel technology. These characteristics could be very important in analogue and mixed signal applications requiring low supply voltage and low power consumption. The cells presented here can be part of a sample and hold circuit operating in current mode, but applications are not restricted. Additionally, a comparison between simulation and experimental results obtained when we tested five 3-input MIFGMOS transistors are included to show their properties and behavior.     

Avoiding linear dependencies in LFSR test pattern generators

Linear Feedback Shift Registers (LFSRs) constitute a very efficient mechanism for generating pseudoexhaustive or pseudo-random test sets for the built-in self-testing of digital circuits. However, a well-known problem with the use of LFSRs is the occurrence of linear dependencies in the generated patterns. In this paper, we show for the first time that the amount of linear dependencies can be controlled by selecting appropriate characteristic polynomials and reordering the LFSR cells. We identify two classes of such polynomials which, by appropriate LFSR cell ordering, guarantee that a large ratio of linear dependencies cannot occur. Experimental results show significant enhancements on the fault coverage for pseudo-random testing and support the theoretical relation between minimization of linear dependencies and effective fault coverage.This work was partially supported by NSF grant MIP-9409905, a 1993–94 ACM/IEEE Design Automation Scholarship and a grant from Nissan Corporation. A preliminary version of this work appeared in A Class of Good Characteristic Polynomials for LFSR Test Pattern Generators, in Proc. of IEEE International Conference on Computer Design, Oct. 1994, pp. 292–295, where it received the ICCD'94 Best Paper Award.     

一种可应用于并发在线测试的扫描单元设计

航天等领域对集成电路可靠性要求较高,要求其具有在线测试功能,以便及时发现故障,减少损失。结合现有扫描设计方法,设计了一种改进的扫描单元结构。将该扫描单元应用于时序电路后,能够在电路工作的同时进行测试;通过灵活的时钟选择机制,方便地控制电路进行非并发和并发测试。仿真实验表明,应用本文提出的扫描单元,时序电路能够在增加一定硬件冗余的条件下实现在线测试,时间开销较小,有较高的可靠性和一定的容错能力,实用性强。     

软件测试模型及其改进方案

当前软件企业面临着用户需求日益复杂、软件产品架构日益扩大等问题。这些问题向软件测试提出了更高的要求。该文对传统测试模型进行了介绍和分析,在分析V模型、W模型以及X模型等软件测试模型的特点和局限性的基础上．利用增加单元测试准则的方法对软件测试模型进行了改进。基于以上工作,以CMMI的标准为指导对软件测试流程以及测试模型的改进提出了思路和方法。     

基于线性递减系数粒子群优化算法的组卷实现

为了避免目前常用的组卷算法组卷时间长、程序结构复杂、收敛速度慢等缺陷,提出基于线性递减系数粒子群优化算法的组卷策略。通过调整惯性系数,使得步长较小,惯性权系数的变化幅度小,这种减小趋势较为缓慢的方法能够避免陷入局部最优。并对数学模型以及线性递减惯性权系数进行了理论设计,同时通过编程实现了该算法。测试结果表明加入线性递减系数后运算迭代次数明显减少,证明加入线性递减系数后的组卷策略收敛性好,能够高效准确地按照一定的预期条件进行组卷,符合预期要求。     

Testing for Bounded Faults in RAMs

We study the class of bounded faults in random-access memories;these are faults that involve a bounded number of cells. This is avery general class of memory faults that includes, for example, theusual stuck-at, coupling, and pattern-sensitive faults, but also manyother types of faults. Some bounded faults are known to requiredeterministic tests of length proportional to n log2 n, where nis the total number of memory cells. The main result of this paper isthat, for any bounded fault satisfying certain very mild conditions,the random test length required for a given level of confidence isalways O(n).     

某型试验指挥系统的软件测试方法

随着军用软件在军事装备中的规模、比例的不断增大,军用软件对武器装备作战使用效能的发挥起着举足轻重的作用,从某型试验指挥系统软件设计原理和功能需求入手,设计了具体的测试方法,经过测试,保证了该型试验指挥系统软件的长期稳定可靠运行,对现在军用软件的测试方法的改进有一定的借鉴作用。     

Techniques for estimating test length under random test

When a circuit is tested using random or pseudorandom patterns, it is essential to determine the amount of time (test length) required to test it adequately. We present a methodology for predicting different statistics of random pattern test length. While earlier methods allowed estimation only of upper bounds of test length and only for exhaustive fault coverage, the technique presented here is capable of providing estimates of all statistics of interest (including expected value and variance) for all coverage specifications.Our methodology is based on sampling models developed for fault coverage estimation [1]. Test length is viewed as awaiting time on fault coverage. Based on this relation we derive the distribution of test length as a function of fault coverage. Methods of approximating expected value and variance of test length are presented. Accuracy of these approximations can be controlled by the user. A practical technique for predicting expected test length is developed. This technique is based on clustering faults into equal detectability subsets. A simple and effective algorithm for fault clustering is also presented. The sampling model is applied to each cluster independently and the results are then aggregated to yield test lengths for the whole circuit. Results of experiments with several circuits (both ISCAS '85 benchmarks and other practical circuits) are also provided.This work was done while the author was with the Department of Electrical Engineering, Southern Illinois University, Carbondale, IL 62901.     

测试设备的面向用户报表方案设计

一些测试设备的测试数据报表格式固定,与用户的文档规范不相符,不便于用户直接使用。介绍了一种面向用户的测试设备报表方案,测试设备软件用Visual C＋＋开发,通过ActiveX数据对象从数据库中读取存储的测试数据后,利用Microsoft Office Word模板生成Word报表。在测试数据数量确定的情况下,用户通过修改Word模板可定制报表格式,提高了系统开发效率,便于用户使用。     

Economic modeling of board test strategies

A long and deep recession, coupled with continuous competitive pressure to reduce costs, is forcing many companies to review their test strategies. Testing costs have become a more significant proportion of the overall manufacturing cost even though manufacturing yields have increased dramatically over the past ten or twelve years. This causes attention to be focused on testing costs as a key source of cost reduction. The increased use of DFT and the integration of design and test are very positive moves towards controlling testing costs but other methods employed can often backfire. The increased use of low priced testers is one such method. The pressure to reduce costs, higher process yields and exhortations that testing adds no value can lead the test engineering manager to take the cheap route. In reality this can often turn out to be an expensive decision. The only way to avoid expensive mistakes is to perform an economic analysis of the alternative courses of action. In most cases this is done, but not always in the right manner or with the necessary amount of detail to make the comparisons meaningful. This article discusses the need for effective cost analysis of test strategies and highlights some of the pitfalls.     

Generation of Primary Input Blocking Pattern for Power Minimization during Scan Testing

In this paper we propose a new approach to generate a primary input blocking pattern for applying to the primary inputs during shift cycle such that the switching activity occurred in the combinational part of the circuit under test can be suppressed as much as possible. The primary input blocking technique suppresses transitions of gates in the combinational part during scan by assigning controlling values to one of the gates' inputs. However, simultaneously assigning controlling values to the gates may result in conflicts in the setting of binary values on the primary inputs. Instead of the heuristics based on fanout in other approaches, we use the impact function which is based on transition density to determine the priorities of the gates to be blocked. Experiments performed on the ISCAS 89 benchmark circuits show that the proposed approach can always produce better results than the existing approaches.