大功率LED驱动谐振电路设计

通过分析对比大功率LED驱动电路的拓扑结构,采用LLC谐振拓扑,提出了一种适用于宽范围恒流输出的设计方法,并进行了效率优化。LLC半桥谐振变换器可在全负载范围内实现功率开关管的零电压开通（ZVS）和整流二极管的零电流关断（ZCS）,以此减小开关损耗。并且采用基波近似方法分析LLC谐振变换器,通过交流等效电路,导出了归一化直流增益曲线,讨论了半桥LLC的三种主要工作方式,以及对应的三个工作区间,分析了每个工作区间的特点和应用场合。     

一种自驱动型LLC半桥谐振变换器的研究

在三谐振LLC变换器基础上,简化控制电路,提出了一种新型的LLC型自驱动半桥谐振变换器拓扑,并分析了该变换器的工作原理。由于它与传统谐振变换器相比,省略了昂贵的半桥驱动芯片和复杂的变频控制策略,实现了全负载范围内零电压开关,提高了变换器的效率、可靠性及功率密度,降低了成本。所以该拓扑十分适合应用于中间母线式变换器中,文中详细讨论了其参数设计。     

Analogue control of the slew-rate in LIN bus digital transitions using translinear circuits

A novel technique to control the LIN (Local Interconnect Network) bus slew-rate transitions in automotive environment, where large fluctuations of the battery voltage are present, is reported. A bipolar translinear circuit generates a non-linear current that is used to modulate a MOS relaxation oscillator, producing a clock frequency that delivers a constant number of pulses during the LIN bus digital signal transition. This frequency modulated clock when applied to a digitally controlled analogue wave-shape driver results in a LIN bus digital transition with a slew-rate that is constant and independent of the car battery voltage. Experimental results measured in an IC implemented in a BiCMOS process showed that constant slew-rate transition of 1?±?2% V/??s is obtained for battery voltages varying from 6 to 40 V, over the temperature range of ?40 to 150°C.     

集成式石英谐振加速度计倍频电路设计

谐振式加速度计可以将加速度转换为频率信号,在导航、姿态控制等加速度计的应用领域,采集信号需要限定在较短时间内,为了满足应用的要求,基于一种单基片集成式石英谐振器,通过现场可编程门阵列(FPGA)实现了一种针对集成式石英谐振加速度计的倍频电路设计方案,包括时钟自适应模块和锁相环。时钟自适应模块根据当前输入信号产生锁相环基准时钟并将输入信号进行倍频。离心机加速度测试结果表明,当测量时间由1 s缩短为0.125 s时,传感器标度因数为3 173 Hz/g(g=9.8 m/s²),线性相关系数R²=0.999 32,与未倍频时相比,标度因数与线性度基本保持不变,所设计的倍频电路可应用于石英谐振加速度计的信号处理及数据采集系统中。     

A sample-and-hold current measurement integrated circuit for neural recording

This paper describes a new differential sample-and-hold technique of current measurement for neural probing. The design utilizes bottom plate sampling (BPS) and T-transmission switches to mitigate signal coupling and a differential sample-and-hold technique to reduce charge injection and clock feed through. The circuit was fabricated in a 0.35?µm CMOS process and tested using different input loads to model the electrochemical properties of the microelectrode. Test results matched closely with the simulation results, proving that the concept of the sample-and-hold current measurement circuit is valid for neural probing.     

一种实用型直流电机控制电路的设计

介绍了由半桥驱动电路以及转向控制电路构成的一种新型、结构简单、调试方便、实用的直流电机控制电路的实现方法,并阐述了电路的组成以及设计过程。实践证明,该套直流电机控制电路能克服传统的H桥控制电路中结构复杂、死区时间不易控制的问题,特别在大功率电机的控制方面该系统具有比传统H桥控制电路更优良的工作性能。     

Design and analysis of an SLPT-based CCFL driver

In this paper, a single-layer piezoelectric-transformer (SLPT)-based driver is realized for driving a cold-cathode fluorescent lamp (CCFL). First, a half-bridge resonant inverter is adopted for driving the SLPT and the CCFL to achieve zero-voltage-switching (ZVS) effect. In addition, a PQ-plane-design-oriented approach is presented for determining the power circuit parameters. Second, a feedback controller is proposed to match the power circuit control requirement. The feedback controller provides the proper switching frequency for the drive to be operated at the most efficient frequency. In addition, functions of dimming control and no-load protection are also available from the controller. Third, a small-signal model is derived and the closed-loop stability analysis is made to guarantee the stable tracking of the command signal of the controller. Finally, a hardware prototype is also constructed to verify the effectiveness of the proposed driver.     

电子镇流器中功率因数校正电路的分析及应用

IR2166/IR2167是集功率因数校正器(PFC)、镇流器和半桥驱动器为一体的新型电子镇流器驱动电路.内部的功率因数校正(PFC)电路以临界导通模式(CCM)工作,可获得高功率因数、低总谐波失真(THD)及直流电压调整.给出典型PFC控制电路的原理并进行了分析.     

开关电源全波整流输出结果的对比研究

采用脉宽调制方波作为输入信号,对全桥和半桥驱动型开关电源的输出电压、效率和纹波系数都做了对比分析和研究。并研究了不同频率、占空比以及不同范围的负载电阻对两种工作电路的影响,分析了两种电路各自的优缺点。实验结果表明,半桥驱动型开关电源,在一定程度上限制了驱动电路的最大输出功率,因此在要求大功率输出时还要采用全桥驱动电路。而且全桥工作的效果也要比半桥好,稳定性更强,可为电路的设计提供一个参考。     

40-Gb/s high-power modulator driver IC for lightwave communicationsystems

A monolithic integrated modulator driver with a data decision function for high-speed optical fiber links is presented. The integrated circuit (IC) was manufactured in a 0.2-μm gate length AlGaAs/InGaAs high electron mobility transistor technology with an f_T of 68 GHz. The modulator driver IC features differential configuration and operates up to 40 Gb/s with a clock phase margin of 210° and an output voltage swing of 2.9 V_p-p at each output. The maximum slew rate of the output signal is 200 mV/ps. The power dissipation of the circuit is 1.6 W using a single supply voltage of -5 V     

A novel versatile modulator circuit

A novel versatile modulator that can operate either as a delta modulator, a sigma-delta modulator, an amplitude modulator or a frequency modulator is presented. The proposed circuit mainly composes of a few components: which are three OTAs, one capacitor and two resistors. Among these components, two OTAs and two resistor construct a Schmitt trigger network whereas the other OTA and a capacitor compose an integrator. The advantage of this circuit is that the clock (carrier) signal employed for modulation is inherent in the circuit. No external clock is needed, only the modulating signal is required for an input. With the compactness of the circuit, it is thus suitable for IC realization. The computer simulation based on CMOS technology demonstrates that the results agree well with the theoretical analysis.     

A CMOS oscillator for radiation-hardened,low-power space electronics

This article presents the design, manufacturing and test results of an on-chip CMOS oscillator, using a ring-oscillator, VCO based architecture. The oscillator generates a configurable square waveform clock signal to be used internally or externally to the IC that integrates it, with very low area (320 transistors, 112?×?148?µm) and power overhead (975?µW). The oscillator is integrated in a mixed signal IC which has been qualified for space applications, at a commercial 250?nm process. It enables the standalone operation of the IC without external oscillator and gives the possibility to clock other components and systems. In addition, it reduces the noise interference at PCB and chip level, optimising the performance of sensitive analogue parts. It was validated by radiation tests according to ESA standards’ procedures that the oscillator's functionality and characteristics do not deteriorate with TID levels up to 1Mrad. This approach can be easily adjusted to a wide range of frequencies, while significantly reducing the cost and power budget of space qualified systems with small design effort trade-off.     

High performance white LED driver with single-wire serial-pulse digital dimming

A high performance white light emitter diode (LED) driver based on boost converter with novel single-wire serial-pulse digital dimming (SWSP) is proposed. The driver uses external serial programmed pulses and internal clock to simplify brightness control. By embedding a 5-bit digital analog converter (DAC) into the driver, wide dimming range is achieved. Moreover, a new dynamic slope compensation circuit is presented and other key circuits of the driver are optimized to get higher efficiency and fast transition response. A practical circuit is implemented with 0.6 um bipolar complementary-metal-oxide-semiconductor double-diffused-metal-oxide-semiconductor (BCD) technology. The simulation results show that the driver can provide both wide output current from 1.3 mA to 42 mA with 32-level digital dimming and higher efficiency up to 83% while it works at 1 MHz switching frequency with the input voltage variation from 2.7 V to 5.5 V.     

一种单锁存器CMOS三值D型边沿触发器设计

提出了一种只使用单个锁存器的CMOS三值D型边沿触发器设计.该电路是通过时钟信号的上升沿后产生的窄脉冲使锁存器瞬时导通完成取样求值.所提出的电路较之以往设计具有更为简单的结构,三值双轨输出时仅需24个MOS管.计算机模拟结果验证了所提出的触发器具有正确的逻辑功能、良好的瞬态特性和更低的功耗.此外,该设计结构极易推广至基值更高的多值边沿触发器的设计.     

Simple clock extraction circuit using a self sustaining monostable multivibrator output signal

A novel and simple clock extraction circuit is described. It is based on feedback around a monostable multivibrator resulting in a self sustaining clock signal. The method is suitable for application in systems which do not require the clock perfectly synchronised to the data. The circuit comprises three standard IC gates plus two delay units.     

采用ZVS条件控制的DC-DC同步整流技术

以Buck结构DC-DC为例,结合仿真波形分析了DC-DC一个开关周期4个阶段的电流电压情况,证明由ZVS条件控制MOS管的导通和断开是损耗最小的。由此提出了两种实现ZVS控制的电路拓扑：同步反馈控制以及由程序综合的控制电路。并与自适应控制进行了比较。同步反馈控制利用时钟和ZVS条件,结合MUX实现了导通和关断的理想波形。由程序综合的控制电路以PWM控制和ZVS控制为目标,并由时钟同步,实现了对驱动波形的控制。     

Voltage-pulse driven harmonic resonant rail drivers for low-power applications

We describe a new design technique for efficient harmonic resonant rail drivers. The proposed circuit implementation is coupled to a standard pulse source and uses only discrete passive components and no external dc power supply. It can thus be externally tuned to minimize the consumed power in the target IC. A new design technique based on current-fed voltage pulse-forming network theory is proposed to find the value of each discrete component for a target frequency and a given load capacitance. The proposed circuit topology can be used to generate any desired periodic 50% duty-cycle waveform by superimposing multiple harmonics of the desired waveform, however, this paper focuses on the generation of trapezoidal-wave clock signals. We have tested the driver with a capacitive load between 38.3 and 97.8 pF with clock frequency ranging between 0.8 and 15 MHz. The overall power dissipation for our second-order harmonic rail driver is 19% of fC/sub L/V/sup 2/ at 15 MHz and 97.8 pF load.     

A low-cost quadrature decoder/counter interface integrated circuit for AC induction motor server control

An AC motor server control IC which performs the quadrature decoder, counter, and bus interface function is presented in this paper. This interface IC employing TSMC 0.6µm SPTM technology has been fabricated and tested and the results indicate that its function fully works. A novel noise filter logic is included in the design which allows reliable operations in noisy environments. It also contains a quadrature decoder such that the phase lag of an external clock and the input signal can be determined.     

Architecture and Implementation of a Low-Power LVDS Output Buffer for High-Speed Applications

This paper presents a new detailed analysis of low-voltage differential signaling (LVDS) output buffers that are intended for use in high-speed integrated circuits. Three theoretically possible architectures of a LVDS output driver are discussed in rigorous detail, resulting in the recognition of the most power-conserving circuit configuration. An innovative realization of this identified low-power architecture is presented in this paper along with computer simulation results and test lab measurement data. The novel LVDS driver is designed using a unique hetero-junction bipolar transistor structure. Computer simulation results show total current consumption of 6.3 mA for the bipolar driver at a 1-GHz clock frequency while operating from a positive supply voltage between 1.7 and 3.3 V, as well as demonstrate full stage compliance with all the requirements of the IEEE 1596.3–1996 standard. The presented version of the buffer was utilized in a multiplexer/demultiplexer chip set that was fabricated in a modern 50-GHz-$f _T$SiGe technology. Test results of the LVDS output buffer taken from five different chip samples reveal high-quality output eyes with more than 0.99 UI opening and close matching between the measured parameters and simulation results.     

一种GaN半桥驱动器电平移位电路设计

GaN半桥输出点电压在死区时间为负值,给GaN功率器件栅极驱动电路信号通信带来了挑战.通过研究驱动器电平移位锁存电路工作状态与半桥功率级输出节点电压跳变、死区时间负压之间的相互影响,设计了一种新型的零静态功耗电平移位电路及其误触发消除电路.电路采用100 V BCD 0.18μm工艺设计,在输入电压100V、开关频率5...