A 0.5 V offset cancelled latch comparator in standard 0.18 μm CMOS process

This paper presents a new 0.5 V high-speed dynamic latch comparator with built-in foreground offset cancellation capability and rail-to-rail input range. Traditional latch comparators lose their speed performance in low voltage condition, especially in sub-1V applications. The proposed latch comparator utilizes a speed-up technique based on a novel boosting method to mitigate the low voltage imperfections on circuit operation. Employing a new offset cancellation technique based on the same boosting capacitors is another key idea. This enhances the accuracy of the ultra low-voltage latch comparators and relaxes the need for preamplifier stage, which is conventionally used in the low offset latch comparator. The performed Monte Carlo simulations over corners in 0.18 μm standard CMOS process show the improvement of input referred offset voltage with a standard deviation of 29.9 mV/299 μV before and after offset cancellation, respectively. The designed comparator dissipates 34 μW power from 0.5 V voltage supply while operating in 200 MHz clock frequency and detects 1 mV input difference.     

Wide tuning-range CMOS VCO based on a tunable active inductor

In this paper, a wide tuning-range CMOS voltage-controlled oscillator (VCO) with high output power using an active inductor circuit is presented. In this VCO design, the coarse frequency is achieved by tuning the integrated active inductor. The circuit has been simulated using a 0.18-µm CMOS fabrication process and presents output frequency range from 100 MHz to 2.5 GHz, resulting in a tuning range of 96%. The phase noise is –85 dBc/Hz at a 1 MHz frequency offset. The output power is from –3 dBm at 2.55 GHz to +14 dBm at 167 MHz. The active inductor power dissipation is 6.5 mW and the total power consumption is 16.27 mW when operating on a 1.8 V supply voltage. By comparing this active inductor architecture VCO with general VCO topology, the result shows that this topology, which employs the proposed active inductor, produces a better performance.     

A novel reconfigurable variable gain amplifier for a multi-mode multi-band receiver

This paper presents a novel approach for designing a reconfigurable variable gain amplifier(VGA) for the multi-mode multi-band receiver system RF front-end applications.The configuration,which is comprised of gain circuits,control circuit,DC offset cancellation circuit and mode switch circuit is proposed to save die area and power consumption with the function of multi-mode and multi-band through reusing.The VGA is realized in 0.18μm CMOS technology with 1.8 V power supply voltage providing a gain tuning...     

Inductor-less PVT robust gain switching balun LNA for multistandard applications

An inductor-less single to differential low-noise amplifier (LNA) is proposed for multistandard applications in the frequency band of 0.2–2 GHz. The proposed LNA incorporates noise cancellation and voltage shunt feedback configuration to achieve minimum noise characteristics and low power consumption. In addition to noise cancellation, trans-conductance of common-source stage is scaled to improve the noise performance. In this way, noise figure (NF) of LNA below 3 dB is achieved. An additional capacitor C_c is used to correct the gain and phase imbalance at the output. The gain switching has been enabled with a step size of 4 dB for high linearity and power efficiency. The bias point of all transistors is chosen such that the variation in g_m is not more than 10%. The proposed LNA is implemented in UMC 0.18-μm RF CMOS technology. The core area is 182 μm × 181 μm. Moreover, the LNA has better ratio of relevant performance to area. The proposed balun LNA is validated by rigorous Monte Carlo simulation. The 3σ deviation of gain and NF is less than 5%. Finally, the proposed LNA is robust to unavoidable PVT variations.     

High-temperature characterisation and analysis of leakage-current-compensated,low-power bandgap temperature sensors

This paper presents a low-power, high-performance current-feedback instrumentation amplifier (CFIA) for portable bio-potential sensing applications. Noise analysis is performed to assign an optimized current for the input stage of the amplifier. Analysis on selecting nested chopping frequencies is performed, further reducing 1/f noise and the residual offset. Enhanced power efficiency is achieved by sharing cascode branches and using a Class-AB output stage. Through these methods, a good balance between noise performance and other parameters such as output ripples and power consumption of the ripple reduction feedback loop (RRFL) is achieved. The amplifier is developed using a 1-poly 6-metal 0.18 μm CMOS process. Three gain stages with a gain-boosting input stage provide a low-frequency, open-loop gain >250 dB. When configured to a closed-loop gain of 60 dB, the amplifier achieves a noise voltage density of 18 \({\text{nV}}/\sqrt {{\text{H}}z}\) and a 1/f noise corner of 3 Hz. With a current of 75 μA and a supply voltage of 3.3 V, a CMRR of 110 dB and a PSRR of 120 dB are achieved, with an average input offset of about 6.5 μV. The amplifier achieves a state-of-art noise efficiency factor of 4.2. Practical application of the CFIA is demonstrated with an in vivo electrocardiogram detection.     

A fractional-N frequency synthesizer for single-chip UHF RFID reader

A novel fractional-N frequency synthesizer which is based on delta sigma modulator (DSM) and specialized for single-chip UHF 860-to-960 MHz band radio frequency identification (RFID) reader is proposed in this paper. The fractional-N synthesizer is implemented in 0.18 μm CMOS process. The phase noise of the fractional-N synthesizer is approximately ?109 and ?129 dBc/Hz at 200 kHz and 1 MHz offset from 900 MHz operating frequency while drawing 9.6 mA from 1.8 V power supply. The synthesizer is evaluated by implementing it in a direct conversion RF front-end. The front-end features a noise figure of 3.5 dB and an input-referred third-order intercept point of 5 dBm.     

A multi-band CMOS PLL-based frequency synthesizer for DRM/DRM+/DAB systems

A wideband frequency synthesizer is designed and fabricated in a 0.18 μm CMOS technology. It is developed for DRM/DRM+/DAB systems and is based on a programmable integer-N phase-locked loop. Instead of using several synthesizers for different bands, only one synthesizer is used, which has three separated divider paths to provide quadrature 8-phase LO signals. A wideband VCO covers a frequency band from 2.0 to 2.9 GHz, generates LO signals from 32 to 72 MHz, and from 250 to 362 MHz. In cooperation with a programmable XTAL multi-divider at the PLL input and output dividers at the PLL output, the frequency step can be altered from 1 to 25 kHz. It provides an average output phase noise of ?80 dBc/Hz at 10 kHz offset, ?95 dBc/Hz at 100 kHz offset, and ?120 dBc/Hz at 1 MHz offset for all the supported channels. The output power of the LO signals is tunable from 0 dBm to +3 dBm, and the phase of quadrature signals can also be adjusted through a varactor in the output buffer. The power consumption of the frequency synthesizer is 45 mW from a 1.8 V supply.     

CMOS CCII– based on modified dual output-OTA for high frequency applications

A negative CMOS second generation current conveyor (CMOS CCII–) based on modified dual output CMOS folded cascode operational transconductance amplifier (CMOS DO-OTA) is presented. The proposed folded cascode CMOS DO-OTA with attractive features for high frequency operation such as high output impedance, wide bandwidth, high slew rate, with low power consumption is used in the realisation. The proposed CMOS DO-OTA and CMOS CCII– with high performance parameters can be used in many high frequency applications. The proposed CMOS CCII– achieves 1.37 GHz (?3 dB BW), 1.8 ns settling time, 48 V/μs slew rate, and low power consumption around 3.25 mW for ±2.5 V supply. P-Spice simulation results are included for 0.5 μm MIETEC CMOS technology.     

A 0.7 V 6.66–9.36 GHz wide tuning range CMOS LC VCO with small chip size

The circuit designs are based on TSMC 0.18 μm CMOS standard technology model. The designed circuit uses transformer coupling technology in order to decrease chip area and increase the Q value. The switched-capacitor topology array enables the voltage-controlled oscillator (VCO) to be tuned between 6.66 and 9.36 GHz with 4.9 mW power consumption at supply voltage of 0.7 V, and the tuning range of the circuit can reach 33.7%. The measured phase noise is ?110.5 dBc/Hz at 1 MHz offset from the carrier frequency of 7.113 GHz. The output power level is about ?1.22 dBm. The figure-of-merit and figure-of-merit-with-tuning range of the VCO are about ?180.7 and ?191.25 dBc/Hz, respectively. The chip area is 0.429 mm² excluding the pads. The presented ultra-wideband VCO leads to a better performance in terms of power consumption, tuning range, chip size and output power level for low supply voltage.     

Low power FSK transmitter using all-digital PLL for IEEE 802.15.4g application

This paper presents low power frequency shift keying (FSK) transmitter using all-digital pll (ADPLL) for IEEE 802.15.4g application. In order to operate at low-power and to integrate a small die area, the ADPLL is adopted in transmitter. The phase noise of the ADPLL is improved by using a fine resolution time to digital converter (TDC) and digitally controlled oscillator (DCO). The resolution of the proposed TDC is improved by using a phase-interpolator, which divides the inverter delay time and the time amplifier, which amplifies the time difference between the reference frequency and the DCO clock. The phase noise of the proposed ADPLL is also improved by using a fine resolution DCO with an active capacitor. To cover the wide tuning range and to operate at a low-power, a two-step coarse tuning scheme with a metal insulator metal capacitor and an active inductor is used. The FSK transmitter is implemented in 0.18 μm 1-poly 6-metal CMOS technology. The die area of the transmitter including ADPLL is 2.2 mm². The power consumption of the ADPLL and transmitter is 12.43 and 22.7 mW when the output power level of the transmitter is ?1.6 dBm at 1.8 V supply voltage, respectively. The frequency resolution of the TDC is 1.25 ps. The effective DCO frequency resolution with the active capacitance and sigma-delta modulator is 2.5 Hz. The phase noise of the ADPLL output at 1.83 GHz is ?121.5 dBc/Hz with a 1 MHz offset.     

Low-power wake-up receiver with subthreshold CMOS circuits for wireless sensor networks

We developed a wake-up receiver comprised of subthreshold CMOS circuits. The proposed receiver includes an envelope detector, a high-gain baseband amplifier, a clock and data recovery (CDR) circuit, and a wake-up signal recognition circuit. The drain nonlinearity in the subthreshold region effectively detects the baseband signal with a microwave carrier. The offset cancellation method with a biasing circuit operated by the subthreshold produces a high gain of more than 100 dB for the baseband amplifier. A pulse-width modulation (PWM) CDR drastically reduces the power consumption of the receiver. A 2.4-GHz detector, a high-gain amplifier and a PWM clock recovery circuit were designed and fabricated with 0.18-μm CMOS process with one poly and six metal layers. The fabricated detector and high-gain amplifier achieved a sensitivity of ?47.2 dBm while consuming only 6.8 μW from a 1.5 V supply. The fabricated clock recovery circuit operated successfully up to 500 kbps.     

A sideband-suppressed fast-hopping synthesizer for dual-carrier OFDM UWB transceivers

A sideband-suppressed China UWB Standard synthesizer which is able to generate two carriers simultaneously is presented. An efficient synthesizing technique with a single quadrature phase-locked loop (QPLL) is proposed for fast band switching. To suppress accumulating sidebands at the outputs, a clock buffer with I/Q calibration and distortion cancellation technique is proposed. Fabricated in TSMC 0.13-μm CMOS technology and operated at 1.2 V, the synthesizer measures a maximum sideband rejection of 45 dB and a phase noise of ?105 dBc/Hz at 1-MHz offset. The synthesizer covers frequency range from 6.2 to 9.4 GHz with band switching time less than 1.4 ns.     

应用于802.11b无线局域网的低噪声高线性度的CMOS射频接收机

实现了一个单片集成、直接转换结构的2.4GHz CMOS接收机.这个正交接收机作为低成本方案应用于802.11b无线局域网系统,所处理的数据传输率为该系统的最大速率--11Mbps.基于系统设计以及低噪声高线性度考虑,设计了低噪声放大器、直接转换混频器、增益可变放大器、低通滤波器、直流失调抵消电路及其他辅助电路.该芯片采用中芯国际0.18μm 1p6m RF CMOS工艺流片.所测的接收机性能如下:噪声系数为4.1dB,高增益设置下低噪声放大器与混频器的输入三阶交调点为-7.5dBm,整个接收机的输入三阶交调点为-14dBm,相邻信道干扰抑制能力在距中心频率30MHz处达到53dBc,输出直流失调电压小于5mV.该接收机采用1.8V电源电压,I,Q两路消耗的总电流为44mA.     

Design of a new low-phase-noise millimetre-wave quadrature voltage-controlled oscillator

This paper presents a new circuit topology of millimetre-wave quadrature voltage-controlled oscillator (QVCO) using an improved Colpitts oscillator without tail bias. By employing an extra capacitance between the drain and source terminations of the transistors and optimising circuit values, a low-power and low-phase-noise (PN) oscillator is designed. For generating the output signals with 90° phase difference, a self-injection coupling network between two identical cores is used. The proposed QVCO dissipates no extra dc power for coupling, since there is no dc-path to ground for the coupled transistors and no extra noise is added to circuit. The best figure-of-merit is ?188.5, the power consumption is 14.98–15.45 mW, in a standard 180-nm CMOS technology, for 58.2 GHz center frequency from 59.3 to 59.6 GHz. The PN is ?104.86 dBc/Hz at 1-MHz offset.     

Dual-band low-phase-noise LC-QVCO using series coupling and switched biasing techniques

An LC-tank quadrature voltage-controlled oscillator (QVCO) is proposed to achieve frequency-band reconfigurability and low phase noise. In this work, phase noise contributed by the 1/f noise of coupling transistors and tail transistors is noticeably reduced when series coupling and switched biasing techniques are simultaneously adopted. The proposed QVCO was implemented in 0.25-μm triple-well CMOS process for K-PCS and WCDMA bands. Measured results showed a phase noise of ?117 dBc/Hz at an offset of 1 MHz and a phase-noise figure-of-merit of ?172 dBc/Hz while consuming 8.13 mA from a 2-V power supply.     

Current-mode phase-locked loop with constant-Q active inductor CCO and active transformer loop filter

This paper presents a current-mode phase-locked loop (PLL) with a constant-Q CMOS active inductor current-controlled oscillator (CCO) and a CMOS current-mode active-transformer loop filter. The constant-Q active inductor provides a large and swing-independent quality factor such that the phase noise of the CCO utilizing the constant-Q active inductor is comparable to that of CCO with spiral inductors. The current-mode active-transformer loop filter offers the advantage of a large and tunable inductance and low silicon consumption such that the loop bandwidth of the PLL can be made small and tunable. The PLL was designed in TSMC-0.18 μm 6-metal 1.8V CMOS technology and analyzed using SpectreRF from Cadence Design Systems with BSIM3v3 device models. The phase noise of the PLL was analyzed using Cadence’s Verilog-AMS behavioral modeling. The phase noise of the CCO with the constant-Q active inductor is ?123.1 dBc/Hz at 1 MHz frequency offset, over 10 dB better as compared with that of the CCO with conventional active inductors, and is only a few dB higher than that of the CCO with spiral inductors. The phase noise of the PLL with an active-transformer loop filter and a constant-Q CCO is ?116 dBc/Hz at 1 MHz frequency offset, nearly 20 dB lower than that of the PLL with the same active-transformer loop filter and a conventional active-inductor CCO. The lock time, power consumption, and phase noise of the PLL are 60 ns, 34 mW, and ?116 dBc/Hz at 1 MHz frequency offset, respectively. The total silicon consumption of the PLL excluding bond pads is 0.013 mm².     

一种中速高精度模拟电压比较器的设计

设计一种中速高精度模拟电压比较器,该比较器采用3级前置放大器加锁存器和数字触发电路的多级结构,应用失调校准技术消除失调,应用共源共栅结构抑制回程噪声干扰;应用数字触发电路获得高性能数字输出信号,设计采用0．35μm5VCMOS工艺实现一个输入电压2．5V、速度1MS／s、精度12位的逐次逼近型MD转换器。Hspice仿真结果表明：在5V供电电压下,速度可达20MHz,准确比较0．2mV电压,有效校准20mV输入失调,功耗约1mW。     

A novel analog/digital reconfigurable automatic gain control with a novel DC offset cancellation circuit

An analog/digital reconfigurable automatic gain control(AGC) circuit with a novel DC offset cancellation circuit for a direct-conversion receiver is presented.The AGC is analog/digital reconfigurable in order to be compatible with different baseband chips.What’s more,a novel DC offset cancellation(DCOC) circuit with an HPCF(high pass cutoff frequency) less than 10 kHz is proposed.The AGC is fabricated by a 0.18μm CMOS process.Under analog control mode,the AGC achieves a 70 dB dynamic range with a 3 dB-bandwidth larger than 60 MHz.Under digital control mode,through a 5-bit digital control word,the AGC shows a 64 dB gain control range by 2 dB each step with a gain error of less than 0.3 dB.The DC offset cancellation circuits can suppress the output DC offset voltage to be less than 1.5 mV,while the offset voltage of 40 mV is introduced into the input.The overall power consumption is less than 3.5 mA,and the die area is 800×300μm~2.     

A 4.6 GHz cascade switched biasing LC–QVCO using source-body resistor

This paper presents a 4.6 GHz LC quadrature voltage-controlled oscillator (QVCO) in which the phase noise performance is improved by two methods: cascade switched biasing (CSB) technique and source-body resistor. The CSB topology can reduce the resonator loss caused by MOSFET resistance. Meanwhile, it can maintain the benefits of conventional switched biasing technique. The source-body resistors are utilized to reduce the noise contribution of the substrate related to the cross coupled MOSFETs. The proposed QVCO has been implemented in standard 0.18 μm CMOS technology. With the two methods mentioned above, it consumes 4.9 mW under 1 V voltage supply and achieves a phase noise of ?120.3 dBc/Hz at 1 MHz frequency offset from the carrier of 4.56 GHz. The figure of merit is 186.5 dBc/Hz and the tuning range is from 4.2 G to 5 GHz (17.3 %). When the QVCO operates at 0.8 V voltage supply, the power consumption is 2.88 mW and the phase noise is ?115.7 dBc/Hz at 1 MHz frequency offset from the carrier of 4.58 GHz.     

A 6-GHz capacitively-coupled Colpitts CMOS quadrature voltage controlled oscillator

In this work a new low-noise low-power Colpitts quadrature voltage controlled oscillator (QVCO) made by coupling two identical current-switching differential Colpitts voltage controlled oscillators (VCO) is proposed; coupling of the VCOs is done using some capacitors in an “in-phase anti-phase” scheme. In this coupling configuration first harmonics (as well as higher harmonics) from each VCO are injected to the other VCO, as opposed to coupling schemes in which only even harmonics are injected. An analysis of the linearized circuit which confirms 90° phase difference between output signals of the proposed circuit is presented. Since no extra noise sources or power consumption are introduced to the core VCOs, the proposed QVCO achieves low phase noise performance and low power consumption. The proposed circuit is designed and simulated in a commercial 0.18 μm CMOS technology. The simulated phase noise of the proposed QVCO at 3 MHz offset frequency is ?138.3 dBc/Hz, at 6 GHz. The circuit dissipates 8.16 mW from a 1.8 V supply and its frequency can be tuned from 5.6 to 6.3 GHz.