S-parameter-measurement-based high-speed signal transientcharacterization of VLSI interconnects on SiO2-Si substrate

A new S-parameter-based signal transient characterization method for very large scale integrated (VLSI) interconnects is presented. The technique can provide very accurate signal integrity verification of an integrated circuit (IC) interconnect line since its S-parameters are composed of all the frequency-variant transmission line characteristics over a broad frequency band. In order to demonstrate the technique, test patterns are designed and fabricated by using a 0.35 μm complementary metal-oxide-semiconductor (CMOS) process. The time-domain signal transient characteristics for the test patterns are then examined by using the S-parameters over a 50 MHz to 20 GHz frequency range. The signal delay and the waveform distortion presented in the interconnect lines based on the proposed method are compared with the existing interconnect models. Using the experimental characterizations of the test patterns, it is shown that the silicon substrate effect and frequency-variant transmission line characteristics of IC interconnects can be very crucial     

S-Parameter-Measurement-Based Time-Domain Signal Transient and Crosstalk Noise Characterizations of Coupled Transmission Lines

Coupled transmission lines are experimentally characterized by using 4-port S-parameter measurements in a broad frequency band (up to 20 GHz). Test patterns are designed and fabricated by using a ball grid array (BGA) package process. Symmetrically coupled transmission lines are decoupled into two eigen modes that can be readily determined from the measured S-parameters. Then transmission line parameters and signal transient waveforms are directly determined by using the measured S-parameters. It is shown that not only are the transmission line parameters frequency-dependent, but also the frequency-variant effects and nonideal characteristics of transmission lines have a substantial effect on signal transients and crosstalk noises.      

Analytical and Experimental Study on Suppression of Electromagnetic Interference on High Speed Printed Circuit Board for Wireless Communication Systems

In this paper, a novel routing topology is proposed to reduce crosstalk between parallel links used for high data rate application. Generally, microstrip lines are used in high frequency RF printed circuit boards for propagating high speed signals in wireless communication. Since RF front end modules in wireless system supports a wide ultra wide band frequency range from 700 MHz to 12 GHz, package density parasitic effects have been a major issue which degrades system performance. The close proximity of signal transmission lines with a high packing density results signal integrity problems such as crosstalk and timing jitter. A modified coupled microstrip line is proposed to reduce crosstalk by means of increasing capacitive coupling ratio. Our proposed structure reduced far end crosstalk by 4 dB and near end crosstalk by 4 dB than existing structures. The proposed microstrip line increased the maximum data rate from 1 to 3.3 Gb/s and reduced timing jitter by 51 ps at 3.3 Gb/s.     

电磁偏谐振阻抗匹配宽带传输超表面设计

针对传统传输超表面固有高Q值导致的工作频带窄的问题,提出了一种电、磁双模偏谐振阻抗匹配实现宽带传输超表面设计方法。建立了实现低损耗透波阻抗匹配的本征参数模型,并根据经典Drude-Lorentz模型分析了本征参数在电磁谐振与偏谐振区域的电磁特性。基于此,通过独立激励电、磁偏谐振模式,设计了满足宽频带阻抗匹配的本征参数电路模型。基于该模型,通过在超表面中引入金属微带线和平行贴片分别作为电、磁偏谐振器,调控结构的本征参数,从而在宽频带内实现所需本征参数条件。仿真和测试结果均证明,设计的超表面实现了双极化模式相对带宽为79.5%的3 dB传输带宽,且结构具有0°~40°的斜入射稳定性。该超表面具有超宽带、结构简单的特点,可应用于高性能天线罩设计中。     

D-band neutralized amplifier design based on accurate millimeter-wave de-embedding method

A D-band neutralized amplifier design methodology based on accurate millimeter-wave de-embedding method is proposed. A neutralized amplifier stage using magnetic coupled configuration is introduced and its small signal equivalent circuit is analyzed in details. The neutralized network cancels the effects of the transistor gate-drain capacitor C_gd and boosts the maximum available gain of the amplifier stage to its maximum achievable gain. To achieve the expectable measured results, a millimeter-wave de-embedding method based on the transmission line model is developed. The transmission matrixes of the test structure are analyzed and the simulation results are used to prove the advantage of the de-embedding method in D-band. Implemented in 65 nm CMOS, 6 amplifier stages with different parameters are embedded into the proposed test structure. The measured results after the de-embedding calibration show a good agreement with the simulated results of the corresponding amplifier stages. Based on the proposed design methodology, one complete D-band amplifier has been implemented and achieves a gain of 13.78 dB at 157 GHz, with only 23.28 mW DC power consumption from a 1.2 V power supply.     

Highly compact tunable stop-band active filter for advanced communication systems

In this paper a novel electronically tunable active stop-band filter design is reported. This filter is designed in the UHF band to avoid the degradation of the receiver sensitivity when interfering signals at fixed or changing frequency are coupled to the antenna of the receiver front-end. The presented solution shows low insertion loss far from the notch frequency while rejecting the interfering signals by more than 40 dB regardless of their frequencies. The filter architecture is simple; it is based on a main transmission line segment to which a quarter-wavelength line segment is coupled. The fact of loading the end of the coupled line by a novel tunable active capacitor circuit introduced in this paper allows tuning simultaneously the filter frequency and the band-stop depth while reducing the power consumption and maintaining the device electrically stable. Moreover, by using the semi-lumped approach, the filter is compacted of more than 70 % in comparison to the conventional quarter-wavelength coupled line. The concept is demonstrated using low cost FR4 substrate and surface mount technology. The complete design has been fully simulated and experimental prototypes realized. Measurements are demonstrating the benefits of the proposed design.     

Design of a W-band Frequency Tripler for Broadband Operation Based on a Modified Equivalent Circuit Model of GaAs Schottky Varistor Diode

This paper presents the design and experimental results of a W-band frequency tripler with commercially available planar Schottky varistor diodes DBES105a fabricated by UMS, Inc. The frequency tripler features the characteristics of tunerless, passive, low conversion loss, broadband and compact. Considering actual circuit structure, especially the effect of ambient channel around the diode at millimeter wavelength, a modified equivalent circuit model for the Schottky diode is developed. The accuracy of the magnitude and phase of S21 of the proposed equivalent circuit model is improved by this modification. Input and output embedding circuits are designed and optimized according to the corresponding embedding impedances of the modified circuit model of the diode. The circuit of the frequency tripler is fabricated on RT/Rogers 5880 substrate with thickness of 0.127 mm. Measured conversion loss of the frequency tripler is 14.5 dB with variation of ±1 dB across the 75?~?103 GHz band and 15.5?~?19 dB over the frequency range of 103?~?110 GHz when driven with an input power of 18 dBm. A recorded maximum output power of 6.8 dBm is achieved at 94 GHz at room temperature. The minimum harmonics suppression is greater than 12dBc over 75?~?110 GHz band.     

Parasitic Parameters Extraction for InP DHBT Based on EM Method and Validation up to H-Band

This paper presents a small-signal model for InGaAs/InP double heterojunction bipolar transistor (DHBT). Parasitic parameters of access via and electrode finger are extracted by 3-D electromagnetic (EM) simulation. By analyzing the equivalent circuit of seven special structures and using the EM simulation results, the parasitic parameters are extracted systematically. Compared with multi-port s-parameter EM model, the equivalent circuit model has clear physical intension and avoids the complex internal ports setting. The model is validated on a 0.5?×?7 μm² InP DHBT up to 325 GHz. The model provides a good fitting result between measured and simulated multi-bias s-parameters in full band. At last, an H-band amplifier is designed and fabricated for further verification. The measured amplifier performance is highly agreed with the model prediction, which indicates the model has good accuracy in submillimeterwave band.     

Design of Multilayered K-Band and Ka-Band Slot-Coupled Microstrip 90° Hybrid Couplers Employing Circular Ring Patch Shapes

Numerical analysis and design of millimeter-wave (mmWave) slot-coupled microstrip 90° hybrid couplers employing circular ring patches, which is operating between 18 and 40 GHz frequency range for K-Band and Ka-Band radar applications, is presented in this paper. The proposed design uses multilayer printed circuit board (PCB) technology that allows having a compact and broad bandwidth coupler. The proposed couplers use broadside coupling between microstrip patches at the top and the bottom layers via an elliptical-shaped slot in the common ground plane (mid-layer). The design uses circular ring shaped broadside coupled patches and an elliptical-shaped slot created in a common ground plane between two identical dielectric substrates. The 3 dB coupler prototype has been fabricated on two 0.127 mm thick Rogers Duroid RT5880 substrates. The circuit occupies the dimensions of less than 5 mm × 5 mm without the extension that is required to insert the connectors. Extensive parametric studies are performed to address the effect of varying the coupler parameters on the coupling values, return losses, isolations, transmission magnitudes and phases through the operational frequency bandwidth. A 3 dB/90° hybrid coupler prototype is fabricated and then tested experimentally using Agilent E8364B PNA Network Analyzer. The simulation and experimental results show a good performance in terms of bandwidth, which covers the entire desired frequency range. In addition, detailed design for different coupling values of the proposed coupler is presented in this paper. The proposed coupler can achieve different coupling values range from 3 up to 9 dB that can be used for switched beam antenna array systems.     

Transmission characteristics of finite-width conductor-backedcoplanar waveguide

This paper presents theoretical and experimental results for a finite-width conductor-backed coplanar waveguide (FW-CBCPW). The guiding characteristics of FW-CBCPW are investigated first by the rigorous method of mode matching. An FW-CBCPW through line is then placed within a test fixture commonly used in laboratories, and the scattering parameters of the through line are obtained theoretically by approximating the FW-CBCPW as a simple system of coupled transmission lines. Experimental results are shown to agree very well with the theoretical ones. In particular, the anomalous behavior observed in the transmission characteristic of the through line is related to the resonant phenomenon of the terminated side planes which are short-circuited at both input and output ends due to the test fixture. Finally, a technique of mode suppression in the side-plane regions is suggested for the improvement of signal transmission over a broad band of frequency spectrum. The effects of extra higher order modes on the transmission characteristics at high frequencies are also discussed     

Analysis of F-shape microstrip line fed dualband antenna for WLAN applications

An analysis of microstrip line fed antennas has been presented theoretically using circuit theory concept. The theoretical investigations of F-shape antenna parameters such as return loss, VSWR, gain and efficiency have been calculated. It is found that antenna resonate at 2.4 and 5.2 GHz for lower and upper resonance frequencies respectively. The bandwidth of the F-shape antenna at lower resonance frequency is 20.08 % (simulated) and 17.05 % (theoretical) whereas at upper resonance frequency, it is 5.93 % (simulated) and 5.78 % (theoretical). The characteristics of the F-shape antenna is compared with other microstrip line fed antennas. It is found that F-shape antenna is linearly polarised along the X direction. The theoretical results are compared with IE3D simulation results as well as reported experimental results and they are in close agreement.     

Design of high-linearity 75–90 GHz CMOS down-conversion mixer for automotive radar

This paper presents a 75–90 GHz down-conversion mixer applied in automotive radar, which is characterized with high linearity, low local oscillator (LO) drive as well as high conversion gain (CG) using TSMC 65-nm CMOS general-purpose technology. The good linearity and isolation of mixer are required for automotive radar to cover short-middle-far range detection. The mixer includes an enhanced double-balanced Gilbert-cell core with series peaking transmission line and source degeneration technique for improving linearity and CG, two on-chip baluns and intermediate frequency (IF) buffer for IF test. Besides, to make the design more accurate and efficient, the modeling and design of millimeter-wave (mm-wave) passive devices are introduced. The mixer consumes 12 mW under 1.5 V. The input 1 dB compression point (P_1dB) is 2.5 dBm as well as IIP3 of 13.2 dBm at 80 GHz. High performances are achieved with the CG of 5 dB at 76 GHz with LO power of 0 dBm for frequencies of 75–90 GHz which covers the application of automotive radar frequency band (76–81 GHz) and LO-RF isolation of 33–37 dB for frequencies of 60–90 GHz. The area of the mixer is 0.14 mm², with PADs included.     

Compact UWB monopole antenna with quadruple band notched characteristics

ABSTRACT

A compact planar Ultrawideband (UWB) monopole antenna with quadruple band notch characteristics is proposed. The proposed antenna consists of a notched rectangular radiating patch with a 50 Ω microstrip feed line, and a defected ground plane. The quadruple band notched functions are achieved by utilising two inverted U-shaped slots, a symmetrical split ring resonator pair (SSRRP) and a via hole. The fabricated antenna has a compact size of 24 mm × 30 mm × 1.6 mm with an impedance bandwidth ranging from 2.86 to 12.2 GHz for magnitude of S₁₁ < ?10 dB. The four band notched characteristics of proposed antenna are in the WiMAX (worldwide interoperability for microwave access) band (3.25–3.55 GHz), C band (3.7–4.2 GHz), WLAN (wireless local area network) band (5.2–5.9 GHz) and the downlink frequency band of X band (7–7.8 GHz) for satellite communication are obtained. The measured and simulation results of proposed antenna are in good agreement to achieve impedance matching, stable radiation patterns, constant gain and group delay over the operating bandwidth.     

Low power analog comb filter for biomedical applications

An analog topology is proposed to implement a comb filter for removal of power-line interference from various low-amplitude biomedical signals. In this proposed methodology, an n-number of all-pass filters (APFs) and an adder circuit are used to suppress n-number of frequencies. All the APFs as well as the adder circuit are designed using a current conveyor to utilize the various properties of the current-mode circuits. The active and passive components used to design the comb filter include second-generation current conveyor (CCII±), resistor, and capacitor. The circuit is designed for n?=?4 to remove the power-line frequency of 50 Hz, and its three odd harmonics such as 150 Hz, 250 Hz, and 350 Hz. A PSPICE simulation is done to verify the performance of the proposed circuit. In simulation, all CCII±?are designed using macro model of commercially-available current feedback operational amplifier integrated circuit (IC) AD844 as well as dynamic threshold voltage metal oxide semiconductor technology. The proposed circuit is also implemented also using commercially available IC AD844 on breadboard for n?=?3. The output result on digital storage oscilloscope confirm the effectiveness of the proposed comb filter circuit in removing the power line interference i.e. the power-line frequency and its odd harmonics.     

A Reconfigurable Low-Noise Amplifier Using a Tunable Active Inductor for Multistandard Receivers

A reconfigurable low-noise amplifier (LNA) based on a high-value active inductor (AI) is presented in this paper. Instead of using a passive on-chip inductor, a high-value on-chip inductor with a wide tuning range is used in this circuit and results in a decrease in the physical silicon area when compared to a passive inductor-based implementation. The LNA is a common source cascade amplifier with RC feedback. A tunable active inductor is used as the amplifier output load, and for input and output impedance matching, a source follower with an RC network is used to provide a 50 Ω impedance. The amplifier circuit has been designed in 0.18 µm CMOS process and simulated using the Cadence Spectra circuit simulator. The simulation results show a reconfigurable frequency from 0.8 to 2.5 GHz, and tuning of the frequency band is achieved by using a CMOS voltage controlled variable resistor. For a selected 1.5 GHz frequency band, simulation results show S ₂₁ (Gain) of 22 dB, S ₁₁ of ?18 dB, S ₂₂ of ?16 dB, NF of 3.02 dB, and a minimum NF (NFmin) of 1.7 dB. Power dissipation is 19.6 mW using a 1.8 V dc power supply. The total LNA physical silicon area is (200×150) µm².     

频率选择性透波吸波电磁结构

提出的频率选择性透波吸波(FSTA)复合结构,是一种在保证天线正常工作性能的前提下,实现对带外电磁波吸收的新技术。该技术具有隐身频带宽,自身结构强度强,电子设备电磁兼容特性高等优势。分析了一些典型频率选择表面(FSS)单元的等效电路模型,推导出了FSTA 复合材料的等效电路模型,实现了对新型结构的快速定性分析,并得到结构中各参数对结构性能的作用规律。通过仿真优化实现了低频透波高频吸波(LTHA)型电磁结构的设计。     

Extraction of small-signal equivalent circuit model parameters for Si/SiGe HBT using S-parameters measurements and one geometrical information

A physical and simple method is proposed to extract the hybrid-π small-signal equivalent circuit model of Si/SiGe heterojunction bipolar transistor (HBT). In this method, we use test (dummy) structures to extract by means of fitting techniques the extrinsic bias-independent parameters representing the contact pads plus the transmission line connections to the core of the active device. All intrinsic bias-dependent parameters are calculated analytically from S-parameters only. The ratio of the area of the emitter contact to base area is used to solve the base–collector feedback problem due to the distributed nature of the base. Using this physical (geometry) constraint instead of the measured direct current (DC) information helps to get more reliable parameters and easier calculations. When we applied this methodology, a good agreement is obtained between the modelled S-parameters with the corresponding measured ones over the broad band from 40 MHz to 20.02 GHz. The error for three different bias points was less than 1.2%.     

一种基于传输线理论的新型GHz共模噪声抑制电路

基于传输线理论提出一种新型GHz宽阻带共模噪声抑制电路。利用双线传输线模型建立奇、偶模等效电路,在宽频带范围内准确预测了该电路结构的性能。实验结果表明:在1.9-4.5GHz频段内共模噪声抑制深度超-10dB,共模阻带相对带宽达81%;在dc-6GHz频段内差模插损小于3dB且差模信号群时延抖动较小,表明该结构可以很好地保证差模信号传输的信号完整性,性能优良。     

宽带低频放大器的设计

文中讨论了宽带低频放大器的设计。宽带网络采用有源低通滤波器和有源高通滤波器组合而成。在电路设计中,有源滤波电路和放大电路采用同一放大模块,这样简化了电路,缩小了体积,提高了产品的可靠性。通过分析低通滤波器和高通滤波器的设计过程,给出了试验数据、滤波器波形和宽带低频放大器电路图,再经过调整得到较好的通频带波形。该放大器在10～85kHz这个范围内,有较好的增益平坦度和稳定的性能,电压增益为60dB,满足设计要求。     

A wide frequency range delay line for fast-locking and low power delay-locked-loops

A voltage controlled delay cell with wide frequency range is presented in this paper. The delay-line which is resulted by connecting five series of delay cells generating a wide range of delay from 1.9 to 13.24 ns. It can be used in an analog delay locked loop. The linear characteristic of the circuit with respect to the conventional delay line structures is improved, and a better performance of noise is obtained using differential structure. This circuit is designed by ADS software and TSMC CMOS 0.18 μm technology, with supply voltage 1.8 V. By changing control voltage from 0.335 to 1.8 V in delay line, a wide range of frequency from 75.52 to 917.43 MHz will be covered. Simulation results show that the proposed delay line has power consumption of maximum 3.77 mW at frequency of 75.52 MHz. It also shows that increasing of frequency will reduce power dissipation which is the one of the main characteristics of this novel circuit. Moreover, the delay locked loop which uses these delay cells has a very high lock speed so that the maximum lock time in just five clock cycles.