Fast binary logarithm computing circuit for binary numbers less than one

A fast and expandable circuit for computing the approximate binary logarithm and antilogarithm of a fractional binary number is described. Illustration examples are included, and accuracy of the circuit is discussed.     

Analogue motion estimation based upon a squaring circuit

Motion estimation (ME) is the most computationally demanding part of the digital video coding process. The use of analogue computational circuits in this application can offer reductions in size and power dissipation. However, analogue circuits are subject to variations which can reduce performance. In this paper the analogue non-idealities are considered, and results are presented for video conferencing applications. Furthermore, a compact MOS squaring circuit for use in analogue ME processors is proposed. The circuit makes use of the inherent square-law characteristic of the MOS transistor in saturation and features small area, low-power and low-voltage operation. Measurements from fabricated samples of the circuit were incorporated in system-level simulations. The results of the simulations confirmed the suitability of the circuit for the intended application.     

高速电路中的信号完整性分析

随着嵌入式系统速度的提高,信号完整性(Signal Integrity,SI)问题受到越来越多的关注。由于信号质量不理想而造成系统崩溃的现象经常出现。结合系统设计中的实例,对高速信号传输的信号完整性问题作了较为详细的论述。在电路设计初期,通过PROTEL软件对和信号完整性进行分析,仿真结果指导PCB板的设计,可以有效地提高信号的完整性,极大地缩短设计周期,降低设计成本。     

边界增强算法的硬件实现

通过对应用于图象处理的边界增强算法的研究,结合目前世界上流行的硬件描述语言Verilog HDL的设计,将边界增强算法用硬件电路模块的形式来实现。此硬件电路采用流水线结构,关键运算部件采用复用形式,以提高系统处理效率。     

高速电路信号完整性问题研究及其仿真分析

针对高速电路信号完整性,在介绍信号完整性基本概念的基础上,重点研究了信号反射问题.分析了反射形成的原因和解决方法,阐述了信号完整性仿真分析的相关内容,最后结合实际的应用说明了利用Mentor Graphics公司的HyperLynx仿真工具解决信号反射的方法.     

基于FPGA的超声波传感器前端电路设计

超声波传感器广泛应用于风速、风向的测量,前端电路的设计直接关乎系统性能的好坏.为达到稳定的驱动效果,驱动电路采用了低压驱动方式.为能接收稳定、准确的超声波信号,设计了接收及信号处理电路,进行接收抗干扰限幅处理、前置放大、带通滤波、自动增益控制放大和电压比较,将所接收的超声波交变电压信号转换成可供FPGA 直接使用的数字信号.实验结果验证,各个电路模块的设计均满足系统要求.     

Top-down design of a VLSI digital filter bank

This paper relates theoretical investigations in digital signal processing (DSP) to the design of a VLSI digital filter bank (DFB). Emphasis is on a top-down approach to identify multilevel parallelisms inherent in a generic DSP algorithm and a new VLSI architecture. System level control and communication requirements are examined. Finite word length effects on filter accuracy are identified. The complexity of filter modules is reduced by partitioning large filter functions into a sum of smaller subfunctions. A memory intensive architecture minimizes design time. Up to 100 DRF modules are configured in parallel to perform signal processing up to 20 MHz. This VLSI DFB out performs sequential von Neumann architectures by several orders of magnitude using the same level of VLSI technology.     

一种高速并行信号处理系统设计

现代嵌入式系统的广泛应用对信号处理运算量以及实时性都提出了更高的要求,通过多处理器构建并行处理体系结构已经成为了解决这一问题的必然趋势。在研究并行处理体系结构的基础上,设计并实现了一种基于多DSP+FPGA的高速并行信号处理系统,该系统具有集成度高、运算能力强、通用性好、可扩展性好等特点,满足大规模实时信号处理的实际应用需求。     

基于FPGA的异步流水乘法器设计的教学方案

本文以异步流水乘法器的设计为例,介绍了利用FPGA进行异步电路设计的思路及方法。本设计采用两段握手协议实现异步流水乘法器,将其分解为三个核心模块:信号分支模块、异步移位模块和异步加法器模块。本文具体说明了利用硬件描述语言实现异步乘法器的方法和步骤,通过Modelsim软件进行功能仿真,并下载到Genesys板卡上进行系统测试。该教学方案有助于学生理解并掌握异步电路设计方法。     

An analysis method for high-speed circuit systems

A new method for analyzing high-speed circuit systems is presented. The method adds transmission line end currents to the circuit variables of the classical modified nodal approach. Then the matrix equation describing high-speed circuit system can be formulated directly and analyzed conveniently for its normative form. A time-domain analysis method for transmission lines is also introduced. The two methods are combined together to efficiently analyze high-speed circuit systems having general transmission lines. Numerical experiment is presented and the results are compared with that calculated by Hspice.     

基于FPGA的全帧CCD驱动设计

以加拿大Dalsa公司的全帧CCD图像传感器FTF4027M为例,在研究了全帧CCD结构和驱动时序的基础上,提出了基于现场可编程逻辑门阵列(FPGA)的驱动脉冲设计方法.选用FPGA作为硬件设计平台,使用VHDL语言对驱动时序发生器进行了硬件描述,采用Quartus Ⅱ 5.0对所设计的驱动时序发生器进行了仿真,针对Altera公司的FPGA器件EP1C3T144C8进行了适配.实验结果表明,设计的驱动电路可以满足其全帧CCD的各项驱动要求并且具有设计灵活、硬件调试简单的优点.     

基于FPGA的频率信号实时程控计数电路

飞控计算机采集飞机上各类传感器和其他飞行控制系统的输入信息,分析解算后控制飞行姿态。频率信号的采集就是其中重要的数据信息类型之一。在此采用可编程芯片FPGA实现将频率信号转换为数字信号的方法。这种设计思想避免了搭建复杂的硬件电路来实现该功能,降低了模块硬件设计成本,节省了印制板布局空间,降低了设计复杂度,同时设计该功能的测试接口,以便于该功能故障后能够准确定位故障源。     

应用于微传感器信号处理的混合电路系统的设计与实现

研究旨在设计一个应用于飞行器机翼表面边界层的流动监测系统。该系统主要由微传感器及其信号处理电路构成。本文的主要工作是微传感器信号处理电路系统中低功耗的模拟电路芯片的及相关数字电路板的设计,重点在于完成模拟电路芯片的具体应用。目的是将该模拟电路芯片良好地应用于该数字电路板,使其协同工作,构成一个完整的混合电路系统,以便在较低的成本下,较好地完成微传感器信号处理的任务。     

Design and implementation of a hybrid circuit system for micro sensor signal processing

This paper covers a micro sensor analog signal processing circuit system(MASPS) chip with low power and a digital signal processing circuit board implementation including hardware connection and software design. Attention has been paid to incorporate the MASPS chip into the digital circuit board.The ultimate aim is to form a hybrid circuit used for mixed-signal processing,which can be applied to a micro sensor flow monitoring system.     

A CMOS Analog Multiplier Free from Mobility Reduction and Body Effect

This paper proposes a novel CMOS analog multiplier. As its significant merit, it is free from mobility reduction and body effect. Thus, the proposed multiplier is expected to have good linearity, comparing with conventional multipliers. Four transistors operating in the linear region constitute the input cell of the multiplier. Their sources and backgates are connected to the ground to cancel the body effect. Their gates are fixed to the same bias voltage to remove the effect of the mobility reduction. Input signals are applied to the drains of the input cell transistors through modified nullors. The simulation results show that THD is less than 0.8% for 0.6 V_p-p input signal at 2.5 V supply voltage, and that the 3 dB bandwidth is up to about 13.3 MHz.     

高速脉冲峰值保持电路的设计

为满足能谱分析中多道脉冲幅度分析器A／D转换的要求,设计了一种高速脉冲峰值保持电路。以高速电压比较器LM311、采样／保持芯片1517398作为主要器件,具有幅度判别、波形采样、峰值保持、电荷泄放等功能,结构简单,易于调试。实验表明：对于高速脉冲信号,该电路可以较好地甄别峰值并保持,性能可靠,响应速度快,误差小于1％。     

60 Gbit/s宽带电路交换ASIC芯片设计

文章提出了一种60 Gbit/s宽带电路交换专用集成电路(ASIC)芯片的设计实现方案.针对设计芯片速度快、规模大和功耗大等特点,给出了采用流水线设计思想和优化结构处理技术的电路设计解决方案.同时还给出了采用现场可编程门阵列(FPGA)芯片对设计电路进行功能验证的结果和ASIC流片的基本数据.     

一种适合芯片技术的语音特征提取电路

设计一种便于芯片技术实现、结构简单的语音特征提取电路. 它由带通滤波器组、整流电路和低通滤波器构成.同时,借此电路阐述一种充分利用器件特性设计电路的思想. 这种思想以完成功能为目的，不以完成算法为目标. 据此建立的数学模型可能很复杂，但电路结构简单，便于芯片实现，芯片资源利用率高. 对实际语音信号进行SPICE模拟结果初步表明，此电路可以得到与线性系统类似的语音特征.     

轻型战场侦察雷达信号处理一体化设计

主要介绍针对轻型战场侦察雷达系统的要求,使用大规模FPGA器件与嵌入式计算机实现高度集成化的信号处理系统设计方案.