A new quantum-dot cellular automata full-adder

A novel expandable five-input majority gate for quantum-dot cellular automata and a new full-adder cell are presented. Quantum-dot cellular automata (QCA) is an emerging technology and a possible alternative for semiconductor transistor based technologies. A novel QCA majority-logic gate is proposed. This component is suitable for designing QCA circuits. The gate is simple in structure and powerful in terms of implementing digital functions. By applying these kinds of gates, the hardware requirement for a QCA design can be reduced and circuits can be simpler in level, gate counts and clock phases. In order to verify the functionality of the proposed device, some physical proofs are provided. The proper functionality of the FA is checked by means of computer simulations using QCADesigner tool. Both simulation results and physical relations confirm our claims and its usefulness in designing every digital circuit.     

Efficient design of parity preserving logic in quantum-dot cellular automata targeting enhanced scalability in testing

Design of parity preserving logic based on emerging nanotechnology is very limited due to present technological limitation in tackling its high error rate. In this work, Quantum-dot cellular automata (QCA), a potential alternative to CMOS, is investigated for designing easily testable logic circuit. A novel self-testable logic structure referred to as the testable-QCA (t-QCA), using parity preserving logic, is proposed. Design flexibility of t-QCA then evaluated through synthesis of standard functions. The programmability feature of t-QCA is utilized to implement an ALU, realizing six important functions. Although the parity preservation property of t-QCA enables concurrent detection of permanent as well as the transient faults, an augmented test logic circuit (TC) using QCA primitives has been introduced to cover the cell defects in nanotechnology. Experimental results establish the efficiency of the proposed design that outperforms the existing technologies in terms of design cost and test overhead. The achievement of 100% stuck-at fault coverage and the 100% fault coverage for single missing/additional cell defects in QCA layout of the t-QCA gate, address the reliability issues of QCA nano-circuit design.     

Design and simulation of sequential circuits in quantum-dot cellular automata: Falling edge-triggered flip-flop and counter study

Quantum-dot Cellular Automata (QCA) is an emerging nanotechnology, with extremely small feature size and ultralow power consumption comparing with transistor-based technology. Anteriority, basic level-triggered flip-flop designs based on QCA implementation were examined. In this paper, we utilize the unique QCA characteristics and clock zones to design falling edge-triggered J-K flip-flop that is stable and practical. Simulation with the QCADesigner simulator is performed to verify the functionality of the proposed falling edge-triggered flip-flop. This paper also explores the design of counters. Synchronous counters are designed with several different bit sizes and simulation results demonstrate the validity of them.     

一种基于量子细胞自动机的三维量子细胞神经网络

以量子细胞自动机为神经元,提出了一种三维的量子细胞神经网络结构;该量子细胞网络包含上下两层的量子细胞自动机阵列,并引入了A模板、B模板以及阈值的概念.以量子细胞自动机的极化率为像素值,通过选择不同的模板、阈值等参数.使得量子细胞神经网络实现了"与"、"或"、"非"操作以及边缘提取等图像处理功能,并利用MATLAB进行了仿真验证,数值仿真结果验证了其在图像处理上的有效性.与传统的细胞神经网络相比,量子细胞神经网络易于实现超大规模且具有超低功耗、超高集成度等优点.     

An efficient design and implementation of Vedic multiplier in quantum-dot cellular automata

Telecommunication Systems - The Quantum-Dot Cellular Automata (QCA) is an incipient nanotechnology in contrast to the CMOS technology with appealing features like low power consumption, high speed...     

基于移动元胞自动机的网络舆情传播模型

为了准确刻画网络舆情的变化规律,针对经典元胞自动机存在的不足,考虑网络舆情主体的可移动因素,提出一种基于移动元胞自动机的网络舆情传播模型。首先对经典元胞自动机的工作原理进行分析,提出移动元胞自动机模型,然后根据网络舆情的特点,制定网络舆情主体状态转换规则和移动规则,建立移动元胞自动机的网络舆情传播模型,最后采用Matlab 2011对网络舆情演化过程进行仿真分析。仿真结果表明,舆情主体移动概率对网络舆情传播速度和同质化率影响比较大,移动元胞自动机模型可以很好地描述网络舆情的实际传播过程。     

Novel RAM cell designs based on inherent capabilities of quantum-dot cellular automata

Quantum Cellular Automata (QCA) is a novel and attractive method which enables designing and implementing high-performance and low-power consumption digital circuits at nano-scale. Since memory is one of the most applicable basic units in digital circuits, having a fast and optimized QCA-based memory cell is remarkable. Although there are some QCA structures for a memory cell in the literature, however, QCA characteristics may be used in designing a more optimized memory cell than blindly modeling CMOS logics in QCA. In this paper, two improved structures have been proposed for a loop-based Random Access Memory (RAM) cell. In the proposed methods, the inherent capabilities of QCA, such as the programmability of majority gate and the clocking mechanism have been considered. The first proposed method enjoys smaller number of cells and the wasted area has been reduced compared to traditional loop-based RAM cell. For the second proposed method, the memory access time has been duplicated in presence of smaller number of cells. Irregular placement of QCA cells in a QCA layout makes its realization troublesome. So, we have proposed alternative versions of the proposed methods that exploit regularity of clock zones in design and have compared them to each other. QCA designer has been employed for simulation of the proposed designs and proving their validity.     

A novel FPGA-programmable switch matrix interconnection element in quantum-dot cellular automata

The Quantum-dot cellular automata (QCA) is a novel nanotechnology, promising extra low-power, extremely dense and very high-speed structure for the construction of logical circuits at a nanoscale. In this paper, initially previous works on QCA-based FPGA’s routing elements are investigated, and then an efficient, symmetric and reliable QCA programmable switch matrix (PSM) interconnection element is introduced. This element has a simple structure and offers a complete routing capability. It is implemented using a bottom-up design approach that starts from a dense and high-speed 2:1 multiplexer and utilise it to build the target PSM interconnection element. In this study, simulations of the proposed circuits are carried out using QCAdesigner, a layout and simulation tool for QCA circuits. The results demonstrate high efficiency of the proposed designs in QCA-based FPGA routing.     

Parallel pseudorandom number generation in GaAs cellular automata for high speed circuit testing

To facilitate test vector generation for high-speed circuits, we present the design and circuit simulation of parallel pseudorandom number generators in GaAs technology. These PRNGs are based on hybrid cellular automata (CA) in which mixtures of local rules are employed in one dimensional arrays, with minimal delay due to having only local wiring between neighboring cells. HSPICE simulations of these circuits demonstrate that they operate at a clock frequency above 1 GHz. Delay simulations indicate that GaAs PRNGs based upon linear feedback shift registers, in contrast with hybrid CAs, exhibit a degradation in clock frequency due to the effects of global interconnects, and that this degradation increases with the register length.This work was supported by Micronet, by the Canadian Microelectronics Corporation, and by the Natural Sciences and Engineering Research Council of Canada.     

一种CORDIC协处理器核的设计与实现

航天导航计算机、数管系统需要进行大量实时数学运算,而目前绝大多数CPU缺乏对三角函数及超越函数的硬件支持。纯软件实现这些基本函数会占用大量的CPU资源。针对这一情况提出了一种基于CORDIC算法的协处理器核。该核可以提供向量旋转、常用三角函数以及exp、sqrt、ln运算,并且其精度可以进行配置。并且该协处理器通过降低与CPU的交互复杂度,提高了其实时性。该IP核可以较容易地集成进航天电子系统常用的FPGA中,具有高运行频率和低资源占用率,可以被广泛地应用于有高计算需求的嵌入式中,具有较高的工程价值。     

A class of two-dimensional cellular automata and their applications in random pattern testing

A basic framework to characterize the behavior of two-dimensional (2-D) cellular automata (CA) has been proposed. The performance of the regular structure of the 2-D CA has been evaluated for pseudo-random pattern generation. The potential increase in the local neighborhood structure for 2-D CA has led to better randomness of the generated patterns as compared to LFSR and 1-D CA. The quality of the random patterns generated with 2-D CA based built-in-self-test (BIST) structure has been evaluated by comparing the fault coverage on several benchmark circuits. Also a method of synthesizing 2-D CAs to generate patterns of specified length has been reported. The patterns generated can serve as a very good source of random two-dimensional sequences and also variable length parallel pattern generation having virtually nil correlation among the bit patterns.     

On behavior of two-dimensional cellular automata with an exceptional rule under periodic boundary condition

This article deals with the behavior of two-dimensional(2-D) cellular automata(CA) with a special rule under periodic boundary condition by using matrix algebra.The important characteristics of CA have been studied,such as Garden of Eden(GOE),maximal transient length,maximal cycle length and so forth.Several necessary and sufficient conditions are provided,which guarantee a given configuration of being a GOE in different cases.Besides,algorithms are proposed to obtain the number of GOEs,the maximal transien...     

Minimal cost one-dimensional linear hybrid cellular automata of degree through 500

This letter is a supplement of the table of the minimal cost one-dimensional linear hybrid cellular automata with the maximum length cycle by Zhang, Miller, and Muzio [IEE Electronics Letters, 27(18):1625–1627, August 1991].This work was supported in part by Research Grants and Postgraduate Scholarships from the Natural Sciences and Engineering Research Council of Canada and by an equipment loan from the Canadian Microelectronics Corporation.     

Pathological liver segmentation using stochastic resonance and cellular automata

Liver segmentation continues to remain a major challenge, largely due to its intensity complexity with surrounding anatomical structures (stomach, kidney, and heart), high noise level and lack of contrast in pathological computed tomography data. In this paper, we present an approach to reconstructing the liver surface in low contrast computed tomography. The main contributions are: (1) a stochastic resonance based methodology in discrete cosine transform domain is developed to enhance the contrast of pathological liver images, (2) a new formulation is proposed to prevent the object boundary, resulted by cellular automata method, from leaking into the surrounding areas of similar intensity, and (3) a level-set method is suggested to generate intermediate segmentation contours from two segmented slices distantly located in a subject sequence. We have tested the algorithm on real datasets obtained from two sources, Hamad General Hospital and MICCAI Grand Challenge workshop. Both qualitative and quantitative evaluation performed on liver data show promising segmentation accuracy when compared with ground truth data reflecting the potential of the proposed method.     

基于FPGA的一种改进型三角超越函数CORDIC实现方式

CORDIC算法将复杂的算术运算转化为简单的加法和移位操作,然后逐步逼近结果。这种方法很好地兼顾了精度、速度,非常适合三角超越函数的硬件实现,但同时也带来硬件资源占用增加的问题。如何尽可能减少CORDIC算法带来的硬件资源占用增加,是利用CORDIC算法实现三角超越函数的关键。本文提出一种改进型三角超越函数CORDIC硬件实现方案,该方案中CORDIC算法IP核利用VHDL语言进行编写,IP核在Modelsim6.5g上通过功能仿真,并且在XUPV5-LX110T FPGA开发板上通过硬件测试,实验结果表明改进的方案可以有效减少CORDIC算法带来的硬件资源占用增加。     

Modeling and Evaluating Errors Due to Random Clock Shifts in Quantum-Dot Cellular Automata Circuits

This paper analyzes the effect of random phase shifts in the underlying clock signals on the operation of several basic Quantum-dot Cellular Automata (QCA) building blocks. Such phase shifts can result from manufacturing variations or from uneven path lengths in the clocking network. We perform numerical simulations of basic building blocks using two different simulation engines available in the QCADesigner tool. We assume that the phase shifts are characterized by a Gaussian distribution with a mean value of , where i is the clock number and a standard deviation, σ, which is varied in each simulation. Our results indicate that the sensitivity of building blocks to phase shifts depends primarily on the layout while the reliability of all building blocks starts to drop once the standard deviation, σ exceeds 4°. A full adder was simulated to analyze the operation of a circuit featuring a combination of the building blocks considered here. Results are consistent with expectations and demonstrate that the carry output of the full adder is better able to withstand the phase shifts in the clocking network than the Sum output which features a larger combination of the simulated building blocks.

基于CORDIC算法的GPS载波跟踪环鉴相器的设计

提出了一种实现GPS载波跟踪环鉴相器的方法,该方法采用CORDIC算法来实现用于鉴相的arctan函数.同时,给出了这种基于CORDIC算法的硬件实现的结构和相应的仿真结果.这种算法结构简单,只需要采用加法和移位操作即可,非常易于硬件实现,并且其仿真结果可以达到GPS的要求.     

基于CORDIC算法的DDS的FPGA设计与优化

采用CORDIC算法计算三角函数值来实现DDS,可以减少存储资源,便于在FPGA中实现.通过对传统CORDIC算法流水结构的分析,提出了一种在迭代过程采用不同位宽的寄存器存储角度值和幅度值的优化方法,可以节省资源而不影响计算精度,并且在FPGA中实现了该方法.     

CORDIC算法在跟踪环中的应用与FPGA实现

主要介绍了坐标旋转数字计算（CORDIC）算法在跟踪环鉴别器中的应用,包括码跟踪环、锁频环和锁相环鉴别器,并进行了FPGA实现。在设计中,采用统一CORDIC算法优化方法减少硬件开销,用非流水方式在一个CORDIC运算基本单元中实现了码跟踪环、锁频环和锁相环三种鉴别器。同时对CORDIC运算的精度和位宽进行分析,在保证环路功能的情况下尽量减少硬件资源的使用。在Virtex5lx220上测试使用了该鉴别器的GPS跟踪环,取得了满意的跟踪效果。