High frequency current mode oscillator employing fTintegration technique

A low distortion high frequency oscillator is described, which is a development of the recently proposed f_T-integrator, in which an amplitude control circuit is embedded inside the integrator. Simulation results suggest that, for the oscillation range 1-2.6 GHz, the total harmonic distortion (THD) of the output current signal is well below 0.5% for the output current level at 50% modulation depth (peak-to-peak). The phase noise of the oscillator is simulated to be -72 dBc/Hz at 1 MHz offset for 1% THD output current     

Fast amplitude stabilization of an RC oscillator

A technique is proposed for stabilizing the output amplitude of a variable-frequency RC sine-wave oscillator. Amplitude settling time is reduced by converting amplitude to a d.c. voltage having only a small ripple content, which requires little filtering. A relationship between amplitude transient response and harmonic distortion is demonstrated, and the results are compared to those obtained by more conventional methods.     

Fast amplitude control in twin-T bridge RC oscillators

When a sinusoidal voltage is applied to the symmetrical twin-T bridge, the voltages at the inner nodes of the bridge have equal amplitudes and are shifted by 90°. If they are squared and summed, the resulting DC voltage can be used to control the gate of a field-effect transistor connected to the bridge. The oscillator with such a control system simultaneously has low distortion and fast amplitude transient response.     

10 MHz CMOS OTA-C voltage-controlled quadrature oscillator

A quadrature-type voltage-controlled oscillator with operational transconductance amplifiers and capacitors (OTA-C) is presented. A monolithic integrated CMOS test circuit is introduced to verify theoretical results. The attainable frequency range of oscillation of the chip test circuit is 3-10.34 MHz. The total harmonic distortion (THD) is 0.20-1.87% for corresponding peak-to-peak amplitude voltages between 100 mV and 1 V. This amplitude can be controlled either by using a diode connection of two MOS transistors or a proposed nonlinear resistor.<>     

Suppression of line voltage related distortion in current controlled grid connected inverters

The influence of selected control strategies on the level of low-order current harmonic distortion generated by an inverter connected to a distorted grid is investigated through a combination of theoretical and experimental studies. A detailed theoretical analysis, based on the concept of harmonic impedance, establishes the suitability of inductor current feedback versus output current feedback with respect to inverter power quality. Experimental results, obtained from a purpose-built 500-W, three-level, half-bridge inverter with an L-C-L output filter, verify the efficacy of inductor current as the feedback variable, yielding an output current total harmonic distortion (THD) some 29% lower than that achieved using output current feedback. A feed-forward grid voltage disturbance rejection scheme is proposed as a means to further reduce the level of low-order current harmonic distortion. Results obtained from an inverter with inductor current feedback and optimized feed-forward disturbance rejection show a THD of just 3% at full-load, representing an improvement of some 53% on the same inverter with output current feedback and no feed-forward compensation. Significant improvements in THD were also achieved across the entire load range. It is concluded that the use of inductor current feedback and feed-forward voltage disturbance rejection represent cost-effect mechanisms for achieving improved output current quality.     

A Modified Valley Fill Electronic Ballast Having a Current Source Resonant Inverter With Improved Line-Current Total Harmonic Distortion (THD), High Power Factor, and Low Lamp Crest Factor

In this paper, a modified valley fill (VF) circuit is employed to combine with a current-fed resonant inverter as a passive high power factor (PF) electronic ballast. A conventional VF circuit limits the line current to conduct when the conduction angles are: 30deg les omegat les 150deg and 210deg les omegat les 330deg during the line period, which results in high total harmonic distortion (THD). The modified VF circuit has the following advantage: When the capacitors are connected in parallel, the voltage across the capacitors is one-third of the peak voltage, which allows the conduction angle of the line current to be further extended to 19.5deg les omegat les 160.5deg and 199.5deg les omegat les 340.5deg, so that a lower THD can be achieved. The high lamp crest factor (CF) problem generated by the high ripple voltage from the modified VF circuit is improved in the proposed ballast as variable frequency control is employed to continuously regulate the lamp current. An experimental prototype is then built in the laboratory to verify the feasibility of the proposed work for a 26-W compact fluorescent lamp. The final results confirm that a PF of 0.986 and a lamp CF of 1.49 are achieved with the proposed circuit, whereas a PF of 0.96 is achieved with the conventional VF ballast.     

A novel switching-mode ac buck-boost voltage regulator

This paper presents a novel switching-mode ac/ac voltage regulator using a bidirectional buck-boost converter. Since it operates at high frequency, the proposed system can be designed compactly, and there is a wide range of input voltage from 1/2 to 2 per unit with fast dynamic response and low harmonics. In order to verify the accuracy of the proposed method, a 500 W prototype has been implemented in the laboratory. From the experimental results, the regulation of the output voltage is within less than 1%. Moreover, the total harmonic distortion (THD) of the input current under full load is 2.46% and the output voltage has a THD of 1.77%.     

High-performance programmable AC power source with low harmonicdistortion using DSP-based repetitive control technique

This paper proposes a new control scheme based on a two-layer control structure to improve both the transient and steady-state responses of a closed-loop regulated pulse-width-modulated (PWM) inverter for high-quality sinusoidal AC voltage regulation. The proposed two-layer controller consists of a tracking controller and a repetitive controller. Pole assignment with state feedback has been employed in designing the tracking controller for transient response improvement, and a repetitive control scheme was developed in synthesizing the repetitive controller for steady-state response improvement. A design procedure is given for synthesizing the repetitive controller for PWM inverters to minimize periodic errors induced by rectifier-type nonlinear loads. The proposed control scheme has been realized using a single-chip digital signal processor (DSP) TMS320C14 from Texas Instruments. A 2-kVA PWM inverter has been constructed to verify the proposed control scheme. Total harmonic distortion (THD) below 1.4% for a 60-Hz output voltage under a bridge-rectifier RC load with a current crest factor of 3 has been obtained. Simulation and experimental results show that the DSP-based fully digital-controlled PWM inverter can achieve both good dynamic response and low harmonics distortion     

基波电压线性输出的两相SVPWM算法

本文提出了一种基于基波电压幅值线性输出控制的两相SVPWM过调制算法,该算法不需要存储数据.能够使逆变器平滑的从线性调制工作状态过渡到方波工作状态,非常适合数字化应用。文中分析了应用该算法以后,逆变器输出相电压的谐波畸变（THD）情况,以及主要谐波成分百分含量的变化情况,并和传统两相SVPWM控制算法进行了技术指标对比。分析及仿真证明,该算法具有输出基波电压增益线形和实现简单的优点,非常适合电机实际应用。     

Design of Low-Voltage Highly Linear Switched-R-MOSFET-C Filters

This paper discusses the design, analysis and performance of a low-voltage, highly linear switched-R-MOSFET-C filter. High linearity, even at a low supply voltage, is achieved through the use of duty-cycle-controlled tuning. Tuning MOSFETs are switched completely on while conducting, such that their nonlinear resistance is much smaller than the linear filter resistors, resulting in low distortion. The MOSFETs are also placed inside the filter feedback loop which further reduces distortion. Because tuning is done in the time domain, rather than in the voltage domain, the tuning range is independent of the supply voltage. The filter achieves -77 dB total harmonic distortion (THD) using a 0.6-V supply, and -90 dB THD using a 0.8-V supply, with a 0.6-Vpp differential 2 kHz sine input. The prototype IC, implemented in a 0.18-mum CMOS process, occupies an area of 0.7 mm² and consumes 1 mW of power from a 0.6-V supply.     

Zero tracking error controller for three-phase CVCF PWM inverter

A zero tracking error control scheme for three-phase CVCF PWM inverters is proposed. The proposed scheme uses repetitive controller (RC) to force output line voltages to track a sinusoidal reference signal with zero error. Minimised voltage distortion and a fast response are obtained. The validity of the proposed scheme has been verified by simulations     

Output voltage distortion characterization in multilevel PWM converters

One of the main features to consider in the development of new pulsewidth modulations (PWM) for multilevel converters is the high-frequency output-voltage distortion. In this letter, a novel per-switching-cycle figure, the harmonic distortion of order n for switching cycle k(HD/sub n,k/), is introduced to quantitatively characterize the output three-phase voltage harmonic distortion of multilevel converters around all the integer multiples of the switching frequency. This figure allows for the decomposing of the modulation design problem within an output voltage fundamental cycle into an independent set of smaller problems for every switching cycle. The expression of HD/sub n,k/ as a function of the switching states' duty-ratio is presented for the three-level three-phase neutral-point-clamped voltage source inverter and it can be easily obtained for any other multilevel converter. From the evaluation of HD/sub n,k/ over 1/6th of the output-voltage fundamental-period the value of HD/sub n/ is obtained, providing a measure of the output voltage distortion in a fundamental period. This information is obtained at a lower computational cost than conventional fast Fourier transform (FFT) analysis. The accuracy of the HD/sub n/ distortion predictions is verified by comparing it to FFT-based results obtained from simulation and experiments. The expression to compute the total harmonic distortion (THD) as a function of HD/sub n/ is also derived.     

A novel single-phase ZCS-PWM high-power-factor boost rectifier

This paper presents a novel single-phase high-power-factor (HPF) pulsewidth-modulated (PWM) boost rectifier featuring soft commutation of the active switches at zero current (ZC). It incorporates the most desirable properties of conventional PWM and soft-switching resonant techniques. The input current shaping is achieved with average current mode control and continuous inductor current mode. This new PWM power converter provides ZC turn on and turn off of the active switches, and it is suitable for high-power applications employing insulated gate bipolar transistors (IGBTs). The principle of operation, the theoretical analysis, a design example and experimental results from a laboratory prototype rated at 1600 W with 400 VDC output voltage are presented. The measured efficiency and the power factor were 96.2% and 0.99%, respectively, with an input current total harmonic distortion (THD) equal to 3.94%, for an input voltage with THD equal to 3.8%, at rated load     

EPS电感式转矩传感器正弦波振荡器的研究

为了满足电动助力转向电感式转矩传感器的需要，设计了一种简单、实用的正弦振荡器。该振荡器采用结型场效应管的压控电阻特性设计自动增益控制电路，通过合理选择元器件的参数抑制了信号幅度的温漂。实验表明，振荡器的输出信号幅度稳定、失真小，满足传感器振荡器的性能要求。     

Linearization Technique for Source-Degenerated CMOS Differential Transconductors

A supplementary linearization technique for CMOS differential pairs with resistive source degeneration is proposed. The approach exploits an auxiliary (degenerated) differential pair to drive the bulk terminals of the main pair. Transistor-level simulations on a design using a 0.25-mum process and powered with 2.5 V and 1 mA, show that total harmonic distortion (THD) in the voltage-to-current conversion is decreased by 10 dB (for an input differential signal with a peak amplitude of 0.5 V and for frequencies up to 100 MHz) compared to the traditional source-degenerated transconductor. This THD improvement is achieved with a negligible increase in power consumption.     

Analysis and CAD implementation techniques of total harmonic distortion in analog VLSI circuits

This paper presents a new methodlogy to accurately evaluate the total harmonic distortion (THD) behavior of modern integrated circuits. The methodology is general, technology independent and is used to determine large-signal or reactive THD of signal processing circuits operating in the voltage or the current domain. It is based on Fourier series analysis and Parseval's theorem, where numerical integration may be needed to accurately compute THD. For low-frequency THD, the numerical integration can be simplified to a small number of summation without degrading the accuracy. The new methodology is incorporated in a computer-aided environment which accurately estimates THD, and the speed of calculation for many circuit is several orders of magnitude faster than SPICE or other commercial CAD tools. In addition, optimization of transistor sizes to reduce THD can be achieved by incorporating the methodology in an object-oriented CAD tool such as APLAC.Currently on leave as a Fulbright-Hays professor at the Helsinki University of Technology, Finland.     

Linear voltage-to-current converters with current reuse technique

This paper proposes a linear voltage-to-cur-rent converter with current reuse technique to reduce circuit power consumption without deteriorating its linearity and bandwidth. The proposed circuit is designed using 0.18???m CMOS process parameters from TSMC. Simulation results show that the total harmonic distortion (THD) of the proposed circuit with a 2.5-V input amplitude is less than 1% for input frequency up to 200?MHz under a 1.8-V supply voltage. The total current consumption is 10.8?mA.     

Photovoltaic Power Conditioning System With Line Connection

A photovoltaic (PV) power conditioning system (PCS) with line connection is proposed. Using the power slope versus voltage of the PV array, the maximum power point tracking (MPPT) controller that produces a smooth transition to the maximum power point is proposed. The dc current of the PV array is estimated without using a dc current sensor. A current controller is suggested to provide power to the line with an almost-unity power factor that is derived using the feedback linearization concept. The disturbance of the line voltage is detected using a fast sensing technique. All control functions are implemented in software with a single-chip microcontroller. Experimental results obtained on a 2-kW prototype show high performance such as an almost-unity power factor, a power efficiency of 94%, and a total harmonic distortion (THD) of 3.6%.     

A new UPS scheme provides harmonic suppression and input powerfactor correction

A new parallel processing uninterruptible power supply (UPS) configuration is proposed in this paper. It provides active power line conditioning to minimize mains current distortion. This performance is superior to a conventional UPS. A prototype has been implemented and tested to verify its performance. The experimental results show that the input power factor of the proposed UPS is nearly unity, and the total harmonic distortion (THD) of the input current under nonlinear loading is only 3.618% for a mains voltage with THD of 1.633%     

Two-level switching pattern deadbeat DSP controlled PWM inverter

A two-level switching algorithm of the deadbeat controlled PWM inverter is presented. Two levels, instead of three levels, are used in the pulse pattern. This scheme allows the use of higher switching frequency for a given computation time delay, which results in lower total harmonic distortion (THD) at the output. Control algorithms are derived. The proposed control scheme is implemented using a TI TMS320C14 DSP controlling an inverter to produce a very low THD sinusoidal output voltage. Simulation and experimental results are presented to verify the performance