CORDIC based fast algorithm for power-of-two point DCT and its efficient VLSI implementation

—In this paper, we present a coordinate rotation digital computer (CORDIC) based fast algorithm for power-of-two point DCT, and develop its corresponding efficient VLSI implementation. The proposed algorithm has some distinguish advantages, such as regular Cooley-Tukey FFT-like data flow, identical post-scaling factor, and arithmetic-sequence rotation angles. By using the trigonometric formula, the number of the CORDIC types is reduced dramatically. This leads to an efficient method for overcoming the problem that lack synchronization among the various rotation angles CORDICs. By fully reusing the uniform processing cell (PE), for 8-point DCT, only four carry save adders (CSAs)-based PEs with two different types are required. Compared with other known architectures, the proposed 8-point DCT architecture has higher modularity, lower hardware complexity, higher throughput and better synchronization.     

VLSI Implementation of Forward Error Control Technique for ATM Networks

In asynchronous transfer mode (ATM) networks, fixed length cells of 53 bytes are transmitted. A cell may be discarded during transmission due to buffer overflow or a detection of errors. Cell discarding seriously degrades transmission quality. The quality degradation can be reduced by employing efficient forward error control (FEC) to recover discarded cells. In this paper, we present the design and implementation of decoding equipment for FEC in ATM networks based on a single parity check (SPC) product code using very‐large‐scale integration (VLSI) technology. FEC allows the destination to reconstruct missing data cells by using redundant parity cells that the source adds to each block of data cells. The functionality of the design has been tested using the Model Sim 5.7cXE Simulation Package. The design has been implemented for a 5 ° 5 matrix of data cells in a Virtex‐E XCV 3200E FG1156 device. The simulation and synthesis results show that the decoding function can be completed in 81 clock cycles with an optimum clock of 56.8 MHz. A test bench was written to study the performance of the decoder, and the results are presented.     

Shaped offset quadrature phase shift keying (SOQPSK) modulation scheme and its application in optical wavelength-division multiplexed (DWDM) transmission

This paper presents a new quaternary modulation scheme called SOQPSK. The principle on the optical SOQPSK generation is derived and analyzed, which is implemented by traditional Mach–Zehnder modulators. The performance of the optical SOQPSK modulated system is evaluated and compared with those of quadrature phase shift keying (QPSK) and offset QPSK (OQPSK) modulation systems via simulation, in terms of spectral efficiency, receiver sensitivity and density DWDM transmission performance. Simulations show that the novel modulation scheme improves spectral efficiency for DWDM transmission and provides better transmission performance than QPSK.     

Design and implementation of a low-cost multiple-range digital phase detector

The feasibility of a multiplex system based on the unique properties of solitons hoe been, successfully demonstrated. The system is composed of non-linear LC networks which are equivalent to a one-dimensional anharmonic lattice, and we have investigated experimentally the recurrence phenomena for a pair of soliton trains of which the amplitudes are independently modulated. The recurrence phenomena could be used for secure communications.     

An Analytical Approximation for the Pull‐Out Frequency of a PLL Employing a Sinusoidal Phase Detector

The pull‐out frequency of a second‐order phase lock loop (PLL) is an important parameter that quantifies the loop's ability to stay frequency locked under abrupt changes in the reference input frequency. In most cases, this must be determined numerically or approximated using asymptotic techniques, both of which require special knowledge, skills, and tools. An approximating formula is derived analytically for computing the pull‐out frequency for a second‐order Type II PLL that employs a sinusoidal characteristic phase detector. The pull‐out frequency of such PLLs can be easily approximated to satisfactory accuracy with this formula using a modern scientific calculator.     

Design of a PLL with improved locking range and its biomedical applications

This paper describes a phase locked loop employing a low voltage VCO using modified ECL inverter cells. The VCO circuit employed, features a positive feed back scheme to improve the operating frequency. The phase detector used in the PLL also uses a positive feedback scheme to improve the locked range and to reduce supply voltage of operation of the entire circuit. An improvement of locked range of around 35% was obtained from circuit simulation (using PSPICE) as well as from practical circuit, using discrete components. The minimum supply voltage required here is 2.5 volts. Some biomedical applications of this PLL are also proposed.     

Hardware implementation of a novel water marking algorithm based on phase congruency and singular value decomposition technique

The effortless accessibility of digital information and the simplicity of the digital systems have left the contents over the digital media extremely insecure. Digital watermark based information hiding is a prospective means for copyright protection, authentication, integrity verification and intellectual property right protection. Phase congruency technique works on the principle that perceptually significant image features have effect at spatial locations, where the essential Fourier components are maximally in phase with one another. An adaptive digital watermarking algorithm for better performance in multi-parametric solution space is developed here for hiding the copyright information by means of phase congruency and singular value decomposition supported information hiding technique. Performance evaluation of the algorithm is performed using simulation in Matlab in terms of Peak Signal to Noise Ratio, Structural Similarity Index Metrics, and Normalized Cross correlation index. Hardware realization up to the register transfer logic schematic level has been performed using high performance field programmable gate array board. The device utilization is 26% only, the dynamic power consumption of the circuit is 5.029 mW and delay after clock is 1.539 ns only. The experimental analysis establishes better robustness of the proposed algorithm as it stands against various attacks along with better data hiding capacity.     

Architecture design,performance analysis and VLSI implementation of a reconfigurable shared buffer for high‐speed switch/router

Modern switches and routers require massive storage space to buffer packets. This becomes more significant as link speed increases and switch size grows. From the memory technology perspective, while DRAM is a good choice to meet capacity requirement, the access time causes problems for high‐speed applications. On the other hand, though SRAM is faster, it is more costly and does not have high storage density. The SRAM/DRAM hybrid architecture provides a good solution to meet both capacity and speed requirements. From the switch design and network traffic perspective, to minimize packet loss, the buffering space allocated for each switch port is normally based on the worst‐case scenario, which is usually huge. However, under normal traffic load conditions, the buffer utilization for such configuration is very low. Therefore, we propose a reconfigurable buffer‐sharing scheme that can dynamically adjust the buffering space for each port according to the traffic patterns and buffer saturation status. The target is to achieve high performance and improve buffer utilization, while not posing much constraint on the buffer speed. In this paper, we study the performance of the proposed buffer‐sharing scheme by both a numerical model and extensive simulations under uniform and non‐uniform traffic conditions. We also present the architecture design and VLSI implementation of the proposed reconfigurable shared buffer using the 0.18 µm CMOS technology. Our results manifest that the proposed architecture can always achieve high performance and provide much flexibility for the high‐speed packet switches to adapt to various traffic patterns. Furthermore, it can be easily integrated into the functionality of port controllers of modern switches and routers. Copyright © 2008 John Wiley & Sons, Ltd.     

A voltage-controlled oscillator with an ultra-low supply voltage and its application to a fractional-N phase-locked loop

With feature size scaling, the supply voltage of digital circuits is becoming lower and lower. As a result, the supply voltage of analogue and RF circuits must also be reduced for system on chip (SoC) realisation. This article proposes an ultra-low-supply voltage-controlled oscillator (ULSVCO) and designs a sigma–delta fractional-N frequency synthesiser which adopts such ULSVCO. A mathematical phase-noise model is built here to describe the noise performance of the low-supply voltage-controlled oscillator (VCO). The substrate of the cross-coupled NMOSFETs in the proposed ULSVCO is not grounded but connected to the supply to further reduce the supply voltage. Implemented in 0.18 μm CMOS technology, the proposed ULSVCO can be operated at a supply voltage as low as 0.41 V, the central frequency is set to 1.55 GHz, the phase noise is ?116 dBc/Hz@1.0 MHz. The minimum supply voltage is decreased by about 11% after our idea is adopted and the power consumption of the ULSVCO is only 1.04 mW. With the proposed ULSVCO, we design a sigma–delta-modulator (SDM) fractional-N phase-locked loop frequency synthesiser, which has a 1.43–1.75 GHz frequency tuning range. When the loop bandwidth is set to 100 KHz, the phase noise of our PLL is ?110 dBc/Hz@1.0 MHz.     

多天线信号合并中相位加权值的修正查表算法及FPGA实现

针对白码查表法的储存器利用效率不高问题,给出了一种改进的基于非线性编码的算法和流水线结构,并通过VHDL语言编程,在FPGA上加以实现.仿真结果表明,与白码查表法的计算结果进行比较,非线性编码查表法提高了查表精确度,降低了查找表的大小,便于FPGA实现.     

VLSI implementation of a new LMS-based algorithm for noise removal in ECG signal

Least mean square (LMS)-based adaptive filters are widely deployed for removing artefacts in electrocardiogram (ECG) due to less number of computations. But they posses high mean square error (MSE) under noisy environment. The transform domain variable step-size LMS algorithm reduces the MSE at the cost of computational complexity. In this paper, a variable step-size delayed LMS adaptive filter is used to remove the artefacts from the ECG signal for improved feature extraction. The dedicated digital Signal processors provide fast processing, but they are not flexible. By using field programmable gate arrays, the pipelined architectures can be used to enhance the system performance. The pipelined architecture can enhance the operation efficiency of the adaptive filter and save the power consumption. This technique provides high signal-to-noise ratio and low MSE with reduced computational complexity; hence, it is a useful method for monitoring patients with heart-related problem.     

数字全息变焦系统测量液晶空间光调制器相位调制特性

针对液晶空间光调制器(LC-SLM)应用于光信息处理等诸多领域的前提是必须准确测量出其相位调制特性曲线,本文利用全息干涉计量原理和数字全息变焦系统,提出了一种测量LC-LSM相位调制特性曲线的新方法,只需拍摄两幅数字全息图就能获得完整的相位调制特性曲线,并能够消除系统误差,从而降低对光学元件和调试精度的要求,且不需要完成衍射计算。介绍了相关的测量原理,给出了具体的实验测量过程、计算方法,实验结果表明,本文方法具有系统简单、可以消除系统误差和快速的优点。     

基于DDS技术L波段小步进低相噪频率源设计与实现

将DDS技术应用于超短波射频通信频率源中,比较了几种常见的小步进频率源的设计方案,设计实现了一种"锁相环-直接数字频率合成器-锁相环"(PLL+DDS+PLL)结构的高性能频率源。与传统的频率源设计相比,新的设计更能够满足工程应用过程中小步进、低相噪、高集成度的需求;设计频率源输出频率范围为1 766.5~1 771.5 MHz,步进0.000 5 Hz,相位噪声在距输出频率10 k Hz处小于–95 d Bc,杂散抑制度优于70 d Bc。     

Ultra low power phase detector and phase-locked loop designs and their application as a receiver

In this paper, we present a new low power down-conversion mixer design with single RF and LO input topology which consumes 48 μW power. Detailed analysis of the mixer has been provided. Using the presented mixer as a phase-detector, a low power phase-locked loop (PLL) has been designed and fabricated. A PLL based receiver architecture has been developed and analyzed. The circuit has been fabricated through 0.13 μm CMOS technology. Dissipating 0.26 mW from a 1.2 V supply, the fabricated PLL can track signals between 1.62 and 2.49 GHz. For receiver applications, the energy per bit of the receiver is only 0.26 nJ making it attractive for low power applications including wireless sensor networks.     

双极工艺用于立体声解调的线性锁相环的设计

设计了一种1.5μm双极工艺用于FM广播立体声解调的锁相环。锁相环中鉴相器由传统的吉尔伯特单元电路转变成上下对称的双开关电路,这样增加了鉴相灵敏度和鉴相范围。环路中增加了直流放大器单元,可很方便地通过调整其增益,来调整环路的阻尼系数,使环路在稳定性,锁定时间,噪声带宽方面做了很好的折中。从电路上实现了晶体压控振荡器的设计。锁相环路中的压控振荡器采用Q值很高的晶体做谐振网络,这样既可以保证窄带锁相环所具有的很高的Q值,也可以降低压控振荡器的相位噪声。     

Speed enhancement of a class of digital phase locked loops (DPLLs) by dynamic gain control technique

A dynamic gain modification algorithm of a class of digital phase locked loops (DPLLs) has been proposed. It has been shown analytically that the modified DPLL based on the proposed algorithm can be designed to have a faster transient response besides having steady-state response and frequency acquisition range same as that of a conventional DPLL. Numerical simulation results have been given to support the analytical predictions.     

基于V/F变换下的数字相敏检测监控光学膜厚

本文采用基于电压-频率变换(V/F)的数字相敏检测技术应用于光学监控信号检测,得到的被检测信号的幅度,即光学监控信号波形.而且针对光学监控系统中被检测信号特点,从理论分析角度说明了本方案抑制被检测信号低次谐波和白噪声的性能.仿真分析中针对加入了2,3,4次谐波和零均值随机白噪声,信噪比为20dB,频率为166Hz的被检测信号,利用本方案检测出光学监控信号反射率最大误差＜0.2%.分别利用本方案检测出的光学监控信号和理想监控信号读取反射率极值点对应薄膜厚度,对比可知采用本方案监控膜厚理论误差＜2nm.     

2.488 Gbit/s时钟数据恢复电路的设计

利用Cadence集成电路设计软件,基于SMIC 0.18 μm 1P6M CMOS工艺,设计了一款2.488 Gbit/s三阶电荷泵锁相环型时钟数据恢复(CDR)电路.该CDR电路采用双环路结构实现,为了增加整个环路的捕获范围及减少锁定时间,在锁相环(PLL)的基础上增加了一个带参考时钟的辅助锁频环,由锁定检测环路实时监控频率误差实现双环路的切换.整个电路由鉴相器、鉴频鉴相器、电荷泵、环路滤波器和压控振荡器组成.后仿真结果表明,系统电源电压为1.8V,在2.488 Gbit/s速率的非归零(NRZ)码输入数据下,恢复数据的抖动峰值为14.6 ps,锁定时间为1.5μs,功耗为60 mW,核心版图面积为566 μm×448μm.     

变换域通信系统QAM调制及抗干扰性能仿真

针对变换域通信系统现有调制方式频谱效率较低的情况,提出了在变换域通信系统中实现QAM调制(TD-QAM)的方法。基于MATLAB,验证了TD-QAM的正确性,仿真了TD-QAM在部分频带干扰下的性能。结果表明,所提出的TD-QAM差错概率与常规数字QAM调制一致,同时具备较强的抗部分频带干扰的能力。     

Design and implementation of a scalable switch architecture for efficient high‐speed data multicasting

This paper presents the design and implementation of a new scalable cell‐based multicast switch fabric for broadband communications. Using distributed control and modular design, the multicast balanced gamma switch features a scalable, high performance architecture for unicast, multicast and combined traffic under both uniform and non‐uniform traffic conditions. The important design characteristic of the switch is that a distributed cell replication function for multicast cells is integrated into the functionality of the switch element with the self‐routing and contention resolution functions. Thus, no dedicated copy network is required. In the paper, we discuss in detail the design issues associated with the multicast functionality of the switch using 0.18 µm CMOS technology and discuss the scalability of the switch in terms of architectural, implementation, and performance scalability. Synthesized results are provided for measures of circuit complexity and timing. Copyright © 2006 John Wiley & Sons, Ltd.