低相位噪声CMOS环形压控振荡器的研究与设计

针对个人电脑和通讯系统对频率合成器中振荡器的低相位噪声的要求,对基本的环形振荡器结构进行改进,设计了两种宽带低相位噪声CMOS环形压控振荡器(VCO),在800 MHz振荡频率、1 MHz频偏下,测试的相位噪声分别为-123 dBc/Hz和-110 dBc/Hz.两个VCO的调谐范围分别为450～1 017 MHz和559～935 MHz.     

基于功率谱FFT的BPSK信号参数估计

针对低信噪比环境下二相编码(BPSK)信号参数估计的问题,该文提出一种基于功率谱FFT的信号参数估计算法。该算法根据信号功率谱傅里叶变换得到的幅度谱和相位谱与各参数之间的关系,实现BPSK信号的码元宽度、载频和码长估计。该算法对功率谱继续做傅里叶变换可以进一步消除噪声对估值的影响,更适合在低信噪比环境下实现参数的估计,且计算简单易于实现。仿真试验证明了该算法的准确性和抗噪性,在信噪比为-10 dB时BPSK信号的载频和码元宽度估计正确率分别比循环谱算法提高了9.9%和190.9%。     

An Analytical Approximation for the Pull‐Out Frequency of a PLL Employing a Sinusoidal Phase Detector

The pull‐out frequency of a second‐order phase lock loop (PLL) is an important parameter that quantifies the loop's ability to stay frequency locked under abrupt changes in the reference input frequency. In most cases, this must be determined numerically or approximated using asymptotic techniques, both of which require special knowledge, skills, and tools. An approximating formula is derived analytically for computing the pull‐out frequency for a second‐order Type II PLL that employs a sinusoidal characteristic phase detector. The pull‐out frequency of such PLLs can be easily approximated to satisfactory accuracy with this formula using a modern scientific calculator.     

GPS射频接收芯片中低功耗压控振荡器的设计

设计了一种应用于GPS射频接收芯片的低功耗环形压控振荡器.环路由5级差分结构的放大器构成.芯片采用TSMC 0.18 μm CMOS工艺,核心电路面积0.25 mm×0.05 mm.测试结果表明,采用1.75 V电源电压供电时,电路的功耗约为9.2 mW,振荡器中心工作频率为62 MHz,相位噪声为-89.39 dBc/Hz @ 1 MHz,该VCO可应用于锁相环和频率合成器中.     

低相位噪声微波锁相频率源设计

介绍了一种用单片机控制的微波锁相频率源的设计思想、设计方法以及实验测试结果。在对锁相技术（PLL）研究的基础上，从理论上提出了锁相源对参考晶振的指标要求，分析了单片机对输出信号频谱纯度的影响，总结设计中需要注意的几个问题，并提出相应的解决方案，使锁相频率源的性能指标达到最佳状态。     

低相噪超多频段VCO宽带锁相环的研究

为了解决宽带锁相环设计中相位噪声和输出频率范围的矛盾,分析并设计了一种基于超多频段压控振荡器(VCO)锁相环的方案。该方案通过降低VCO的频率灵敏度和每个VCO 配置LC矩阵等效多个VCO的方法,使VCO在保证输出的频率范围的同时,优化了相位噪声。实验结果发现,该方案可以使锁相环在保证较大的输出频率范围前提下拥有更低的相位噪声。     

宽带VCO自动幅度控制电路中检幅电路的设计

设计了一种新型的幅度检测器用于宽带CMOSVCO的自动幅度控制电路中,通过AAC确保了VCO在整个带宽内能够可靠的起振,同时,新的幅度检测器解决了传统幅度检测电路导致的VCO相位噪声恶化的问题。基于Chartered0.25μm CMOS工艺的测试结果表明,在AAC电路运用新型的检幅电路后,VCO在全波段能够可靠起振同时获得较好的相位噪声特性,偏移中心频率10k处的相噪能改善6dBc。     

The Economical PAPR Minization Scheme for Combinative Coding Technique Applied OFDM Communication System

In this paper, we propose a new combinative scheme to combine with parity check and block coding methods for the reduction of the peak to average power ratio (PAPR) of orthogonal frequency division multiplexing (OFDM) system. In the proposed schemes, the simulation results shown that Peak-to-Average Power Ratio (PAPR) can be reduced by 3.502 dB. The results of this mapped can be shown that PAPR is reduced. The principle of the scheme is illustrated with the specific example of an eight-carriers signal and its computer simulation results. All simulation results have compare with ideal channel case and AWGN case separately; both of cases are shown the PAPR reduced indeed. Do Horng Guo received his B.S. Degree in Electronic Engineering from National Taiwan Marine Science University, Keelung, Taiwan, in 1983, and M.S. Degree in Computer Communication from Northrop University, Los Angeles, USA, in 1986. He is enrolled in Ph.D program in Graduate Institute of Communication Engineering of Tatung University from 2001. His current interest includes wireless communication system and digital signal processing. Chau-Yun Hsu received his B.S. degree M.S. and Ph.D in Electrical Engineering from Tatung Institute of Technology, Taipei, Taiwan, in 1981, 1983 and 1988, respectively. He was the lecturer in Department of Electrical Engineering of Tatung University from 1983 to 1985. From 1988 to 1997, he served as the Associate professor of Tatung University. Since 1998, he has been the Chair Professor of Graduate Institute of Communication Engineering of Tatung University. Now he is also the chair of department of Electrical Engineering of Tatung University. His current interest includes Wireless Channel Model and Estimation, Machine Learning, Digital Signal Processing and Image Processing.     

一种多载波OFDM-UWB无线通信系统

在对超宽带(UWB)技术中的MB-OFDM-UWB系统进行研究分析的基础上,提出了一种基于BPSK调制的MB-OFDM-UWB发送接收系统,并对发送机和接收机的工作原理进行了详细的阐述,给出了相应的数学描述公式.     

宽带锁相环中的快速频带切换电路

首先讨论了普通频带切换电路及使用它的锁相环的电路结构,指出了其存在切换频带时间较长的问题,进而提出并分析了一种改进的频带切换电路。该电路在锁相环切换频带时,产生与输入参考时钟同步的复位信号用于复位鉴频鉴相器(PFD)和环路分频器,从而加快了锁相环频带的切换。该电路基于smicRF 0.18μm 1.8V CMOS工艺设计和流片验证,测试结果显示与普通频带切换电路相比,改进的频带切换电路明显的减少了频带切换时间。     

A voltage-controlled oscillator with an ultra-low supply voltage and its application to a fractional-N phase-locked loop

With feature size scaling, the supply voltage of digital circuits is becoming lower and lower. As a result, the supply voltage of analogue and RF circuits must also be reduced for system on chip (SoC) realisation. This article proposes an ultra-low-supply voltage-controlled oscillator (ULSVCO) and designs a sigma–delta fractional-N frequency synthesiser which adopts such ULSVCO. A mathematical phase-noise model is built here to describe the noise performance of the low-supply voltage-controlled oscillator (VCO). The substrate of the cross-coupled NMOSFETs in the proposed ULSVCO is not grounded but connected to the supply to further reduce the supply voltage. Implemented in 0.18 μm CMOS technology, the proposed ULSVCO can be operated at a supply voltage as low as 0.41 V, the central frequency is set to 1.55 GHz, the phase noise is ?116 dBc/Hz@1.0 MHz. The minimum supply voltage is decreased by about 11% after our idea is adopted and the power consumption of the ULSVCO is only 1.04 mW. With the proposed ULSVCO, we design a sigma–delta-modulator (SDM) fractional-N phase-locked loop frequency synthesiser, which has a 1.43–1.75 GHz frequency tuning range. When the loop bandwidth is set to 100 KHz, the phase noise of our PLL is ?110 dBc/Hz@1.0 MHz.     

一种高工作频率、低相位噪声的CMOS环形振荡器

采用全开关状态的延时单元和双延时路径两种电路技术设计了一种高工作频率、低相位噪声的环形振荡器。环路级数采用偶数级来获得两路相位相差90°的正交输出时钟,芯片采用台湾TSMC0.18μmCMOS工艺。测试结果表明,振荡器在5GHz的工作频率上,在偏离主频10MHz处相位噪声可达-89.3dB/Hz。采用1.8V电源电压时,电路的功耗为50mW,振荡器核芯面积为60μm×60μm。     

基于片上变压器的3.16-7GHz CMOS压控振荡器设计

摘要：本文基于片上变压器的四阶谐振腔实现宽带低相位噪声压控振荡器设计。与传统的宽带压控振荡器相比,在不影响相位噪声性能的情况下能获得几乎2倍于LC-VCO的频率调谐范围,缓和了频率调谐范围与相位噪声之间的限制关系。对变压器的耦合系数与频带选择以及品质因数之间的关系进行了详细的分析。与传统的八边形结构相比,变压器采用圆形共面非对称的中心抽头结构,Q值较高,相位噪声较低。本文采用TSMC 0.18μm工艺实现,在低频和高频模式下输出频率分别覆盖3.16~4.64GHz和4.5~7.01GHz,可实现3.16~7.01GHz连续频率调节,频率调谐范围达75%。在1.8 V供电电压下,消耗直流电流在高频和低频模式下分别为6.3和4.9mA。在载频3.1, 4.5, 5.1, 和 6.6GHz处频相位噪声分别为-122.5, -113.3, -110.1, 和 -116.8dBc/Hz。芯片面积为1.2 mm×0.62mm。     

A 0.7 V 6.66–9.36 GHz wide tuning range CMOS LC VCO with small chip size

The circuit designs are based on TSMC 0.18 μm CMOS standard technology model. The designed circuit uses transformer coupling technology in order to decrease chip area and increase the Q value. The switched-capacitor topology array enables the voltage-controlled oscillator (VCO) to be tuned between 6.66 and 9.36 GHz with 4.9 mW power consumption at supply voltage of 0.7 V, and the tuning range of the circuit can reach 33.7%. The measured phase noise is ?110.5 dBc/Hz at 1 MHz offset from the carrier frequency of 7.113 GHz. The output power level is about ?1.22 dBm. The figure-of-merit and figure-of-merit-with-tuning range of the VCO are about ?180.7 and ?191.25 dBc/Hz, respectively. The chip area is 0.429 mm² excluding the pads. The presented ultra-wideband VCO leads to a better performance in terms of power consumption, tuning range, chip size and output power level for low supply voltage.     

Reliability analysis of MOS varactor in CMOS LC VCO

The paper investigates the reliability of MOS varactor tuned voltage-controlled oscillators (VCO). Due to the stress induced threshold voltage shift of the MOS varactor, the resonant tank degrades and the center frequency and phase noise of VCO deviate. The behavior is modeled and an adaptive body biasing scheme is proposed to make VCO resilient to reliability. In the mean time it does not degrade the VCO performance. An LC VCO at 24 GHz carrier frequency with adaptive body biasing is compared with VCO without such biasing design in PTM 65 nm technology. The ADS simulation results show that the biasing design helps improve the robustness of the VCO in resonant frequency. The design reduces the frequency sensitivity of VCO by 20% when subjected to threshold voltage degradation.     

变压器反馈的超低功耗低相位噪声CMOSLC-VCO设计

设计了一种全集成交叉耦合变压器反馈的LC压控振荡器(LC-VCO),该VCO在电源电压低于阈值电压的情况下实现了超低功率消耗和低相位噪声.该超低功耗的VCO采用SMIC 0.18μm数模混合RF 1P6M CMOS工艺进行了流片验证.测试结果表明:电路在0.4V电源供电和工作频率为2.433GHz时,相位噪声为-125.3dBc/Hz(频偏1MHz),核心直流功耗仅为720μW.芯片的工作频率为2.28～2.48GHz,调谐范围为200MHz(8.7%),电路的优值为-193.7dB,信号的输出功率约为1dBm.该VCO完全可以满足IEEE 802.11b接收机的应用要求.     

基于功率谱离散余弦变换的BPSK信号参数估值

该文针对低信噪比环境下二相编码(BPSK)信号参数估值问题,提出一种基于功率谱离散余弦变换(DCT)的BPSK信号参数估值方法。该方法利用DCT的能量集中特性,通过对提取到的BPSK信号功率谱进行离散余弦变换(DCT)和阈值处理可以得到BPSK信号的码长估计。再进行逆离散余弦变换,可以进一步实现对BPSK信号功率谱的降噪处理,消除噪声对估值的影响,进而利用功率谱特征实现对载频和子脉冲宽度的准确估计。实验表明,该方法在低信噪比环境下,可以准确地识别出BPSK信号的码长和对BPSK信号载频和子脉冲宽度的精确估计,并在信噪比时,较对比方法载频和子脉冲宽度的估值准确率分别提高了22.1%和28.3%。