基于改进型ADPLL的频合器设计与实现

本文采用VHDL语言完成了基于改进型全数字锁相环(ADPLL)的频率合成器设计与实现。本设计使用自适应数字分频器克服了锁相环同步带的限制。频率合成器的输入信号频率从1Hz到10MHz范围,输出信号相位以输入信号为基准,输出信号频率从1Hz到10MHz由用户设定,频率分辨率为1Hz。输出信号与输入信号的最大相差可控,输出信号频率的最大频差可控。     

ANALYSIS OF WAVEFORM ERRORS IN MILLIMETER-WAVE LFMCW SYNTHETIC APERTURE RADAR

In remote sensing applications, there is a special interest in the lightweight, cost effective, and high resolution imaging sensors. The combination of linearly frequency modulated continuous wave (LFMCW) technology and synthetic aperture radar (SAR) technique can lead to such a sensor. This paper concentrates on the analysis of waveform errors in millimeter-wave (MMW) LFMCW SAR. The generating scheme of millimeter-wave LFMCW waveforms with phase locked loop (PLL) and direct digital synthesizer (DDS) combined frequency synthesizer is investigated. The impacts of quantization errors, spurs, and frequency nonlinearities are analyzed. Simulation results show that the quality of LFMCW waveforms has a direct influence on the SAR images. Hence a scheme of frequency synthesizer to achieve high performance MMW LFMCW waveform is proposed. This synthesizer driven by a DDS array can adaptive suppress the spurious level without degradation of excellent frequency linearity and fast switching speed.     

The fractional frequency synthesizer with coincidence mixer

In this paper, a fractional frequency synthesizer architecture is proposed, employing a new mixer based on signal coincidence, which achieves fast-settling, and high resolution compared with the direct frequency synthesizer based on diophantine equations. This new coincidence mixer, using digital error correction techniques, requires no output filters where sum and difference of input signal frequencies are obtained directly by separated outputs. Besides some examples, related to synthesizers the simulations are performed by using Matlab. The new coincidence mixer is also realized and the measuring results are also given.     

宽带PCSF雷达信号频率合成器的设计与实现

基于脉内相位编码脉间频率步进（PCSF）雷达信号的特点,提出了利用复杂可编程逻辑器件、直接数字频率合成器（DDS）和锁相环倍频器产生任意PCSF雷达信号的方法,并实际构造了一个宽带、低噪声的S波段PCSF信号源。利用该方法可以实现对输出信号相位的精确控制,通过选择DDS输出信号的频率范围可以减少带内的杂散分量。测试结果表明：该频率源在320 MHz带宽内的无杂散动态范围为62 dBc,相位噪声为-110 dBc/Hz@1 kHz。     

Ka 波段应用的捷变频高频率分辨率频率合成器

传统基于锁相环(PLL)实现带宽信号输出的频率合成方案,常常为了获得高输出频率而降低频率分辨率和缩短跳频时间。相较而言,基于直接数字频率合成器(DDS)实现带宽信号输出的频率合成方案,其频率分辨率更高,跳频时间更快。然而,DDS 输出频率低,须经多次混频或倍频操作以提升输出频率,对频率源中的滤波器设计造成极大压力,并且这种压力随着频率源输出频率的升高而不断上升。对此,基于高性能、小型化无源滤波器的设计能力,实现了基于DDS 变频的34-35GHz 捷变频、高频率分辨率频率源。实验结果表明,其工作相位噪声优于-85dBc/Hz@1kHz,杂散和谐波抑制优于45 dBc,频率分辨率达到1.86Hz,跳频时间最快4ns。     

一种C波段跳频频率源设计

采用直接数字频率合成激励锁相环方案,基于现场可编程门阵列串行高速控制方式,设计并实现了一种低杂散、低相位噪声的C波段雷达跳频频率源。通过对有源环路滤波器参数和印制电路板的优化设计,使相位噪声和杂散等关键指标得到了极大改善。对系统设计方案、m序列发生器、跳频时间和相位噪声模型做了详细的理论分析和估算。测试结果表明：在7.5 GHz处,相位噪声≤-100 dBc/Hz@100 kHz,杂散电平≤-65 dBc,跳频时间≤10 μs,输出功率>10 dBm,实测结果满足产品的设计指标要求。     

基于Delta-Sigma技术的直接数字频率发生器的设计

直接数字频率合成技术(DDFS)具有很好的频率渐变与很高的频率分辨率,然而该技术却伴随着严重的谐波噪声,主要的谐波噪声是相位截断噪声。该文将介绍一种新型的DDFS结构,该结构采用了Delta-Sigma噪声整形技术,有效地减少由相位截断引入的噪声。经测试,信号的信噪比可以大于60dB,同时减小了硬件的复杂性。     

一种新颖的高速宽带频率合成器设计方法

高速宽带频率合成器是现代电子战系统的关键技术之一。采用锁相频率合成、数字频率合成与直接频率合成相结合的混合频率合成技术,可实现高速、高稳定度、大带宽、低杂散、低相噪的频率合成。混合频率合成技术可广泛运用于现代电子战系统的频率合成器设计中。     

C波段小型化低相噪全相参频率综合器

提出了一种小型低相噪、低杂散的C波段全相参频率综合器设计方案。基带信号由DDS芯片产生,通过对环路滤波器和电路印制板的优化设计改善相噪和杂散性能,并与PLL输出的C波段点频信号进行上变频,得到所需信号。介绍了实现原理、相位噪声模型及设计方法。测试结果表明,在7.8GHz处,频综相位噪声≤-103dBc/Hz@100kHz,杂波抑制≤-61dBc。     

A new PLL frequency synthesizer with high switching speed

A phase-locked loop (PLL) frequency synthesizer with high switching speed is proposed. Mobile communication networks are evolving towards microcellulars operating in narrowband TDMA and microwave bands to meet the rapidly increasing demands for both voice and data services. Therefore, synthesizers with high switching speed are required for the realization. However, it will be difficult for conventional synthesizers to provide switching times of shorter than 1 ms. The PLL synthesizer proposed is composed entirely of digital signal processors except for a voltage-controlled oscillator (VCO). The VCO control signal is derived by the subtraction of the linear reference phase and the feedback phase; therefore, it does not need the band-limited loop filter which limits the ability of the loop to switch fast. The experimental results show that it can provide switching times as short as 0.1 ms, which is 10²~10³ times higher than conventional PLL synthesizers, and spurs of less than -60 dB     

一种具有相位噪声跟踪补偿的全数字锁相环频率合成器

为了实现频率合成器中的相位噪声跟踪补偿和降低全数字锁相环的复杂性,本文提出了一种新的基于全数字锁相环的频率合成器。它采用了一种低复杂度的数字鉴频鉴相器和非线性相位/频率判决电路以及数控振荡器,从而显著降低了硬件复杂性。同时结构中采用的非线性相位和频率判决电路能够很好地实现噪声跟踪和快速的相位/频率捕获,数控振荡器能够获得高的频率分辨率(大约6kHz)和大的线性频率调谐范围。通过采用90nm CMOS工艺制造的ADPLL实验结果表明,本文所提出的基于全数字锁相环的频率合成器能够实现从100kHz到6MHz的可控环路带宽和相当好的带内相位噪声跟踪性能。     

Ramsey-CPT原子频标的高性能小型脉冲微波源研究

根据Ramsey-CPT原子频标对脉冲微波源高性能小型化的要求,采用直接数字频率合成器（DDS）激励锁相环频率合成器,再结合可编程数字功率衰减器和阻抗匹配电路,从而实现具有高稳定度、高分辨率、快跳频速度、低相位噪声、小体积、小步长扫描的脉冲微波源。比较应用于Ramsey-CPT原子频标的脉冲微波源方案,介绍脉冲微波源的基本原理,简述其具体实现方法,并通过仿真优化得到最佳的输出性能。实现的脉冲微波源具有优良的技术性能,进一步提高了Ramsey-CPT原子频标输出频率的性能。同时,达到了设计小型化的要求,有利于Ramsey-CPT原子频标的便携式应用。     

An Approach of Developing High Performance Millimeter-wave Frequency Synthesizer

In this paper, an approach of developing high performance millimeter-wave frequency synthesizer is proposed, which is significantly simpler than the conventional cases. The synthesizer is driven by one triple tuned typed synthesizer, which adjusts the output frequency of DDS and frequency division ratios of variable frequency divider to suppress the spurious level. With the proposed method, a microwave phase locked loop (PLL) PE3236 and a millimeter-wave multiplier HMC283 are also used. Moreover, the PLL is implemented with the form of charge pump followed by a passive three-order low-pass filter which can further suppress the phase noise. Finally, a low spurious level and high frequency resolution millimeter-wave frequency synthesizer without degradation of frequency switching speed is developed. Experimental results show that this method can achieve the performances of low spurious level, low phase noise, and high frequency resolution.     

Architecture of a dual-mode cascaded-loop frequency synthesizer

A new architecture for a frequency synthesizer with adjustable output frequency range and channel spacing is introduced. It is intended for the generation of closely spaced frequency channels in the GHz range while producing minimal spurious phase noise components. The architecture employs two independent phase-locked loops that are driven in cascade by a single reference oscillator. This approach provides fine resolution and wide bandwidth as well as low phase noises. The synthesizer can be operated in either of two different modes: nonfractional and mini-denominator fractional modes. The architecture produces no fractional spurs in the first mode and relatively small phase spurs in the second mode. It is simulated that, in an application to a P-GSM 900 system tuning from 890 to 915 MHz with a channel spacing of 200 kHz, the worst case phase spurs are of −100 dBc at an offset frequency of 833 kHz and the linear frequency-switching settling time (to 0.01% of frequency increments) is of 128 μs.     

A 1.8-GHz CMOS fractional-N frequency synthesizer with randomized multiphase VCO

A 1.8 GHz fractional-N frequency synthesizer implemented in 0.6 /spl mu/m CMOS with an on-chip multiphase voltage-controlled oscillator (VCO) exhibits no spurs resulting from phase interpolation. The proposed architecture randomly selects output phases of a multiphase VCO for fractional frequency division to eliminate spurious tones. Measured phase noise at 1.715 GHz is lower than -80 dBc/Hz within a 20 kHz loop bandwidth and -118 dBc/Hz at 1 MHz offset with no fractional spurs above -70 dBc/Hz. The synthesizer has a frequency resolution step smaller than 10 Hz. The chip consumes 52 mW at 3.3 V and occupies 3.7 mm/spl times/2.9 mm.     

全集成低噪声CMOS宽带分数分频频率综合器

设计了一款应用于CMMB数字电视广播接收的全集成低噪声宽带频率综合器。采用三阶ΣΔ调制器小数分频器完成高精度的频率输出,使用仅一个低相位噪声的宽带VCO输出频率范围覆盖900~1 600 MHz,产生的本振信号覆盖UHF的数字电视频段(470~790 MHz)。设计中的频率综合器能在所有的频道下保证环路的稳定以及最小的环路性能偏差。测试结果表明,整个频率综合器的带内相位噪声小于-85 dBc/Hz,并且带外相位噪声在1MHz时均小于-121 dBc/Hz,总的频率综合器锁定时间小于300μs。设计在UMC 0.18μm RFCMOS工艺下实现,芯片面积小于0.6 mm2,在1.8 V电源电压的测试条件下,总功耗小于22 mW。     

A 700-kHz bandwidth /spl Sigma//spl Delta/ fractional synthesizer with spurs compensation and linearization techniques for WCDMA applications

A /spl Sigma//spl Delta/ fractional-N frequency synthesizer targeting WCDMA receiver specifications is presented. Through spurs compensation and linearization techniques, the PLL bandwidth is significantly extended with only a slight increase in the integrated phase noise. In a 0.18-/spl mu/m standard digital CMOS technology a fully integrated prototype with 2.1-GHz output frequency and 35 Hz resolution has an area of 3.4 mm/sup 2/ PADs included, and it consumes 28 mW. With a 3-dB closed-loop bandwidth of 700 kHz, the settling time is only 7 /spl mu/s. The integrated phase noise plus spurs is -45 dBc for the first WCDMA channel (1 kHz to 1.94 MHz) and -65 dBc for the second channel (2.5 to 6.34 MHz) with a worst case in-band (unfiltered) fractional spur of -60 dBc. Given the extremely large bandwidth, the synthesizer could be used also for TX direct modulation over a broad band. The choice of such a large bandwidth, however, still limits the spur performance. A slightly smaller bandwidth would fulfill WCDMA requirements. This has been shown in a second prototype, using the same architecture but employing an external loop filter and VCO for greater flexibility and ease of testing.     

抑制DDS相位舍位杂散的一种新方法

直接数字式频率合成器(DDS)是最新的频率合成技术,它具有分辨率高,频率转换速度快等优点,但是杂散分量丰富.本文旨在介绍相控阵天线抑制旁瓣的几种方法,并利用其中的随机相位馈相法来处理相位舍位条件下的DDS,从而降低杂散电平.     

DDS的相位截断及相应的杂散信号分析

直接数字频率合成（DDS）的缺点在于输出频率低和存在大量的杂散信号。而杂散信号产生的原因之一就是相位截断。文章首先介绍了DDS的基本结构和原理，总结了产生DDS杂散噪声的来源。重点分析了相位截断误差以及由相位截断引起的杂散频率分量，提出了计算这一杂散频率分量个数及信噪比的方法。