Large-signal subthreshold CMOS transconductance amplifier

A folding architecture for a subthreshold CMOS transconductance amplifier is described. Good linearity is obtained for an extremely large differential input voltage, without loss in the common-mode voltage range. Theoretical noise analysis indicates a 6 dB improvement in the dynamic range compared to a simple single-pair MOS implementation. A prototype has been fabricated in a 2 μm CMOS process, and experimental results are presented     

CMOS low-voltage class-AB operational transconductance amplifier

The authors present a new low-voltage class-AB operational transconductance amplifier (OTA). The proposed OTA achieves a fast non slew-rate limited settling time with low power consumption. The circuit is power efficient when driving large capacitive loads. The OTA circuit is well suited for low-voltage low-power switched capacitor applications. Experimental results of the proposed circuit are included     

A CMOS multi-gain transconductance amplifier and its applications

Transconductance amplifier (g_m) based circuits are attractive due to their inherent programmability features. Single output g_m’s are often replaced by multi-output g_m’s to reduce the number of active devices for a given application. However, this usually results in losing the circuit programmability features. This work shows that this problem can be circumvented through adopting a new programmable multi-gain g_m. The advantages of the proposed multi-gain g_m are demonstrated using two filter design examples. They show that the proposed multi-gain g_m reduces the number of active devices by two-third compared with their single output g_m based counterparts while maintaining their versatile programmability characteristics. Experimental results obtained from a 0.18 μm CMOS process for one of the applications are provided.     

A new CMOS design of high transconductance current follower transconductance amplifier and its applications

In this work, a new CMOS implementation of high transconductance current follower transconductance amplifier (CFTA) is proposed. The proposed CFTA uses current starving technique along with an auxiliary unit (AU) to enhance transconductance performance. The cross-drain-coupled MOSFETs are also used in AU which further enhances transconductance of proposed circuit. The proposed CFTA provides higher transconductance and wider tuning range without affecting its output swing and bandwidth performance. The proposed CFTA provides transconductance of 11.3 mS, dissipates 1.8 mW power and operates at?±?0.6 V supply voltage. A current mode third order quadrature oscillator and biquad filter have been designed and simulated, to validate the performance of proposed circuit. The workability of proposed CFTA and its applications have been verified by using Cadence virtuoso schematic composer with TSMC 0.18 µm process parameters.     

A novel CMOS operational transconductance amplifier based on a mobility compensation technique

This brief describes a new linear operational transconductance amplifier (OTA) and its application to a ninth-order Bessel filter. To improve the linearity of the OTA, we employ a mobility compensation circuit which combines the transistors operating in the triode and the subthreshold regions. The proposed technique enhances the linearity of the transconductance without loss of the input swing range. The proposed OTA shows /spl plusmn/0.5% Gm variation and the total harmonic distortion of less than - 60-dB over the input range of /spl plusmn/0.8-V. The ninth-order Bessel filter employing the proposed OTA has been implemented in a 0.35-/spl mu/m n-well CMOS process under 3.3-V supply voltage. It shows the cutoff frequency of 8 MHz and the power consumption of 65 mW.     

CMOS current-controlled current differencing transconductance amplifier and applications to analog signal processing

This article presents design of a basic current-mode building block for analog signal processing, named as current-controlled current differencing transconductance amplifier (CCCDTA). Its parasitic resistances at two current input ports can be controlled by an input bias current. Owing to working in current-mode of all terminals, it is very suitable to use in a current-mode signal processing, which is continually more popular than a voltage one. The proposed element is realized in a CMOS technology and is examined the performance through PSPICE simulations. They display usability of the new active element, where the maximum bandwidth is 311 MHz. The CMOS CCCDTA performs low power consumption and tuning over a wide current range. In addition, some examples as a current-mode universal biquad filter, floating inductance simulator and quadrature oscillator are included. They occupy only single CCCDTA.     

A CMOS transconductance amplifier architecture with wide tuningrange for very low frequency applications

A pseudodifferential CMOS operational transconductance amplifier (OTA) with wide tuning range and large input voltage swing has been designed for very small G_M's (of the order of a few nanoamperes per volt). The OTA is based on a modified four-quadrant multiplier architecture with current division. A common-mode feedback circuit structure has been proposed and designed using floating-gate transistors to handle large differential signals. Large on-chip capacitors are emulated through impedance scaling circuits. The circuits, fabricated in a 1.2-μm CMOS process, have been used to design a fourth-order bandpass filter and a relaxation oscillator. Experimental results are in good agreement with the theoretical results     

Impedance projection based transconductance amplifier

A current feedback technique is proposed to realise the transposition of grounded impedance to a floating impedance or transconductance. This technique, that can be viewed as an impedance projection, also allows one to implement a new current conveyor topology and to extend applications based on transconductance amplification. A theoretical approach of this new technique using a grounded impedance, two classical transconductance amplifiers and one second generation current conveyor only is presented.     

Low-distortion low-voltage operational transconductance amplifier

A new operational transconductance amplifier (OTA) is proposed, which is based on the flipped voltage follower and source degeneration techniques. The OTA is simulated in a standard TSMC 0.18 μm CMOS process with a 1.8 V supply voltage. The simulation results show that the total harmonic distortion of the proposed OTA is less than 1% up to 0.85 Vp-p.     

Novel single-ended CMOS transconductance amplifiers

Two novel CMOS single-ended amplifiers are presented. Suitable for switched-capacitor-filter designs, they exhibit high gain and bandwidth as well as high PSRR, low power and small size.     

Ultra low-voltage CMOS transconductance amplifiers

Simple and symmetrical ultra low-voltage current mode analog circuits and autozeroing amplifiers are presented. The low-voltage analog circuits are based on low-voltage inverters resembling precharge digital logic. Ultra low-voltage analog circuits can be operated at supply voltages down to 250?mV with rail-to-rail input and output swing. The output current of the ultra low-voltage symmetrical transconductance amplifier can be quite large due to a current boost technique. Ultra low-voltage analog circuits can be operated at supply voltages down to 250?mV with rail- to-rail input and output swing. The current headroom is 3???A and the supply voltage is 300?mV. For supply voltages down to 300?mV simulated data shows that the maximum clock frequency is approximately 600?MHz.     

A 90-nm CMOS Doherty power amplifier with minimum AM-PM distortion

A linear Doherty amplifier is presented. The design reduces AM-PM distortion by optimizing the device-size ratio of the carrier and peak amplifiers to cancel each other's phase variation. Consequently, this design achieves both good linearity and high backed-off efficiency associated with the Doherty technique, making it suitable for systems with large peak-to-average power ratio (WLAN, WiMAX, etc.). The fully integrated design has on-chip quadrature hybrid coupler, impedance transformer, and output matching networks. The experimental 90-nm CMOS prototype operating at 3.65 GHz achieves 12.5% power-added efficiency (PAE) at 6 dB back-off, while exceeding IEEE 802.11a -25 dB error vector magnitude (EVM) linearity requirement (using 1.55-V supply). A 28.9 dBm maximum Psat is achieved with 39% PAE (using 1.85-V supply). The active die area is 1.2 mm/sup 2/.     

Low voltage low power CMOS current differencing buffered amplifier

The major goal of this work is to present a new CMOS realization for the current differencing buffered amplifier (CDBA). A design technique based on flipped voltage follower current sources is preferred to obtain a high performance CDBA. The proposed circuit can operate with the minimum supply voltages of ±0.6 V. It also consumes less power than its counterparts that have been reported so far. Moreover, the proposed CDBA has good voltage and current gain accuracies. For the simulations, UMC 0.18 μm CMOS process is used. The performance of the CDBA is verified with HSPICE. Finally, a second-order, allpass/notch filter configuration is proposed to show the performance and usefulness of the circuit. The results from HSPICE simulations are in remarkable agreement with the expected ones.     

High slew rate current mode transconductance error amplifier for low quiescent current output-capacitorless CMOS LDO regulator

This paper presents a CMOS low quiescent current output-capacitorless low-dropout regulator (LDO) based on a high slew rate current mode transconductance amplifier (CTA) as error amplifier. Using local common-mode feedback (LCMFB) in the proposed CTA, the order of transfer characteristic of the circuit is increased. Therefore, the slew rate at the gate of pass transistor is enhanced. This improves the LDO load transient characteristic even at low quiescent current. The proposed LDO topology has been designed and post simulated in HSPICE in a 0.18 µm CMOS process to supply the load current between 0 and 100 mA. The dropout voltage of the LDO is set to 200 mV for 1.2–2 V input voltage. Post-layout simulation results reveal that the proposed LDO is stable without any internal compensation strategy and with on-chip output capacitor or lumped parasitic capacitances at the output node between 10 and 100 pF. The total quiescent current of the LDO including the current consumed by the reference buffer circuit is only 3.7 µA. A final benchmark comparison considering all relevant performance metrics is presented.     

Low power high performance CMOS amplifier for epileptic seizure prediction

Analog Integrated Circuits and Signal Processing - For neural recording applications, a low power neural signal acquisition amplifier has been proposed. Since extracellular neural signals are weak...     

Linear CMOS transconductance element for VHF filters

A differential transconductance element based on CMOS inverters is presented. With this circuit a linear, tunable integrator for very high-frequency continuous-time integrated filters can be made. This integrator has good linearity properties (THD<0.04%, V/sub ipp/=1.8 V), nondominant poles in the gigahertz range and a 40 dB DC gain.<>     

一种超宽带伪差分跨导放大器

提出了一种超宽带伪差分运算跨导放大器.该放大器通过共模前馈和共模反馈方法使得运算跨导放大器单元具有更为简单的电路结构,易于设计验证并能够稳定工作在较高频率.以该放大器作为单元电路,可以实现截止频率到达百兆赫兹的高频连续时间滤波器,并作为中频滤波器用于射频接收机中.     

A positive-feedback transconductance amplifier with applications tohigh-frequency, high-Q CMOS switched-capacitor filters

The authors describe a high-bandwidth amplifier that simultaneously achieves high gain by using internal positive feedback. The results obtained when the amplifier is used in a general-purpose switched-capacitor biquadratic building block are also presented. This device achieves 150-kHz center-frequency operation with Q accuracy of 15% when clocked at 7.5 MHz with 10-V ±10% supplies from -55°C to +125°C. With a minimum power supply of 4.5 V, this filter operates with center frequencies up to 100 kHz when clocked at 5 MHz, while performing with the same accuracy and across the same temperature range as above     

A high-voltage bipolar transconductance amplifier for electrotactile stimulation

This paper describes a high-performance transconductance amplifier specifically designed for electrotactile (electrocutaneous) stimulation. It enables voltages up to plusmn600 V to be produced at the output that will allow the psychophysiological performance associated with stimulation of the fingertip using various stimulation waveforms to be studied more thoroughly. The design has a transconductance of up to 20 mA/V, an 8.8-MOmega output resistance, and can provide output currents up to plusmn20 mA. A complete schematic diagram is presented along with a discussion of theory of operation and safety issues as well as performance and derating plots from the implemented design.