Design of improved rail-to-rail low-distortion and low-stress switches in advanced CMOS technologies

This paper describes the efficient design of an improved and dedicated switched-capacitor (SC) circuit capable of linearizing CMOS switches to allow SC circuits to reach low distortion levels. The described circuit (SC linearization control circuit, SLC) has the advantage over conventional clock-bootstrapping circuits of exhibiting low-stress, since large gate voltages are avoided. This paper presents exhaustive corner simulation results of a SC sample-and-hold (S/H) circuit which employs the proposed and optimized circuits, together with the experimental evaluation of a complete 10-bit ADC utilizing the referred S/H circuit. These results show that the SLC circuits can reduce distortion and increase dynamic linearity above 12 bits for wide input signal bandwidths.     

Design of a very linear CMOS transconductance input stage forcontinuous-time filters

A CMOS differential input stage for transconductance amplifiers that combines a low noise excess factor, low input capacitance, and high common-mode rejection ratio with a very good linearity is described. The measured distortion is only 0.2% for a 1-V RMS input signal and only 1% for a 2-V RMS input signal on a test circuit implemented in a standard 3-μm CMOS process, using ±5-V supplies, resulting in over 85 dB of dynamic range. Applications include high-performance continuous-time filters and linear amplifiers     

一种高线性Gm-C复数滤波器的设计

针对低电源电压Gm-C复数滤波器线性度不足的问题,提出了一种使用大信号线性化技术的一阶复数带通滤波器。所提出的复数滤波器使用了不平衡差分对和自适应偏置电路两种线性化技术,通过扩展跨导相对恒定的输入电压范围提高滤波器的线性度。滤波器采用UMC 110 nm CMOS工艺设计,中心频率和带宽分别为2 MHz和1 MHz。Cadence仿真结果显示,在1.2 V电源电压下,滤波器功耗为229μW,镜像抑制比(IIR)为18 dB,线性度(输入三阶交调点IIP3)为9.53 dBm,总谐波失真(THD)为-55.7 dB。该复数滤波器电路结构简单、功耗较低,以期能广泛应用于低电源电压的接收机设计。     

用于减小总谐波失真的乘法器设计

模拟乘法器是实现有源功率因数校正(APFC)的关键模块电路.为了提高APFC电路的性能,在对目前一般芯片中普遍采用校正电路的THD(总谐波失真)较大,导致功率因数较低的原因进行分析研究的基础上,给出了一种高线性度的单像限模拟乘法器,该乘法器在经典的电路结构上加以改进,采用双极型和CMOS混合工艺设计,在德国XFAB工艺厂进行流片.仿真测试和流片结果表明,该乘法器消除了传统的APFC电路总谐波失真较大的缺陷,提高了功率因数,并且没有增加版图面积,具有较高性价比,适合嵌入在中小功率APFC芯片中使用.     

A Low Voltage and Low Power Current-Mode Analog Computational Circuit

A new current-mode analog computational circuit is presented. The circuit can be digitally controlled to produce multiplying, squaring and inverse functions. The design is based on using MOSFETs operating in sub-threshold region to achieve ultra low power dissipation. The circuit is operated from a ±0.75 V DC supply. The proposed circuit has been simulated using Tanner in 0.35-μm TSMC CMOS process. Simulation results confirm the functionality of the circuit. The total power consumption is 2.3 μW, total harmonic distortion is 1.1 %, maximum linearity error is 0.3 % and the bandwidth is 2.3 MHz.     

A highly linear 125-MHz CMOS switched-resistor programmable-gain amplifier

A highly linear programmable-gain amplifier (PGA) is fabricated using a 0.35-/spl mu/m CMOS technology. High linearity and constant wide bandwidth are achieved by using a high-gain amplifier with low input impedance and resistor-network feedback. The voltage gain is varied by digitally controlling the input switched resistors. The distortion of a switched resistor has been analyzed using the Volterra series. The PGA has a voltage gain varying from 0 to 19 dB, while maintaining a constant bandwidth of 125 MHz. The third-order intermodulation distortion is -86dB at 10 MHz. The circuit dissipates 21 mW from a 3.3-V supply.     

A 2-V, low distortion, 1-GHz CMOS up-conversion mixer

A 1 GHz, very linear, CMOS up-conversion mixer is presented. The circuit is able to operate at a 2-V power supply. The topology has a true single-ended output stage which avoids the use of any balun. The total power consumption in both the mixers and the output stage is only 22 mW at 2 V. A profound analysis of the origins of distortion in the mixer has been performed. This study has resulted in the optimization of the linearity of the realized up-conversion mixer. The low power consumption, the low supply voltage, the high frequency performance, and the relatively large amplitude and low distortion single-ended off-chip output signal make the presented topology very suitable for wireless applications     

一种高线性度电压电流转换电路的设计与实现

介绍了利用CSMC 0.6μm CMOS工艺实现的、应用于电流模逻辑电路中的高线性度电压电流转换(VTC)电路。该电路采用了高增益两级运算放大器,以及工作在弱反型区的MOS管电压电流呈指数律关系实现的PTAT基准电流源。详细分析了电阻与运算放大器的非线性影响因素。测试结果表明,输出的总谐波失真为0.0002%,输入动态范围为0～2.6V,输出电流为50～426μA,PTAT基准电流源对电源变化的灵敏度为0.0217。芯片采用5V供电,功耗约为1.3mW,芯片面积为0.112mm2。     

Linear voltage-to-current converters with current reuse technique

This paper proposes a linear voltage-to-cur-rent converter with current reuse technique to reduce circuit power consumption without deteriorating its linearity and bandwidth. The proposed circuit is designed using 0.18???m CMOS process parameters from TSMC. Simulation results show that the total harmonic distortion (THD) of the proposed circuit with a 2.5-V input amplitude is less than 1% for input frequency up to 200?MHz under a 1.8-V supply voltage. The total current consumption is 10.8?mA.     

New Active Digital Pixel Circuit for CMOS Image Sensor

A new active digital pixel circuit for CMOS image sensor is designed consisting of four components: a photo-transducer, a preamplifier, a sample & hold (S & H) circuit and an A/D converter with an inverter. It is optimized by simulation and adjustment based on 2 μm standard CMOS process. Each circuit of the components is designed with specific parameters. The simulation results of the whole pixel circuits show that the circuit has such advantages as low distortion, low power consumption, and improvement of the output performances by using an inverter.     

Intermodulation Distortion in CMOS Attenuators and Switches

Gain control elements are widely used in communication systems both to limit the incident power to the circuitry and to control the amplitude of the transmitted signal. Attenuators are one way of controlling the signal amplitude. The distortion performance of common CMOS attenuator topologies is investigated in this work. CMOS device equations that model the device in different regions of operation and which also model short channel effects are used for calculating distortion performance. Calculated distortion is compared with simulation results and experimental data, and qualitative explanations of the distortion curves as well as the deviation between different sources of data are given. Potential improvements in linearity performance of attenuators via circuit design techniques have also been discussed     

An accurate CMOS sample-and-hold circuit

An accurate sample-and-hold (S/H) circuit implemented with a 2-μm double-poly CMOS process is described. Competitive performance in terms of output swing, linearity, and clock feedthrough compensation was obtained using a new circuit topology. The sample and hold operates up to 1 MHz of sampling frequency with less than -60 dB of total harmonic distortion. The accuracy of the held step is better than 0.2 mV. The circuit dissipates 4 mW with a 5-V power supply     

A 330?MHz 11?bit 26.4?mW CMOS Low-Hold-Pedestal Fully Differential Sample-and-Hold Circuit

A new technique for realizing a very-high-speed low-power low-voltage fully differential CMOS sample-and-hold circuit with low hold pedestal is presented. To achieve high sampling linearity the circuit utilizes linearized input switches. The fully differential design relaxes the trade-off between sampling speed and the sampling precision. The circuit design of major building blocks is described in detail. A prototype circuit in a 0.35-μm CMOS process is designed and experimental results are presented. The sample-and-hold circuit operates up to 330 MHz of sampling frequency with less than −68.3 dB of total harmonic distortion, corresponding to 11 bits for an input 80.24 MHz sinusoidal amplitude of 1.2V _pp at a 3 V supply. This total harmonic distortion measurement reflects the held values as well as the tracking components of the output waveform. In these conditions, a differential hold pedestal of less than 0.8 mV, 0.8 ns acquisition time at 1.2 V step input, and 1.2V _pp full-scale differential input range are achieved. The circuit dissipates 26.4 mW with a 3 V power supply.     

Impedance boosting techniques based on BiCMOS technology

An impedance enhancement technique, based on a combination of bipolar and MOS devices, is presented. The technique uses negative active feedback action to boost the impedance level of a cascode circuit. This technique improves the gain of the conventional folded-cascode BiCMOS amplifier by the loop gain of the feedback loop. The BiCMOS-based impedance boosting circuit, compared to the CMOS version, offers the advantage of higher bandwidth together with higher output current capability. The SPICE simulations of a folded-cascode op amp based on this technique show that a 120 dB DC gain can be achieved. Application of the technique to a transducer resulted in a total harmonic distortion as low as 0.02% with 2 V_p-p input signals and an improvement of more than 10 dB in linearity, with respect to the case where no feedback was used     

Linear transconductor with flipped voltage follower in 130 nm CMOS

This paper presents a modified design method for linear transconductor circuit in 130 nm CMOS technology to improve linearity, robustness against process induced threshold voltage variability and reduce harmonic distortion. Source follower in the adaptively biased differential pair (ABDP) linear transconductor circuit is replaced with flipped voltage follower to improve the efficiency of the tail current source, which is connected to a conventional differential pair. The simulation results show the performance of the modified circuit also has better speed, noise performance and common mode rejection ratio compared to the ABDP circuit.     

A 250 MHz 11 bit 22 mW CMOS low-hold-pedestal fully differential sample-and-hold circuit

A new technique for realizing a very-high-speed low-power low-voltage fully differential CMOS sample-and-hold circuit with low hold pedestal is presented. To achieve high sampling linearity the circuit utilizes improved bootstrapped input switches. The fully differential design relaxes the trade-off between sampling speed and the sampling precision. The circuit design of major building blocks is described in detail. A prototype circuit in a 0.35-μm CMOS process is integrated and experimental results are presented. The sample-and-hold circuit operates up to 250 MHz of sampling frequency with less than −70 dB of total harmonic distortion corresponding to 11 bits for an input 60.8 MHz sinusoidal amplitude of 1.8 V _pp at a 3 V supply. The total harmonic distortion measurement reflects the held values as well as the tracking components of the output waveform. In these conditions, a differential hold pedestal of less than 0.8 mV, 0.8 ns acquisition time at 1.8 V step input, and 1.8 V _pp full-scale differential input range are achieved. The circuit dissipates 22 mW with a 3 V power supply.     

A Compact Four-Quadrant Floating-Gate MOS Multiplier

A compact, four-quadrant analog CMOS multiplier featuring wide dynamic range is presented. The capacitive voltage division obtained by the use of Floating-Gate MOS (FGMOS) transistors, and an accurate wide-swing current mirror based on active bootstrapping, allow a wide input range, low harmonic distortion, and high linearity. Simulation and measurement results for a 0.8 μm CMOS prototype demonstrate the validity of the proposed approach.     

A MOS four-quadrant analog multiplier using the quarter-square technique

A circuit configuration for a four-quadrant analog multiplier in MOS integrated circuit technology is described. It is based on the quarter-square algebraic identity and uses differential summer and differential squaring stages. The multiplier achieves a linearity of 0.44%, a -3-dB bandwidth of 5 MHz, a dynamic range of 87 dB, and a total harmonic distortion of 0.59%. The circuit was fabricated in a 5-/spl mu/m double-polysilicon p-well CMOS process. Typical power consumption is 10 mW. Chip size is 500 mil/SUP 2/.     

1.5 V four-quadrant CMOS current multiplier/divider

A low voltage CMOS four-quadrant current multiplier/divider circuit is presented. It is based on a compact V-I converter cell able to operate at very low supply voltages. Measurement results for an experimental prototype in a 0.8 /spl mu/m CMOS technology show good linearity for a /spl plusmn/15 /spl mu/A input current range and a 1.5 V supply voltage.     

A 100-MHz CMOS wide-band IF amplifier

When the data rates of communication systems increase, wideband IF amplifiers are needed. It is also possible to use a single wideband intermediate frequency (IF) amplifier for a radio band with several narrow-band channels of varying strengths. The linearity is then critical, if intermodulation products are not to disturb weak channels. We try to find a topology for this new amplifier application, suitable for integration in a standard CMOS process. To get low distortion, we use an output stage with high linearity, which is further linearized by feedback in a double-nested Miller configuration. A 0.8-μm standard CMOS IF amplifier design with low distortion up to 20 MHz is presented